Millimeter wave low noise amplifier

Abstract

The utility model provides a millimeter wave low noise amplifier which comprises a first-stage amplifying circuit, a second-stage amplifying circuit and a third-stage amplifying circuit, and the signal output end of the first-stage amplifying circuit is connected with the signal input end of the second-stage amplifying circuit. The signal output end of the second-stage amplification circuit is connected with the signal input end of the third-stage amplification circuit; on the premise that the bandwidth is increased, high gain and low noise can be realized at the same time. (1) the transformer is matched with the inductor and the capacitor in a combined manner, so that the loss of a passive matching circuit is reduced, and meanwhile, large-bandwidth output of the low-noise amplifier is realized; and (2) a cascode amplification structure is adopted, and impedance matching is carried out by combining a transformer, a capacitor and an inductor, so that broadband, high-gain amplification and low-noise signal output can be realized.

Description

Technical Field

[0001] The utility model relates to the technical field of millimeter-wave integrated circuit design, in particular to a millimeter-wave low-noise amplifier. Background Art

[0002] There are significant differences in the performance requirements and technical difficulties of radio frequency integrated circuits in different fields and at different operating frequencies. In practice, in order to meet requirements such as cost performance and operating frequency, many manufacturing processes have emerged, such as BJT, HEMT, BiMOS, CMOS, etc. Although BJT has the advantages of speed and accuracy, it is not suitable for large-scale integration. HEMT, due to its high electron saturation velocity and operating frequency up to sub-millimeter waves, is mostly used for high-speed, high-power, etc. Like BJT, it is suitable for digital integrated circuits. In previous designs, although CMOS has the advantage of low cost, due to process limitations, its cut-off frequency is low and the noise is large, so it is not suitable for the design of radio frequency circuits. However, with the progress of technology and the improvement of microelectronic process technology, the frequency characteristics of CMOS transistors have been gradually improved, greatly stimulating the use of CMOS in the radio frequency field. Compared with processes such as GaAs and BiCMOS, the CMOS process has the advantages of high integration, the lowest cost, and easy integration with digital circuits, providing better conditions for the productization of modules.

[0003] In the design of radio frequency circuits, the low-noise amplifier is a key device of the receiver. The quality of its performance directly affects the sensitivity of the entire receiver. For a low-noise amplifier, the noise figure, gain, etc. are important indicators. The low-noise amplifier receives weak signals from the antenna, amplifies the weak signals, and in order to reduce the influence of the noise of the subsequent circuit on the noise of the entire system, the LNA needs to provide sufficient gain, which is particularly important for the down-conversion circuit. Therefore, how to achieve high gain and low noise has always been a problem to be solved in the design of low-noise amplifiers (LNA).

[0004] The design of low-noise amplifiers generally adopts structures such as common-source, common-gate, and cascode. For a common-source amplifier, it has good gain and noise performance, but has a narrow bandwidth; the common-gate amplifier has broadband characteristics, and the linearity and isolation are also better, but its gain is smaller than that of the common-source structure; the cascode structure is composed of a common-source transistor and a common-gate transistor stacked, equivalent to two-stage amplifiers, and the gain is significantly better than that of the common-source and common-gate amplifiers. Therefore, it is used in the design of high-gain amplifiers, but it requires a higher supply voltage, and its noise is significantly greater than that of the common-source stage amplifier, and has narrowband characteristics. Therefore, using the cascode structure to achieve high gain and low noise is also a problem to be solved.

[0005] In radio frequency circuit design, impedance matching and the reasonable application of passive devices contribute to reducing the noise figure. Impedance matching is a very important design in the circuit, and the inductor is an important passive device in the radio frequency circuit, which plays a key role in impedance matching. However, with the development of technology, on-chip integrated transformers have gradually shown their advantages over traditional inductors, especially in broadband matching.

[0006] In summary, the disclosed low-noise amplifier needs to be improved in the following aspects: (1) When using transformer matching, it is easy to introduce excessive insertion loss while increasing the bandwidth, resulting in the deterioration of noise; (2) It is difficult to achieve a large bandwidth using traditional LC (L is the inductor, C is the capacitor) matching; (3) While achieving high gain with the cascode structure, it is difficult to achieve both high gain and low noise simultaneously. Summary of the Invention

[0007] The present invention aims to at least solve the technical problems existing in the prior art, and particularly innovatively proposes a millimeter-wave low-noise amplifier.

[0008] To achieve the above object of the present invention, the present invention provides a millimeter-wave low-noise amplifier, which includes: a first-stage amplification circuit, a second-stage amplification circuit, and a third-stage amplification circuit. The signal output end of the first-stage amplification circuit is connected to the signal input end of the second-stage amplification circuit, and the signal output end of the second-stage amplification circuit is connected to the signal input end of the third-stage amplification circuit;

[0009] The first-stage amplification circuit includes: a first input matching capacitor, a second input matching capacitor, an input transformer, a first common-source transistor, a second common-source transistor, a first common-source neutralizing capacitor, a second common-source neutralizing capacitor, a first cascode inductor, a second cascode inductor, a first common-gate transistor, a second common-gate transistor, a first common-gate neutralizing capacitor, a second common-gate neutralizing capacitor, a first inter-stage transformer, a first inter-stage inductor, and a second inter-stage inductor; The input transformer includes: an input transformer primary coil P1 and an input transformer secondary coil S1; The first inter-stage transformer includes: a first inter-stage transformer primary coil P2 and a first inter-stage transformer secondary coil S2; The specific connection method is as follows:

[0010] The radio frequency signal serving as the input signal is connected to the primary coil P1 of the input transformer. One end of the first input matching capacitor is connected to the first end of the primary coil P1 of the input transformer, and the other end of the first input matching capacitor is grounded. One end of the second input matching capacitor is connected to the second end of the primary coil P1 of the input transformer, and the other end of the second input matching capacitor is grounded. The first end of the secondary coil S1 of the input transformer is connected to the gate of the first common-source transistor and one end of the first common-source neutralizing capacitor. The second end of the secondary coil S1 of the input transformer is connected to the gate of the second common-source transistor and one end of the second common-source neutralizing capacitor. The drain of the first common-source transistor is connected to one end of the first common-source cascode inductor and the other end of the second common-source neutralizing capacitor. The drain of the second common-source transistor is connected to one end of the second common-source cascode inductor and the other end of the first common-source neutralizing capacitor. The source of the first common-source transistor is grounded, and the source of the second common-source transistor is grounded; the other end of the first common-source cascode inductor is connected to the source of the first common-gate transistor, and the other end of the second common-source cascode inductor is connected to the source of the second common-gate transistor. The gate of the first common-gate transistor is connected to one end of the first common-gate neutralizing capacitor, and the other end of the first common-gate neutralizing capacitor is connected to the drain of the second common-gate transistor and the second end of the primary coil P2 of the first inter-stage transformer; the gate of the second common-gate transistor is connected to one end of the second common-gate neutralizing capacitor, and the other end of the second common-gate neutralizing capacitor is connected to the drain of the first common-gate transistor and the first end of the primary coil P2 of the first inter-stage transformer; the first end of the secondary coil S2 of the first inter-stage transformer is connected to one end of the first inter-stage inductor, and the second end of the secondary coil S2 of the first inter-stage transformer is connected to one end of the second inter-stage inductor. The other end of the first inter-stage inductor is connected to the input end of the second-stage amplifier circuit, and the other end of the second inter-stage inductor is connected to the input end of the second input amplifier circuit;

[0011] The second-stage amplifier circuit includes: a third common-source transistor, a fourth common-source transistor, a third common-source neutralizing capacitor, a fourth common-source neutralizing capacitor, a third common-source cascode inductor, a fourth common-source cascode inductor, a third common-gate transistor, a fourth common-gate transistor, a third common-gate neutralizing capacitor, a fourth common-gate neutralizing capacitor, a second inter-stage transformer, a third inter-stage inductor, and a fourth inter-stage inductor; the second inter-stage transformer includes: a primary coil P3 of the second inter-stage transformer and a secondary coil S3 of the second inter-stage transformer; the specific connection method is as follows:

[0012] The first input terminal of the differential input of the second-stage amplifier circuit is connected to the gate of the third common-source transistor and one end of the third common-source neutralization capacitor. The second input terminal of the differential input of the second-stage amplifier circuit is connected to the gate of the fourth common-source transistor and one end of the fourth common-source neutralization capacitor. The drain of the third common-source transistor is connected to one end of the third common-source cascode inductor and the other end of the fourth common-source neutralization capacitor. The drain of the fourth common-source transistor is connected to one end of the fourth common-source cascode inductor and the other end of the third common-source neutralization capacitor. The source of the third common-source transistor is grounded, and the source of the fourth common-source transistor is grounded. The other end of the third common-source cascode inductor is connected to the source of the third cascode transistor. The other end of the fourth common-source cascode inductor is connected to the source of the fourth cascode transistor. The gate of the third cascode transistor is connected to one end of the third cascode neutralization capacitor. The other end of the third cascode neutralization capacitor is connected to the drain of the fourth cascode transistor and the second end of the primary coil P3 of the second-stage transformer. The gate of the fourth cascode transistor is connected to one end of the fourth cascode neutralization capacitor. The other end of the fourth cascode neutralization capacitor is connected to the drain of the third cascode transistor and the first end of the primary coil P3 of the second-stage transformer. The first end of the secondary coil S3 of the second-stage transformer is connected to one end of the third-stage inductor. The second end of the secondary coil S3 of the second-stage transformer is connected to one end of the fourth-stage inductor. The other end of the third-stage inductor is connected to the input terminal of the third-stage amplifier circuit. The other end of the fourth-stage inductor is connected to the input terminal of the third input amplifier circuit.

[0013] The third-stage amplifier circuit includes: a fifth common-source transistor, a sixth common-source transistor, a fifth common-source neutralization capacitor, a sixth common-source neutralization capacitor, a fifth common-source cascode inductor, a sixth common-source cascode inductor, a fifth cascode transistor, a sixth cascode transistor, a fifth cascode neutralization capacitor, a sixth cascode neutralization capacitor, an output transformer XF4, a first output matching capacitor, and a second output matching capacitor. The output transformer includes: an output transformer primary coil P4 and an output transformer secondary coil S4. The specific connection method is as follows:

[0014] The first input terminal of the differential input of the third-stage amplifier circuit is connected to the gate of the fifth common-source transistor and one end of the fifth common-source neutralization capacitor. The second input terminal of the differential input of the third-stage amplifier circuit is connected to the gate of the sixth common-source transistor and one end of the sixth common-source neutralization capacitor. The drain of the fifth common-source transistor is connected to one end of the fifth common-source cascode inductor and the other end of the sixth common-source neutralization capacitor. The drain of the sixth common-source transistor is connected to one end of the sixth common-source cascode inductor and the other end of the fifth common-source neutralization capacitor. The source of the fifth common-source transistor is grounded, and the source of the sixth common-source transistor is grounded. The other end of the fifth common-source cascode inductor is connected to the source of the fifth cascode transistor. The other end of the sixth common-source cascode inductor is connected to the source of the sixth cascode transistor. The gate of the fifth cascode transistor is connected to one end of the fifth cascode neutralization capacitor. The other end of the fifth cascode neutralization capacitor is connected to the drain of the sixth cascode transistor and the second end of the primary coil P4 of the output transformer. The gate of the sixth cascode transistor is connected to one end of the sixth cascode neutralization capacitor. The other end of the sixth cascode neutralization capacitor is connected to the drain of the fifth cascode transistor and the first end of the primary coil P4 of the output transformer. The first end of the secondary coil S4 of the output transformer is connected to one end of the first output matching capacitor. The second end of the secondary coil S4 of the output transformer is connected to one end of the second output matching capacitor. The other ends of the first output matching capacitor and the second output matching capacitor are both grounded. The secondary coil S4 of the output transformer outputs a radio frequency signal.

[0015] Further, one or any combination of the first input matching capacitor, the second input matching capacitor, the first output matching capacitor, and the second output matching capacitor is a transmission line flat capacitor, and one or any combination of the first inter-stage inductor, the second inter-stage inductor, the third inter-stage inductor, and the fourth inter-stage inductor is a transmission line inductor.

[0016] Using transmission line flat capacitors and transmission line inductors has better effects than ordinary capacitors and inductors.

[0017] Further, the width of the transmission line flat capacitor is 4.5 um, and the length is 15 um.

[0018] Further, the transmission line flat capacitor is drawn using metal layers M4 and M5.

[0019] Further, the inner diameter of the transmission line inductor is 20 um, and the metal line width is 3.5 um.

[0020] Further, the transmission line inductor is drawn using high-level metals.

[0021] Further, the first, second, third, fourth, fifth, and sixth common-source transistors, and the first, second, third, fourth, fifth, and sixth cascode transistors are all MOS transistors in CMOS process.

[0022] Furthermore, the turns ratio of the first inter-stage transformer is 1:2, and the turns ratios of the input transformer, the second inter-stage transformer, and the output transformer are 1:1.

[0023] Furthermore, the input transformer, the first inter-stage transformer, the second inter-stage transformer, and the output transformer all have center taps.

[0024] In summary, due to the adoption of the above technical solution, the present utility model can achieve high gain and low noise simultaneously while increasing the bandwidth. The specific beneficial effects are as follows:

[0025] (1) By combining the transformer with inductors and capacitors for matching, the loss of the passive matching circuit is reduced, and at the same time, a large bandwidth output of the low-noise amplifier is achieved;

[0026] (2) By adopting a cascode amplifier structure and combining the transformer with capacitors and inductors for impedance matching, broadband, high-gain amplification and low-noise signal output can be achieved.

[0027] The additional aspects and advantages of the present utility model will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present utility model will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, wherein:

[0029] Figure 1 is a schematic structural diagram of Embodiment 1 of the present utility model.

[0030] Figure 2 is a comparison diagram of the return loss (S11) parameters of the capacitors and transmission line planar capacitors in the PDK library used in Embodiment 1 of the present utility model.

[0031] Figure 3 is a comparison diagram of the noise figure (NF) of the capacitors, inductors, transmission line planar capacitors, and transmission line inductors in the PDK library used in Embodiment 1 of the present utility model.

[0032] Figure 4 is a comparison diagram of the gain of the inductors and transmission line inductors in the PDK library used in Embodiment 1 of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] The embodiments of the present utility model will be described in detail below. The examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present utility model and should not be construed as a limitation of the present utility model.

[0034] The structural schematic diagram of a millimeter-wave low-noise amplifier provided by Embodiment 1 of the present utility model is as follows Figure 1 shown, which includes a first-stage amplification circuit, a second-stage amplification circuit, and a third-stage amplification circuit; the signal output end of the first-stage amplification circuit is connected to the signal input end of the second-stage amplification circuit, and the signal output end of the second-stage amplification circuit is connected to the signal input end of the third-stage amplification circuit. First, the low-noise amplifier of the present application abandons the ordinary transformer matching, and uses the transformer in combination with the transmission line flat capacitor and the transmission line inductor for impedance matching, increasing the flexibility of the design; uses the transmission line inductor to weaken the parasitic capacitance in the chip layout, reducing the additional loss brought by the parasitic capacitance and improving the gain; realizes the amplification of signals with lower noise while achieving the broadband design of the return loss, and at the same time adopts the cascode amplifier structure to achieve high-gain amplification and low-noise output.

[0035] The first-stage amplification circuit includes: a first input matching capacitor C1P, a second input matching capacitor C1N, an input transformer XF1, a first common-source transistor M1P, a second common-source transistor M1N, a first common-source neutralization capacitor CM1, a second common-source neutralization capacitor CM2, a first cascode inductor LM1, a second cascode inductor LN1, a first common-gate transistor M2P, a second common-gate transistor M2N, a first common-gate neutralization capacitor CM3, a second common-gate neutralization capacitor CM4, a first inter-stage transformer XF2, a first inter-stage inductor LM2, and a second inter-stage inductor LN2;

[0036] The input transformer XF1 includes: an input transformer primary coil P1 and an input transformer secondary coil S1; the first inter-stage transformer XF2 includes: a first inter-stage transformer primary coil P2 and a first inter-stage transformer secondary coil S2;

[0037] The input transformer XF1 forms a coupled resonance with the first input matching capacitor C1P and the second input matching capacitor C1N. The input matching capacitor increases the parasitic capacitance value of the transformer and realizes strong coupled resonance with the transformer, achieving the large-bandwidth matching of the low-noise amplifier. The values of the first input matching capacitor and the second input matching capacitor are equal; both the first input matching capacitor and the second input matching capacitor are transmission line flat capacitors, both are drawn using metal layers M4 and M5, with a width of 4.5um and a length of 15um;

[0038] The first common-source transistor M1P and the second common-source transistor M1N adopt a finger interpolation structure to reduce the parasitic resistance, and the single finger is 0.04 um; the sources of the first common-source transistor M1P, the second common-source transistor M1N, the first common-gate transistor M2P, and the second common-gate transistor M2N are connected by the first common-source common-gate inductor LM1 and the second common-source common-gate inductor LN1. There is a parasitic capacitance between the drain of the common-source transistor and the source of the common-gate transistor. Increasing the resonance between the common-source common-gate inductors LM1 and LN1 and the parasitic capacitance can achieve the purpose of reducing circuit noise; the first common-gate transistor M2P and the second common-gate transistor M2N also adopt an interpolation structure, and the single finger is 0.04 um; the inner diameters of the first common-source common-gate inductor LM1 and the second common-source common-gate inductor LN1 are 20 um, and they are drawn using high-level metal, and the metal line width is 3.5 um;

[0039] The first common-gate neutralization capacitor CM3 and the second common-gate neutralization capacitor CM4 have a capacitance value of 19 f each, which can compensate for the influence brought by the gate-drain capacitance of the MOS transistor, suppress the Miller effect, and improve the stability and gain of the circuit.

[0040] The first inter-stage transformer XF2 is a differential transformer. The two input terminals of the first inter-stage transformer XF2 are respectively connected to the drains of the first common-gate transistor M2P and the second common-gate transistor M2N, and the two output terminals are respectively connected to the first-stage transmission line inductors LM2 and LN2. The transmission line inductors LM2 and LN2 are used for the inter-stage matching between the first-stage amplifier circuit and the second-stage amplifier circuit. The transmission line inductors LM2 and LN2 can be drawn using high-level metal in the PDK library to reduce losses. To reduce the area, a bending process is adopted; the transmission line inductor not only reduces the passive matching loss but also increases the design flexibility, optimizes the inter-stage matching performance, and realizes the high-gain broadband design; the first inter-stage transformer XF2 adopts a turns ratio of 1:2 structure and is drawn using high-level metal and sub-high-level metal;

[0041] The second-stage amplifier circuit includes: a third common-source transistor M3P, a fourth common-source transistor M3N, a third common-source neutralization capacitor CM5, a fourth common-source neutralization capacitor CM6, a third common-source common-gate inductor LM2, a fourth common-source common-gate inductor LN2, a third common-gate transistor M4P, a third common-gate transistor M4N, a third common-gate neutralization capacitor CM7, a fourth common-gate neutralization capacitor CM8, a second inter-stage transformer XF3, a third inter-stage inductor LM3, and a fourth inter-stage inductor LN3; the inter-stage transformer XF3 includes: a transformer primary coil P3, a transformer secondary coil S3;

[0042] The gates of the third common-source transistors M3P and M3N are connected to the first-stage transmission line inductors LM2 and LN1. The drains of the third common-source transistors M3P and M3N are connected to the third common-source cascode inductors LM3 and LN3. The third common-source cascode inductors LM3 and LN3 have a line width of 4um and an inductance value of 100p. Metal isolation rings are added around the inductors to isolate substrate noise. The third common-source cascode inductors LM3 and LN3 are connected to the source terminals of the third cascode transistors M4P and M4N. The third cascode transistors M4P and M4N both adopt an interpolation structure to reduce the parasitic resistance of the MOS transistors.

[0043] The third cascode transistors M4P and M4N are respectively connected to the differential input terminals of the second-stage inter-stage transformer XF3. The differential output terminals of the second-stage inter-stage transformer are connected to the third transmission line inductor LM4 and the fourth transmission line inductor LN4, increasing the inductance value of the secondary coil of the second-stage inter-stage transformer. Independent transmission line inductors are used to increase the flexibility of transformer design.

[0044] The design of the third-stage amplifier is the same as that of the second stage. First output matching capacitors C2P and second output matching capacitors C2N are added at the secondary coil of the output transformer. The capacitance values of the first output matching capacitor C2P and the second output matching capacitor C2N are both 20f. The output matching capacitors increase the parasitic capacitance value of the transformer and achieve strong coupling resonance with the transformer, adjusting the output matching of the low-noise amplifier.

[0045] For the design of a millimeter-wave low-noise amplifier, the frequency range corresponding to a return loss less than -10dB is greater than 4GHz, which meets the broadband design. For the design of a three-stage low-noise amplifier, the noise figure is less than 7dB and the gain is greater than 20dB, which meets the high-gain and low-noise design requirements of the low-noise amplifier. Figures 2 to 4 It can be seen that the low-noise amplifier designed by the present utility model can simultaneously achieve high gain and low noise on the premise of increasing the bandwidth.

[0046] Figure 2 This is a comparison chart of the return loss (S11) parameters of the capacitors and transmission line planar capacitors in the PDK library used in Embodiment 1 of the present utility model. The dotted line is the return loss diagram of the capacitors in the PDK, and the solid line is the return loss diagram of the transmission line planar capacitors. It can be seen from the figure that the use of transmission line planar capacitors can achieve a wider bandwidth when the return loss is -10dB.

[0047] Figure 3This is a comparison chart of the noise figure (NF) of capacitors, inductors, transmission line planar capacitors, and transmission line inductors in the PDK library in Embodiment 1 of the present utility model. The dashed line is the noise figure chart of capacitors and inductors in the PDK library, and the solid line is the noise figure chart of transmission line planar capacitors and transmission line inductors. It can be seen that the noise figure of using transmission line planar capacitors and transmission line inductors is significantly lower than that of using capacitors and inductors in the PDK library. In the frequency band, the maximum change in the noise figure is 0.35 dB.

[0048] Figure 4 This is a comparison chart of the gain of inductors in the PDK library and transmission line inductors in Embodiment 1 of the present utility model. The dashed line is the gain chart of inductors in the PDK library, and the solid line is the gain chart of transmission line inductors. It can be seen that the gain of using transmission line inductors is significantly higher than that of using inductors in the PDK library. The loss of the transmission line inductor is low. Therefore, compared with the inductors in the PDK library, the gain of the low-noise amplifier can be improved.

[0049] Although the embodiments of the present utility model have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and purposes of the present utility model. The scope of the present utility model is defined by the claims and their equivalents.

Claims

1. A millimeter wave low noise amplifier, characterized in that: The low noise amplifier comprises: a first-stage amplifier circuit, a second-stage amplifier circuit, and a third-stage amplifier circuit, wherein the signal output end of the first-stage amplifier circuit is connected to the signal input end of the second-stage amplifier circuit, and the signal output end of the second-stage amplifier circuit is connected to the signal input end of the third-stage amplifier circuit; The first-stage amplifier circuit includes: a first input matching capacitor, a second input matching capacitor, an input transformer, a first common-source transistor, a second common-source transistor, a first common-source neutralizing capacitor, a second common-source neutralizing capacitor, a first common-source common-gate inductor, a second common-source common-gate inductor, a first common-gate transistor, a second common-gate transistor, a first common-gate neutralizing capacitor, a second common-gate neutralizing capacitor, a first interstage transformer, a first interstage inductor, and a second interstage inductor; the input transformer includes: an input transformer primary coil P1 and an input transformer secondary coil S1; the first interstage transformer includes: a first interstage transformer primary coil P2 and a first interstage transformer secondary coil S2; the specific connection method is: The radio frequency signal as an input signal is connected to the primary coil P1 of the input transformer, one end of the first input matching capacitor is connected to the first end of the primary coil P1 of the input transformer, the other end of the first input matching capacitor is grounded, one end of the second input matching capacitor is connected to the second end of the primary coil P1 of the input transformer, the other end of the second input matching capacitor is grounded, the first end of the secondary coil S1 of the input transformer is connected to the gate of the first common source transistor and one end of the first common source neutralizing capacitor, the second end of the secondary coil S1 of the input transformer is connected to the gate of the second common source transistor and one end of the second common source neutralizing capacitor, the drain of the first common source transistor is connected to one end of the first common source common gate inductor and the other end of the second common source neutralizing capacitor, the drain of the second common source transistor is connected to one end of the second common source common gate inductor and the other end of the first common source neutralizing capacitor, the source of the first common source transistor is grounded, and the source of the second common source transistor is grounded; The other end of the first common-source common-gate inductor is connected to the source of the first common-gate transistor, the other end of the second common-source common-gate inductor is connected to the source of the second common-gate transistor, the gate of the first common-gate transistor is connected to one end of the first common-gate neutralizing capacitor, the other end of the first common-gate neutralizing capacitor is connected to the drain of the second common-gate transistor and the second end of the primary coil P2 of the first interstage transformer; the gate of the second common-gate transistor is connected to one end of the second common-gate neutralizing capacitor, the other end of the second common-gate neutralizing capacitor is connected to the drain of the first common-gate transistor and the first end of the primary coil P2 of the first interstage transformer; the first end of the secondary coil S2 of the first interstage transformer is connected to one end of the first interstage inductor, the second end of the secondary coil S2 of the first interstage transformer is connected to one end of the second interstage inductor, the other end of the first interstage inductor is connected to the input end of the second-stage amplifier circuit, and the other end of the second interstage inductor is connected to the input end of the second input amplifier circuit; The second stage amplifier circuit includes: a third common source transistor, a fourth common source transistor, a third common source neutralization capacitor, a fourth common source neutralization capacitor, a third common source common gate inductor, a fourth common source common gate inductor, a third common gate transistor, a fourth common gate transistor, a third common gate neutralization capacitor, a fourth common gate neutralization capacitor, a second interstage transformer, a third interstage inductor, and a fourth interstage inductor; the second interstage transformer includes: a second interstage transformer primary coil P3 and a second interstage transformer secondary coil S3; the specific connection method is: The first input end of the differential input of the second-stage amplifier circuit is connected to the gate of the third common-source transistor and one end of the third common-source neutralizing capacitor, and the second input end of the differential input of the second-stage amplifier circuit is connected to the gate of the fourth common-source transistor and one end of the fourth common-source neutralizing capacitor; the drain of the third common-source transistor is connected to one end of the third common-source common-gate inductor and the other end of the fourth common-source neutralizing capacitor, and the drain of the fourth common-source transistor is connected to one end of the fourth common-source common-gate inductor and the other end of the third common-source neutralizing capacitor; the source of the third common-source transistor is grounded, and the source of the fourth common-source transistor is grounded; the other end of the third common-source common-gate inductor is connected to the source of the third common-gate transistor, and the other end of the fourth common-source common-gate inductor is connected to the source of the fourth common-gate transistor, and the third common-source transistor is grounded. The gate of the gate transistor is connected to one end of the third common-gate neutralizing capacitor, and the other end of the third common-gate neutralizing capacitor is connected to the drain of the fourth common-gate transistor and the second end of the primary coil P3 of the second interstage transformer; the gate of the fourth common-gate transistor is connected to one end of the fourth common-gate neutralizing capacitor, and the other end of the fourth common-gate neutralizing capacitor is connected to the drain of the third common-gate transistor and the first end of the primary coil P3 of the second interstage transformer, the first end of the secondary coil S3 of the second interstage transformer is connected to one end of the third interstage inductor, the second end of the secondary coil S3 of the second interstage transformer is connected to one end of the fourth interstage inductor, the other end of the third interstage inductor is connected to the input end of the third-stage amplifier circuit, and the other end of the fourth interstage inductor is connected to the input end of the third input amplifier circuit; The third-stage amplifier circuit includes: a fifth common-source transistor, a sixth common-source transistor, a fifth common-source neutralization capacitor, a sixth common-source neutralization capacitor, a fifth common-source common-gate inductor, a sixth common-source common-gate inductor, a fifth common-gate transistor, a sixth common-gate transistor, a fifth common-gate neutralization capacitor, a sixth common-gate neutralization capacitor, an output transformer XF4, a first output matching capacitor, and a second output matching capacitor; the output transformer includes: an output transformer primary coil P4 and an output transformer secondary coil S4; the specific connection method is: The first input terminal of the differential input of the third-stage amplifier circuit is connected to the gate of the fifth common-source transistor and one end of the fifth common-source neutralizing capacitor, and the second input terminal of the differential input of the third-stage amplifier circuit is connected to the gate of the sixth common-source transistor and one end of the sixth common-source neutralizing capacitor; the drain of the fifth common-source transistor is connected to one end of the fifth common-source common-gate inductor and the other end of the sixth common-source neutralizing capacitor, the drain of the sixth common-source transistor is connected to one end of the sixth common-source common-gate inductor and the other end of the fifth common-source neutralizing capacitor, the source of the fifth common-source transistor is grounded, and the source of the sixth common-source transistor is grounded; the other end of the fifth common-source common-gate inductor is connected to the source of the fifth common-gate transistor, and the other end of the sixth common-source common-gate inductor is connected to the source of the sixth common-gate transistor. The gate of the fifth common-gate transistor is connected to one end of the fifth common-gate neutralization capacitor, and the other end of the fifth common-gate neutralization capacitor is connected to the drain of the sixth common-gate transistor and the second end of the output transformer primary coil P4; the gate of the sixth common-gate transistor is connected to one end of the sixth common-gate neutralization capacitor, and the other end of the sixth common-gate neutralization capacitor is connected to the drain of the fifth common-gate transistor and the first end of the output transformer primary coil P4; the first end of the output transformer secondary coil S4 is connected to one end of the first output matching capacitor, the second end of the output transformer secondary coil S4 is connected to one end of the second output matching capacitor, the other ends of the first output matching capacitor and the second output matching capacitor are both grounded, and the output transformer secondary coil S4 outputs a radio frequency signal.

2. A millimeter wave low noise amplifier according to claim 1, characterized in that: One or any combination of the first input matching capacitor, the second input matching capacitor, the first output matching capacitor, and the second output matching capacitor is a transmission line flat plate capacitor, and one or any combination of the first inter-stage inductor, the second inter-stage inductor, the third inter-stage inductor, and the fourth inter-stage inductor is a transmission line inductor.

3. A millimeter wave low noise amplifier according to claim 2, characterized in that: The transmission line flat plate capacitor has a width of 4.5 um and a length of 15 um.

4. A millimeter wave low noise amplifier according to claim 2, characterized in that: The transmission line planar capacitor is drawn using metal layers M4 and M5.

5. A millimeter wave low noise amplifier according to claim 2, characterized in that: The inner diameter of the transmission line inductor is 20um, and the metal line width is 3.5um.

6. A millimeter wave low noise amplifier according to claim 2, characterized in that: The transmission line inductor is drawn using high-layer metal.

7. The millimeter wave low noise amplifier according to claim 1, characterized in that: The first, second, third, fourth, fifth and sixth common-source transistors and the first, second, third, fourth, fifth and sixth common-gate transistors are all MOS tubes of CMOS process.

8. The millimeter wave low noise amplifier according to claim 1, characterized in that: The turns ratio of the first interstage transformer is 1:2, and the turns ratio of the input transformer, the second interstage transformer, and the output transformer is 1:

1.

9. The millimeter wave low noise amplifier according to claim 1, characterized in that: The input transformer, the first interstage transformer, the second interstage transformer, and the output transformer all have center taps.

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