Display device

Abstract

The display device includes: a substrate; a first electrode on the substrate; a light emitting layer on the first electrode; a pixel defining layer on the light emitting layer; and a second electrode on the light emitting layer. First and second sides of the light emitting layer opposite each other are on the pixel defining layer, and the first and second sides of the light emitting layer each have a linear shape inclined at an angle with respect to an upper surface of the pixel defining layer.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0142570, filed with the Korean Intellectual Property Office on October 24, 2023, the entire disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device and a method of manufacturing the same. Background Art

[0004] A head-mounted display (HMD) is a display device for displaying an image and is worn on a user's head in the form of glasses or a helmet such that a focus is formed at a distance close to the user's eyes. For example, a head-mounted display can implement virtual reality (VR) or augmented reality (AR).

[0005] A head-mounted display magnifies and displays a small-sized image displayed by a display device by using a plurality of lenses. Accordingly, it can be expected that a display device applied to a head-mounted display provides a high-resolution image (such as an image having a resolution of 3000 pixels per inch (PPI) or more). Thus, an organic light-emitting diode on silicon (OLEDoS) display device, which is a small-sized organic light-emitting display device having a high resolution, can be used as a display device applied to a head-mounted display. An OLEDoS display device is a device including an organic light-emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided to display an image.

[0006] The above information disclosed in this background art section is for enhancing an understanding of the background art of the present disclosure, and thus, it may include information that does not constitute the prior art. Summary of the Utility Model

[0007] Embodiments of the present disclosure may relate to a display device capable of suppressing the occurrence of lateral leakage current between adjacent light-emitting layers and a method of manufacturing the same.

[0008] However, the present disclosure is not limited to the above aspects and features, and the above and other aspects and features will be partially described hereinafter, and will be partially apparent from the description, or may be learned by practicing one or more of the presented embodiments of the present disclosure.

[0009] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first electrode on the substrate; a light-emitting layer on the first electrode; a pixel defining layer on the light-emitting layer; and a second electrode on the light-emitting layer. Opposite first and second sides of the light-emitting layer are located on the pixel defining layer, and each of the first and second sides of the light-emitting layer has a linear shape inclined at an angle with respect to the upper surface of the pixel defining layer.

[0010] In an embodiment, the angle between the upper surface of the pixel defining layer and the first side of the light-emitting layer may be greater than 60° and less than or equal to 90°, and the angle between the upper surface of the pixel defining layer and the second side of the light-emitting layer may be greater than 60° and less than or equal to 90°.

[0011] In an embodiment, the distance between the first side and the second side of the light-emitting layer may gradually decrease in a direction away from the pixel defining layer.

[0012] In an embodiment, the display device may further include a first functional layer between the first electrode and the light-emitting layer.

[0013] In an embodiment, opposite first and second sides of the first functional layer may be located on the pixel defining layer, and each of the first and second sides of the first functional layer may have a linear shape inclined at an angle with respect to the upper surface of the pixel defining layer.

[0014] In an embodiment, the angle between the upper surface of the pixel defining layer and the first side of the first functional layer may be greater than 60° and less than or equal to 90°, and the angle between the upper surface of the pixel defining layer and the second side of the first functional layer may be greater than 60° and less than or equal to 90°.

[0015] In an embodiment, the distance between the first side and the second side of the first functional layer may gradually decrease in a direction away from the pixel defining layer.

[0016] In an embodiment, the first functional layer may include: a hole injection layer on the first electrode; and a hole transport layer on the hole injection layer.

[0017] In an embodiment, the display device may further include a second functional layer between the light-emitting layer and the second electrode.

[0018] In an embodiment, opposite first and second sides of the second functional layer may be located on the pixel defining layer, and each of the first and second sides of the second functional layer may have a linear shape inclined at an angle with respect to the upper surface of the pixel defining layer.

[0019] In an embodiment, the angle between the upper surface of the pixel defining layer and the first side of the second functional layer may be greater than 60° and less than or equal to 90°, and the angle between the upper surface of the pixel defining layer and the second side of the second functional layer may be greater than 60° and less than or equal to 90°.

[0020] In an embodiment, the distance between the first side and the second side of the second functional layer may gradually decrease in a direction away from the pixel defining layer.

[0021] In an embodiment, the second functional layer may include a buffer layer on the light emitting layer.

[0022] In an embodiment, the display device may further include a common buffer layer between the second functional layer and the second electrode.

[0023] In an embodiment, the display device may further include a first functional layer between the first electrode and the light emitting layer, and the common buffer layer may be located on the first side and the second side of the light emitting layer, the first side and the second side of the first functional layer, and the first side and the second side of the second functional layer.

[0024] In an embodiment, the display device may further include an electron transport layer between the common buffer layer and the second electrode.

[0025] In an embodiment, the electron transport layer may be located on the common buffer layer to surround the light emitting layer in a plan view.

[0026] In an embodiment, the display device may further include a packaging layer on the second electrode.

[0027] In an embodiment, the pixel defining layer may include an inorganic layer.

[0028] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: disposing a first electrode on a substrate; disposing a pixel defining layer on the first electrode; disposing a first functional layer, a light emitting layer, a second functional layer, and a sacrificial layer on the pixel defining layer over the entire surface of the substrate; disposing a photoresist pattern on the sacrificial layer to overlap with the first electrode; etching the first functional layer, the light emitting layer, the second functional layer, and the sacrificial layer by using the photoresist pattern as a mask such that the first functional layer, the light emitting layer, the second functional layer, and the sacrificial layer are disposed between the first electrode and the photoresist pattern; removing the photoresist pattern; and removing the etched sacrificial layer.

[0029] In an embodiment, the method may further include cleaning the substrate and the etched first functional layer, etched light emitting layer, and etched second functional layer.

[0030] In an embodiment, the method may further include: disposing the cleaned substrate in a vacuum chamber; and drying the substrate in the vacuum chamber.

[0031] In an embodiment, the method may further include disposing a common buffer layer on the second functional layer in a vacuum chamber.

[0032] In an embodiment, the method may further include disposing an electron transport layer on the common buffer layer in a vacuum chamber.

[0033] In an embodiment, the method may further include disposing a second electrode on the electron transport layer in a vacuum chamber.

[0034] In an embodiment, when etching the first functional layer, the light-emitting layer, the second functional layer, and the sacrificial layer by using a photoresist pattern as a mask, the first functional layer, the light-emitting layer, the second functional layer, and the sacrificial layer may be etched by dry etching.

[0035] In an embodiment, when removing the etched sacrificial layer, the etched sacrificial layer may be removed by an etchant.

[0036] In an embodiment, the sacrificial layer may include at least one of aluminum and silver.

[0037] According to one or more embodiments of the present disclosure, the occurrence of lateral leakage current between adjacent light-emitting layers can be suppressed. Accordingly, deterioration of image quality that may be caused by color mixing between adjacent pixels can be minimized or reduced.

[0038] However, the present disclosure is not limited to the above aspects and features, and those of ordinary skill in the art can understand the above and other aspects and features of the present disclosure through the following detailed description with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of exemplary, non-limiting embodiments with reference to the drawings, in which:

[0040] Figure 1 is an exploded perspective view showing a display device according to an embodiment;

[0041] Figure 2 is showing Figure 1 an example layout diagram of the display panel shown in;

[0042] Figure 3 is a block diagram showing a display device according to an embodiment;

[0043] Figure 4 is an equivalent circuit diagram showing a first pixel according to an embodiment;

[0044] Figure 5 is a plan view showing a unit pixel according to an embodiment;

[0045] Figure 6 is a cross-sectional view of a display device taken along line I-I' according to an embodiment; Figure 5

[0046] Figure 7 is a view showing Figure 6 an enlarged view of a first light-emitting element; and

[0047] Figures 8 to 24 is a cross-sectional view of a method of manufacturing a display device according to one or more embodiments. DETAILED DESCRIPTION

[0048] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals always denote like elements. However, the present disclosure may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. Instead, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise noted, like reference numerals refer to like elements throughout the drawings and the written description, and thus, redundant descriptions thereof may not be repeated.

[0049] When a particular embodiment can be implemented differently, the specific process order may be different from that described. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or two consecutively described processes may be performed in an order opposite to that described.

[0050] In the drawings, for clarity, the relative dimensions, thicknesses, and proportions of elements, layers, and regions may be exaggerated and / or simplified. For ease of explanation, spatially relative terms such as "under", "below", "lower", "beneath", "above", and "upper" may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatially relative terms are also intended to encompass different orientations of the device during use or operation. For example, if the device is flipped in the drawing, an element described as "under", "below", or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the example terms "under", "below", and "beneath" can encompass both an upper and a lower orientation. The device may be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein should be interpreted accordingly.

[0051] ​In the accompanying drawings, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0052] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, the first component, the first region, the first layer, or the first part described below may be named the second element, the second component, the second region, the second layer, or the second part.

[0053] It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or there can be one or more intervening elements or intervening layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, the layer, region, or element can be directly electrically connected to the other layer, region, or element, and / or can be indirectly electrically connected with one or more intervening layers, intervening regions, or intervening elements therebetween. Further, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or intervening layers.

[0054] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, as used herein, the singular forms "a" and "an" are also intended to include the plural forms. It will also be understood that when used in this specification, the terms "comprises," "comprising," "includes," "including," "has," "have," and "having" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" means A, B, or A and B. When an expression such as "at least one of..." is placed after a list of elements, the expression modifies the entire list of elements and not individual elements in the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof.

[0055] As used herein, the terms "substantially," "about," and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art. Further, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0057] Figure 1 is an exploded perspective view showing a display device 10 according to an embodiment. Figure 2 is a view showing Figure 1 an example layout diagram of the display panel 100 shown in Figure 3 is a view showing a display device 10 according to an embodiment (seeFigure 1 ) block diagram.

[0058] Referring to Figures 1 to 3 , the display device 10 according to the embodiment is a device for displaying dynamic images and / or still images. The display device 10 can be applied to portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile PCs (UMPCs)). For example, the display device 10 can be applied to televisions, laptop computers, monitors, signs, or display units (e.g., displays) of Internet of Things (IoT) devices. In addition, the display device 10 can be applied to smart watches, watch phones, and head-mounted displays (HMDs) for implementing virtual reality (VR) and / or augmented reality (AR).

[0059] The display device 10 according to the embodiment includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0060] The display panel 100 can be formed in a planar shape similar to a rectangular shape. For example, the display panel 100 can have a planar shape like a rectangular shape, which has a short side extending in a first direction DR1 and a long side extending in a second direction DR2 that intersects the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be rounded to have a curvature (e.g., a predetermined curvature), or can be formed at right angles. The planar shape of the display panel 100 can be formed in a shape similar to other polygonal shapes, circular shapes, or elliptical shapes, and is not limited to the rectangular shape. The planar shape of the display device 10 can follow the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0061] As Figure 2 shown, the display panel 100 includes a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0062] As Figure 3 shown, the display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines ECL, and a plurality of data lines DL.

[0063] Each of the plurality of pixels PX includes a light-emitting element for emitting light. The plurality of pixels PX can be arranged in a matrix along the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines ECL can extend in the first direction DR1 and can be arranged along the second direction DR2. The plurality of data lines DL can extend in the second direction DR2 and can be arranged along the first direction DR1.

[0064] The plurality of scan lines SL includes a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines ECL includes a plurality of first emission control lines ECL1 and a plurality of second emission control lines ECL2.

[0065] The plurality of unit pixels UPX (for example, see Figure 5 ) may include a plurality of pixels PX1, PX2, and PX3 (for example, see Figure 5 ). The plurality of pixels PX1, PX2, and PX3 may include a plurality of pixel transistors as shown in Figure 4 . The plurality of pixel transistors may be formed by a semiconductor process and may be disposed at a semiconductor substrate (for example, in or on the semiconductor substrate). For example, the plurality of pixel transistors may be formed of complementary metal oxide semiconductor (CMOS).

[0066] Each of the plurality of pixels PX1, PX2, and PX3 may be connected to a corresponding one of the plurality of write scan lines GWL, a corresponding one of the plurality of control scan lines GCL, a corresponding one of the plurality of bias scan lines EBL, a corresponding one of the plurality of first emission control lines ECL1, a corresponding one of the plurality of second emission control lines ECL2, and a corresponding one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 may receive the data voltage of the corresponding data line DL according to the write scan signal of the corresponding write scan line GWL, and may allow the corresponding light-emitting element to emit light according to the data voltage.

[0067] The non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0068] The scan driving area SDA may be an area where the scan driver 610 and the emission driver 620 are disposed. Although Figure 2 it is shown that the scan driver 610 is disposed on the left side of the display area DAA and the emission driver 620 is disposed on the right side of the display area DAA, the present disclosure is not limited thereto. For example, each of the scan driver 610 and the emission driver 620 may be disposed on the left or right side of the display area DAA.

[0069] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of emission transistors. The plurality of scan transistors and the plurality of emission transistors may be formed by a semiconductor process and may be formed at a semiconductor substrate (for example, Figure 6 the substrate SUB of

[0070] The scan driver 610 may include a write scan signal output unit (e.g., a write scan signal output circuit) 611, a control scan signal output unit (e.g., a control scan signal output circuit) 612, and a bias scan signal output unit (e.g., a bias scan signal output circuit) 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400, and may sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS, and may sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and may sequentially output the bias scan signal to the bias scan line EBL.

[0071] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate a first emission control signal according to the emission timing control signal ECS, and may sequentially output the first emission control signal to the first emission control line ECL1. The second emission control driver 622 may generate a second emission control signal according to the emission timing control signal ECS, and may sequentially output the second emission control signal to the second emission control line ECL2.

[0072] The data driver area DDA may be an area where the data driver 700 is provided. The data driver 700 may include a plurality of data transistors. The plurality of data transistors may be formed by a semiconductor process and may be formed at (e.g., in or on) a semiconductor substrate (e.g., Figure 6 the substrate SUB). For example, the plurality of data transistors may be formed of CMOS.

[0073] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 may be selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0074] The pad area PDA includes a plurality of pads PD arranged along a first direction DR1. Each of the plurality of pads PD may be exposed without being covered by a cover layer and a polarizing plate.

[0075] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100 (such as taking the rear surface of the display panel 100 as an example). The heat dissipation layer 200 is used to dissipate the heat generated from the display panel 100. The heat dissipation layer 200 may include graphite or a metal with high thermal conductivity, such as silver (Ag), copper (Cu), or aluminum (Al).

[0076] The circuit board 300 may be electrically connected to the plurality of pads PD of the pad area PDA of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film including a flexible material. Although Figure 1 the circuit board 300 is shown as being unfolded, the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100. One end of the circuit board 300 may be opposite to the other end of the circuit board 300, and the other end of the circuit board 300 is connected to the plurality of pads PD of the pad area PDA of the display panel 100 by using a conductive adhesive member.

[0077] The timing control circuit 400 may receive digital video data DATA and timing signals from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 according to the timing signals. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610, and may output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0078] The power supply circuit 500 may generate a plurality of panel driving voltages according to a power voltage from the outside. For example, the power supply circuit 500 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and may supply them to the display panel 100. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described in more detail later with reference to Figure 4 more details.

[0079] Each of the timing control circuit 400 and the power supply circuit 500 may be formed of an integrated circuit (IC) and may be attached to one surface of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0080] Figure 4 is an equivalent circuit diagram showing a first pixel PX1 according to an embodiment.

[0081] Referring to Figure 4 and in conjunction with Figure 3 , the first pixel PX1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line ECL1, the second emission control line ECL2, and the data line DL. The first pixel PX1 may also be connected to the first driving voltage line VSL, the second driving voltage line VDL, and the third driving voltage line VIL. The first driving voltage VSS corresponding to the low potential voltage is applied to the first driving voltage line VSL, the second driving voltage VDD corresponding to the high potential voltage is applied to the second driving voltage line VDL, and the third driving voltage VINT corresponding to the initialization voltage is applied to the third driving voltage line VIL. In other words, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. In this case, the first driving voltage VSS may be lower than the third driving voltage VINT. The second driving voltage VDD may be higher than the third driving voltage VINT.

[0082] The first pixel PX1 includes a plurality of transistors T1 to T6, a light emitting element ED, a first capacitor C1, and a second capacitor C2.

[0083] The light emitting element ED emits light according to the driving current Ids flowing through the channel region of the first transistor T1. The amount of light emitted from the light emitting element ED may be proportional to the driving current Ids. The light emitting element ED may be disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element ED may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light emitting element ED may be connected to the first driving voltage line VSL. The first electrode of the light emitting element ED may be an anode electrode (e.g., a pixel electrode), and the second electrode of the light emitting element ED may be a cathode electrode (e.g., a common electrode CE (see Figure 6). The light-emitting element ED may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light-emitting element ED may be an inorganic light-emitting element, and the inorganic light-emitting element includes a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light-emitting element ED may be a micro light-emitting diode.

[0084] The first transistor T1 may be a driving transistor for controlling a source-drain current (hereinafter referred to as a driving current Ids) flowing between the source electrode and the drain electrode of the first transistor T1 according to a voltage applied to the gate electrode of the first transistor T1. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0085] The second transistor T2 may be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 may be turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. As a result, the data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0086] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by controlling a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. Since the gate electrode and the source electrode of the first transistor T1 are connected to each other through the third transistor T3, the first transistor T1 may operate like a diode (for example, may be diode-connected). The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0087] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emission control signal of the first emission control line ECL1 to connect the second node N2 to the third node N3. Accordingly, the driving current Ids of the first transistor T1 may be supplied to the light-emitting element ED. The fourth transistor T4 includes a gate electrode connected to the first emission control line ECL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0088] The fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 can be turned on by a bias scan signal for the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. As a result, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element ED. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0089] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 can be turned on by a second emission control signal for the second emission control line ECL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. As a result, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line ECL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0090] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0091] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0092] The first node N1 is the contact point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is the contact point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the contact point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element ED.

[0093] Each of the first transistor T1 to the sixth transistor T6 may be a metal-oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but the present disclosure is not limited thereto. For example, each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. As another example, each of some of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, and each of the other transistors of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET.

[0094] Although Figure 4 it is shown that the first pixel PX1 includes six transistors T1 to T6 and two capacitors C1 and C2, the present disclosure is not limited to Figure 4 the equivalent circuit diagram of the first pixel PX1 shown therein. For example, as those of ordinary skill in the art will understand, the number of transistors and the number of capacitors of the first pixel PX1 can be variously modified according to needs or expectations.

[0095] In addition, the equivalent circuit diagram of the second pixel PX2 (see Figure 5 ) and the equivalent circuit diagram of the third pixel PX3 (see Figure 5 ) may be the same as or substantially the same as the equivalent circuit diagram of the first pixel PX1 described above with reference to Figure 4 . Therefore, the redundant description of the equivalent circuit diagrams of the second pixel PX2 and the third pixel PX3 will not be repeated.

[0096] Figure 5 is a plan view showing a unit pixel UPX according to an embodiment.

[0097] As Figure 5 shown in Figure 1 , the display device 10 (see

[0098] The first pixel PX1 to the third pixel PX3 of the unit pixel UPX may be pixels for providing lights of different colors (e.g., wavelengths) from each other. For example, the first pixel PX1 may provide light of a first color, the second pixel PX2 may provide light of a second color, and the third pixel PX3 may provide light of a third color. The first color may be any one of red, green, or blue, the second color may be any color different from the first color among red, green, and blue, and the third color may be any remaining color different from the first color and the second color among red, green, and blue.

[0099] The first pixel PX1 may include a first pixel electrode PE1, the second pixel PX2 may include a second pixel electrode PE2, and the third pixel PX3 may include a third pixel electrode PE3.

[0100] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be arranged adjacent to each other. For example, the first pixel electrode PE1 and the second pixel electrode PE2 may be arranged adjacent to each other in a first direction DR1, the second pixel electrode PE2 and the third pixel electrode PE3 may be arranged adjacent to each other in a second direction DR2, and the third pixel electrode PE3 and the first pixel electrode PE1 may be arranged adjacent to each other in the second direction DR2.

[0101] The first pixel electrode PE1 to the third pixel electrode PE3 may have different sizes from each other. For example, the area of the third pixel electrode PE3 may be larger than the sum of the areas of the first pixel electrode PE1 and the second pixel electrode PE2. In this case, the third pixel PX3 including the third pixel electrode PE3 may provide blue light, the first pixel PX1 including the first pixel electrode PE1 may provide red light, and the second pixel PX2 including the second pixel electrode PE2 may provide green light. When the third pixel PX3 provides blue light, the first pixel PX1 provides red light, and the second pixel PX2 provides green light, the area of the second pixel electrode PE2 may be larger than the area of the first pixel electrode PE1 and smaller than the area of the third pixel electrode PE3.

[0102] A part (e.g., an edge) of the first pixel electrode PE1, a part (e.g., an edge) of the second pixel electrode PE2, and a part (e.g., an edge) of the third pixel electrode PE3 may be covered by a pixel defining layer (e.g., see the pixel defining layer PDL of Figure 11 ), which will be described in more detail later. In other words, a part (e.g., an edge) of the first pixel electrode PE1, a part (e.g., an edge) of the second pixel electrode PE2, and a part (e.g., an edge) of the third pixel electrode PE3 may partially overlap with the pixel defining layer PDL (e.g., see Figure 11 ).

[0103] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be defined by regions of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively, which regions are exposed without being covered by the pixel defining layer PDL. For example, the first light-emitting region EA1 may be the light-emitting region of the first pixel PX1 including the first pixel electrode PE1, the second light-emitting region EA2 may be the light-emitting region of the second pixel PX2 including the second pixel electrode PE2, and the third light-emitting region EA3 may be the light-emitting region of the third pixel PX3 including the third pixel electrode PE3.

[0104] Figure 6 is a cross-sectional view showing a display device 10 (see Figure 5 ) taken along line I-I' according to an embodiment. Figure 1 )

[0105] As Figure 6 shown, the display device 10 according to some embodiments may include a driving circuit layer DCL, a light-emitting element layer EMTL, and a packaging layer ENC.

[0106] The substrate SUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate SUB may be doped with a first type of impurity.

[0107] The well region W may be provided at the substrate SUB (e.g., inside the substrate SUB). The well region W may be a region doped with a second type of impurity. The second type of impurity may be different from the first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. When the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0108] The source region S, the drain region D, and the channel region CH of the transistor TR may be provided in the well region W. For example, the source region S (e.g., source electrode) and the drain region D (e.g., drain electrode) of the transistor TR may be provided in the well region W. Each of the source region S and the drain region D may be a region doped with the first type of impurity. The gate electrode G of the transistor TR may overlap with the well region W while crossing the well region W. In a plan view, the well region W crossing the gate electrode G may be defined as two regions, the source region S may be provided in any one of the two regions, and the drain region D may be provided in the other of the two regions. In other words, in the well region W, the source region S and the drain region D may be provided on both sides (e.g., opposite sides) of the channel region CH, and the channel region CH is between the source region S and the drain region D. The channel region CH of the transistor may be provided in the region of the well region W overlapping with the gate electrode G. Figure 6 The transistor TR shown in Figure 4The fourth transistor T4 shown in

[0109] The source region S may include a first lightly doped impurity region having an impurity concentration that is relatively lower than that of other portions of the source region S. In other words, a part of the source region S may include impurities having a concentration lower than that of other portions of the source region S. The drain region D may include a second lightly doped impurity region having an impurity concentration that is relatively lower than that of other portions of the drain region D. In other words, a part of the drain region D may include impurities having a concentration lower than that of other portions of the drain region D.

[0110] The first lightly doped impurity region and the second lightly doped impurity region may be disposed adjacent to the channel region CH of the transistor TR. For example, the first lightly doped impurity region may be disposed adjacent to the channel region CH so as to overlap with a first sidewall provided at one side of the gate electrode G. The second lightly doped impurity region may be disposed adjacent to the channel region CH so as to overlap with a second sidewall provided at the other side of the gate electrode G. As described above, the distance between the heavily doped impurity regions of the source region S and the drain region D may be increased by the first lightly doped impurity region and the second lightly doped impurity region. Due to the increased distance, the length of the channel region CH may be increased. Accordingly, breakdown phenomena and hot carrier phenomena caused by a short channel may be avoided.

[0111] The source region S of each transistor TR may be connected to the pixel electrode of the corresponding light-emitting layer through a metal layer ME.

[0112] The interlayer insulating layer INS may be disposed on the substrate SUB. The interlayer insulating layer INS may include a plurality of insulating layers stacked along a third direction DR3.

[0113] The light-emitting element layer EMTL may be disposed on the interlayer insulating layer INS. The light-emitting element layer EMTL may include, for example, a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3, which are respectively disposed in different light-emitting regions from each other. For example, the first light-emitting element ED1 of the light-emitting element layer EMTL may be disposed in the first light-emitting region EA1, the second light-emitting element ED2 of the light-emitting element layer EMTL may be disposed in the second light-emitting region EA2, and the third light-emitting element ED3 of the light-emitting element layer EMTL may be disposed in the third light-emitting region EA3.

[0114] The first light-emitting element ED1 may provide red light, the second light-emitting element ED2 may provide green light, and the third light-emitting element ED3 may provide blue light.

[0115] The first light-emitting element ED1 may include a first pixel electrode PE1 (e.g., a first anode electrode), a first light-emitting layer EL1, and a common electrode CE stacked in a third direction DR3. The first light-emitting element ED1 may further include a first hole injection layer HIL1 and a first hole transport layer HTL1, which are sequentially stacked on the first pixel electrode PE1 in the third direction DR3 between the first pixel electrode PE1 and the first light-emitting layer EL1. In addition, the first light-emitting element ED1 may further include a first buffer layer BF1, a common buffer layer CBF, and an electron transport layer mETL, which are sequentially stacked on the first light-emitting layer EL1 in the third direction DR3 between the first light-emitting layer EL1 and the common electrode CE.

[0116] The second light-emitting element ED2 may include a second pixel electrode PE2 (e.g., a second anode electrode), a second light-emitting layer EL2, and a common electrode CE stacked in a third direction DR3. The second light-emitting element ED2 may further include a second hole injection layer HIL2 and a second hole transport layer HTL2, which are sequentially stacked on the second pixel electrode PE2 in the third direction DR3 between the second pixel electrode PE2 and the second light-emitting layer EL2. In addition, the second light-emitting element ED2 may further include a second buffer layer BF2, a common buffer layer CBF, and an electron transport layer mETL, which are sequentially stacked on the second light-emitting layer EL2 in the third direction DR3 between the second light-emitting layer EL2 and the common electrode CE.

[0117] The third light-emitting element ED3 may include a third pixel electrode PE3 (e.g., a third anode electrode), a third light-emitting layer EL3, and a common electrode CE stacked in a third direction DR3. The third light-emitting element ED3 may further include a third hole injection layer HIL3 and a third hole transport layer HTL3, which are sequentially stacked on the third pixel electrode PE3 in the third direction DR3 between the third pixel electrode PE3 and the third light-emitting layer EL3. In addition, the third light-emitting element ED3 may further include a third buffer layer BF3, a common buffer layer CBF, and an electron transport layer mETL, which are sequentially stacked on the third light-emitting layer EL3 in the third direction DR3 between the third light-emitting layer EL3 and the common electrode CE.

[0118] The common buffer layer CBF, the electron transport layer mETL, and the common electrode CE can be common layers that are commonly used for each of the light-emitting elements ED1 to ED3. In other words, the plurality of light-emitting elements ED1 to ED3 of the light-emitting element layer EMTL can share the common buffer layer CBF, the electron transport layer mETL, and the common electrode CE with each other.

[0119] Each of the light-emitting layers EL1 to EL3 can include an organic material to emit light of a desired color (e.g., a predetermined color). For example, the organic material layer can include a host and a dopant. The organic material layer can include a suitable material for emitting light of a desired color (e.g., a predetermined color), and can be formed by using a phosphorescent material or a fluorescent material.

[0120] For example, the first light-emitting layer EL1 can provide light of a first color (e.g., red). Thus, the organic material layer of the first light-emitting layer EL1 can include a host material containing carbazole biphenyl (CBP) or 1,3-bis(carbazol-9-yl)benzene (mCP), and can include a phosphorescent material that includes a dopant containing at least one selected from PIQIr(acac) (bis(1-phenylisoquinoline)acetylacetonatoiridium), PQIr(acac) (bis(1-phenylquinoline)acetylacetonatoiridium), PQIr(tris(1-phenylquinoline)iridium), and PtOEP (octaethylporphyrin platinum). As another example, the organic material layer of the first light-emitting layer EL1 of the first light-emitting region EA1 can be a fluorescent material containing PBD:Eu(DBM)3(Phen) (europium(III) tris(dibenzoylmethane) mono(phenanthroline)) or perylene, but the present disclosure is not limited thereto.

[0121] The second light-emitting layer EL2 can provide light of a second color (e.g., green). Thus, the organic material layer of the second light-emitting layer EL2 can include a host material containing CBP or mCP, and can include a phosphorescent material that includes a dopant material containing Ir(ppy)3 (fac-tris(2-phenylpyridine)iridium). As another example, the organic material layer of the second light-emitting layer EL2 of the second light-emitting region EA2 that emits light of the second color can be a fluorescent material containing Alq3 (aluminum tris(8-hydroxyquinoline)), but the present disclosure is not limited thereto.

[0122] The third light-emitting layer EL3 can provide light of a third color (e.g., blue). Thus, the organic material layer of the third light-emitting layer EL3 can include a host material containing CBP or mCP, and can include a phosphorescent material that includes a dopant material containing (4,6-F2ppy)2IrPic or L2BD111, but the present disclosure is not limited thereto.

[0123] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be connected to the source region S of the transistor TR through contact holes in the interlayer insulating layer INS (e.g., penetrating the interlayer insulating layer INS).

[0124] The first pixel electrode PE1 may be set to correspond to the first emission region EA1, the second pixel electrode PE2 may be set to correspond to the second emission region EA2, and the third pixel electrode PE3 may be set to correspond to the third emission region EA3.

[0125] The pixel defining layer PDL may be disposed on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

[0126] The pixel defining layer PDL may define each of the light emitting regions of the pixels PX1 to PX3 (e.g., the first emission region EA1 of the first pixel PX1, the second emission region EA2 of the second pixel PX2, and the third emission region EA3 of the third pixel PX3). In this way, the pixel defining layer PDL may be set to expose partial regions of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The pixel defining layer PDL may cover the edges of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The pixel defining layer PDL may be formed of an inorganic layer. The pixel defining layer PDL may be formed of an organic layer, such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0127] The hole injection layer may be disposed on each of the pixel electrodes PE1, PE2, and PE3. For example, the first hole injection layer HIL1 may be disposed on the first pixel electrode PE1, the second hole injection layer HIL2 may be disposed on the second pixel electrode PE2, and the third hole injection layer HIL3 may be disposed on the third pixel electrode PE3.

[0128] The hole transport layer may be disposed on each of the hole injection layers HIL1 to HIL3. For example, the first hole transport layer HTL1 may be disposed on the first hole injection layer HIL1, the second hole transport layer HTL2 may be disposed on the second hole injection layer HIL2, and the third hole transport layer HTL3 may be disposed on the third hole injection layer HIL3.

[0129] The light emitting layer may be disposed on each of the hole transport layers HTL1 to HTL3. For example, the first light emitting layer EL1 may be disposed on the first hole transport layer HTL1, the second light emitting layer EL2 may be disposed on the second hole transport layer HTL2, and the third light emitting layer EL3 may be disposed on the third hole transport layer HTL3.

[0130] The buffer layer may be disposed on each of the light-emitting layers EL1 to EL3. For example, the first buffer layer BF1 may be disposed on the first light-emitting layer EL1, the second buffer layer BF2 may be disposed on the second light-emitting layer EL2, and the third buffer layer BF3 may be disposed on the third light-emitting layer EL3. The first buffer layer BF1, the second buffer layer BF2, and the third buffer layer BF3 are physically separated from each other.

[0131] The common buffer layer CBF may be disposed on each of the buffer layers BF1 to BF3. For example, the common buffer layer CBF may overlap with the first buffer layer BF1, the second buffer layer BF2, the third buffer layer BF3, the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the first light-emitting region EA1, the second light-emitting region EA2, the third light-emitting region EA3, and the pixel defining layer PDL. In an embodiment, the common buffer layer CBF may be further disposed on the first side and the second side of each of the light-emitting layers EL1 to EL3, the first side and the second side of each of the hole injection layers HIL1 to HIL3, the first side and the second side of each of the hole transport layers HTL1 to HTL3, and the first side and the second side of each of the buffer layers BF1 to BF3.

[0132] The electron transport layer mETL may be disposed on the common buffer layer CBF. For example, the electron transport layer mETL may be disposed on the common buffer layer CBF to overlap with the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the first light-emitting region EA1, the second light-emitting region EA2, the third light-emitting region EA3, and the pixel defining layer PDL. In an embodiment, the electron transport layer mETL may be disposed on the common buffer layer CBF to surround the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 (e.g., around the periphery of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3). For example, in a plan view, the electron transport layer mETL may surround each of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 (e.g., around the periphery of each of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3). Accordingly, the occurrence of lateral leakage current between adjacent light-emitting layers can be suppressed. Accordingly, the deterioration of image quality due to color mixing between adjacent pixels can be minimized or reduced.

[0133] The common electrode CE can be disposed on the electron transport layer mETL. For example, the common electrode CE can be disposed on the electron transport layer mETL to overlap with the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the first light-emitting region EA1, the second light-emitting region EA2, the third light-emitting region EA3, and the pixel defining layer PDL. In a top-emission structure, the common electrode CE can be formed of a transparent conductive material (TCO) (such as indium tin oxide (ITO) and / or indium zinc oxide (IZO)), or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or a suitable alloy of magnesium (Mg) and silver (Ag)). When the common electrode CE is formed of a semi-transmissive conductive material, the light-emitting efficiency can be enhanced by a microcavity.

[0134] The encapsulation layer ENC can be disposed on the common electrode CE. The encapsulation layer ENC can cover the upper surface and the side of the light-emitting element layer EMTL, and can protect the light-emitting element layer EMTL. The encapsulation layer ENC can include at least one inorganic layer and at least one organic layer to encapsulate the light-emitting element layer EMTL. The encapsulation layer ENC can include at least one inorganic layer to prevent or substantially prevent oxygen and / or moisture from penetrating into the light-emitting element layer EMTL. The encapsulation layer ENC can also include at least one organic layer to protect the light-emitting element layer EMTL from particles such as dust. For example, the encapsulation layer ENC can include a first encapsulating inorganic layer, an encapsulating organic layer, and a second encapsulating inorganic layer, which can be sequentially stacked on the common electrode CE along the third direction DR3. For example, the first encapsulating inorganic layer can be disposed on the common electrode CE, the encapsulating organic layer can be disposed on the first encapsulating inorganic layer, and the second encapsulating inorganic layer can be disposed on the encapsulating organic layer. The first encapsulating inorganic layer and the second encapsulating inorganic layer can be formed of a multi-layer structure in which one or more inorganic layers among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The encapsulating organic layer can be an organic layer including, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0135] Figure 7 is a magnified view showing Figure 6 the first light-emitting element ED1.

[0136] Referring to Figure 7 , the first side S1 and the second side S2 (or may also be described as opposite sides) of the first light-emitting layer EL1 facing away from each other can be disposed on the pixel defining layer PDL. Each of the first side S1 and the second side S2 can have a linear shape.

[0137] The first side S1 may have a linear shape inclined at an angle (e.g., a predetermined angle) with respect to the upper surface of the pixel defining layer PDL. For example, the angle θ (e.g., an interior angle) formed by the upper surface of the pixel defining layer PDL and the first side S1 of the first light emitting layer EL1 may be greater than 60° and less than or equal to 90°. The angle formed by the upper surface of the pixel defining layer PDL and the second side S2 of the first light emitting layer EL1 may be the same as or different from the angle formed by the upper surface of the pixel defining layer PDL and the first side S1 of the first light emitting layer EL1. For example, the angle (e.g., an interior angle) formed by the upper surface of the pixel defining layer PD1 and the second side S2 of the first light emitting layer EL1 may be greater than 60° and less than or equal to 90°.

[0138] The distance between the first side S1 and the second side S2 of the first light emitting layer EL1 may gradually decrease in a direction away from the pixel defining layer PDL. For example, the distance between the first side S1 and the second side S2 may gradually decrease along the third direction DR3.

[0139] Both sides (e.g., opposite sides) of the first functional layer (e.g., at least one of the first hole injection layer HIL1 and the first hole transport layer HTL1) disposed between the first light emitting layer EL1 and the first pixel electrode PE1 may respectively have a shape that is the same as or substantially the same as the shape of the first side S1 and the second side S2 of the first light emitting layer EL1 as described above (e.g., a linear shape). In this case, both sides of the first functional layer may be disposed on the pixel defining layer PDL. In addition, the distance between both sides of the first functional layer may gradually decrease in a direction away from the pixel defining layer PDL. For example, the distance between both sides of the first functional layer may gradually decrease along the third direction DR3. The angle formed by the pixel defining layer PDL and one side of the functional layer may be greater than 60° and less than or equal to 90°. In addition, the angle between the pixel defining layer PDL and the other side of the functional layer may be greater than 60° and less than or equal to 90°.

[0140] Both sides (e.g., opposite sides) of the second functional layer (e.g., the first buffer layer BF1) disposed between the first light emitting layer EL1 and the common buffer layer CBF may respectively have a shape that is the same as or substantially the same as the shape of the first side S1 and the second side S2 of the first light emitting layer EL1 as described above (e.g., a linear shape). Both sides of the second functional layer may be disposed on the pixel defining layer PDL. The distance between both sides of the second functional layer may gradually decrease in a direction away from the pixel defining layer PDL. For example, the distance between both sides of the second functional layer may gradually decrease along the third direction DR3. The angle formed by the pixel defining layer PDL and one side of the second functional layer may be greater than 60° and less than or equal to 90°. In addition, the angle formed by the pixel defining layer PDL and the other side of the second functional layer may be greater than 60° and less than or equal to 90°.

[0141] On both sides (e.g., opposite sides) of the second light-emitting layer EL2, shapes and angles that are the same as or substantially the same as the shapes and angles of both sides S1 and S2 of the first light-emitting layer EL1 described above (e.g., interior angles greater than 60° and less than or equal to 90°) can be respectively provided.

[0142] In addition, on both sides (e.g., opposite sides) of the first functional layer of the second light-emitting layer EL2 (e.g., at least one of the second hole injection layer HIL2 and the second hole transport layer HTL2), shapes and angles that are the same as or substantially the same as the shapes and angles of both sides S1 and S2 of the first light-emitting layer EL1 described above (e.g., interior angles greater than 60° and less than or equal to 90°) can be respectively provided.

[0143] In addition, on both sides (e.g., opposite sides) of the second functional layer of the second light-emitting layer EL2 (e.g., the second buffer layer BF2), shapes and angles that are the same as or substantially the same as the shapes and angles of both sides S1 and S2 of the first light-emitting layer EL1 described above (e.g., interior angles greater than 60° and less than or equal to 90°) can be respectively provided.

[0144] In addition, on both sides (e.g., opposite sides) of the third light-emitting layer EL3, shapes and angles that are the same as or substantially the same as the shapes and angles of both sides S1 and S2 of the first light-emitting layer EL1 described above (e.g., interior angles greater than 60° and less than or equal to 90°) can be respectively provided.

[0145] In addition, as described above, on both sides (e.g., opposite sides) of the first functional layer of the third light-emitting layer EL3 (e.g., at least one of the third hole injection layer HIL3 and the third hole transport layer HTL3), shapes and angles that are the same as or substantially the same as the shapes and angles of both sides S1 and S2 of the first light-emitting layer EL1 can be respectively provided (e.g., interior angles greater than 60° and less than or equal to 90°).

[0146] In addition, as described above, on both sides (e.g., opposite sides) of the second functional layer of the third light-emitting layer EL3 (e.g., the third buffer layer BF3), shapes and angles that are the same as or substantially the same as the shapes and angles of both sides S1 and S2 of the first light-emitting layer EL1 can be respectively provided (e.g., interior angles greater than 60° and less than or equal to 90°).

[0147] Since each of the first light-emitting layer EL1, the second light-emitting layer EL2, the third light-emitting layer EL3, the first hole injection layer HIL1, the second hole injection layer HIL2, the third hole injection layer HIL3, the first hole transport layer HTL1, the second hole transport layer HTL2, the third hole transport layer HTL3, the first buffer layer BF1, the second buffer layer BF2, and the third buffer layer BF3 has the shape and angle as described above on both sides, the light-emitting layer, the first functional layer, and the second functional layer may not be provided between the pixel definition layer PDL and the common buffer layer CBF directly on the pixel definition layer PDL. Accordingly, tail defects and mask shadow defects caused by using an existing fine metal mask (FMM) may not be generated. Accordingly, the occurrence of lateral leakage current between adjacent light-emitting layers may be suppressed. As a result, deterioration of image quality due to color mixing between adjacent pixels may be minimized or reduced.

[0148] Since the foregoing light-emitting layer, hole injection layer, hole transport layer, and buffer layer may be formed by a photolithography process (e.g., an etching process using a photoresist pattern as a mask, which will be described in more detail below), each of the first light-emitting layer EL1, the second light-emitting layer EL2, the third light-emitting layer EL3, the first hole injection layer HIL1, the second hole injection layer HIL2, the third hole injection layer HIL3, the first hole transport layer HTL1, the second hole transport layer HTL2, the third hole transport layer HTL3, the first buffer layer BF1, the second buffer layer BF2, and the third buffer layer BF3 may have the shape and angle as described above on both sides. Hereinafter, a method for manufacturing a display device according to one or more embodiments will be described in more detail with reference to Figures 8 to 24 FIG.

[0149] Figures 8 to 24 is a cross-sectional view showing a method for manufacturing a display device according to one or more embodiments.

[0150] First, as Figure 8 shown, a substrate SUB may be prepared, and a transistor TR may be formed at the substrate SUB (e.g., formed in or on the substrate SUB). An interlayer insulating layer INS may be provided on the substrate SUB. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be provided on the interlayer insulating layer INS. The first pixel electrode PE1 may be connected to the transistor TR of the first pixel PX1 through one or more contact holes passing through the interlayer insulating layer INS. The second pixel electrode PE2 may be connected to the transistor TR of the second pixel PX2 through one or more contact holes passing through the interlayer insulating layer INS. The third pixel electrode PE3 may be connected to the transistor TR of the third pixel PX3 through one or more contact holes passing through the interlayer insulating layer INS.

[0151] Next, as shown in Figure 8 a pixel defining layer PDL may be provided on the interlayer insulating layer INS, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. Portions of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 except for their respective edges may be exposed through corresponding openings of the pixel defining layer PDL. For example, the first light emitting region EA1 of the first pixel PX1, the second light emitting region EA2 of the second pixel PX2, and the third light emitting region EA3 of the third pixel PX3 may be defined by the pixel defining layer PDL. According to the method for manufacturing a display device according to an embodiment, since a light emitting layer or the like can be formed by a photolithography process without using an existing fine metal mask, the pixel defining layer PDL may not need to have a large thickness. Thus, according to an embodiment, the pixel defining layer PDL may include an inorganic material that can have a lower (e.g., reduced) thickness (e.g., may be made of an inorganic material having a lower (e.g., reduced) thickness).

[0152] As shown in Figure 9 a first hole injection layer HIL1, a first hole transport layer HTL1, a first light emitting layer EL1, a first buffer layer BF1, and a first sacrificial layer SAL1 may be sequentially provided on the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the pixel defining layer PDL along a third direction DR3. For example, the first hole injection layer HIL1, the first hole transport layer HTL1, the first light emitting layer EL1, the first buffer layer BF1, and the first sacrificial layer SAL1 may be provided on the entire or substantially entire surface of the substrate SUB.

[0153] Next, as shown in Figure 10 a first photoresist pattern PR1 may be provided on the first sacrificial layer SAL1 corresponding to the first light emitting region EA1 of the first pixel PX1.

[0154] Then, as shown in Figure 11 an etching process may be performed using the first photoresist pattern PR1 as a mask. The etching process may be a dry etching process. The first sacrificial layer SAL1 may prevent or substantially prevent the first buffer layer BF1 below the first sacrificial layer SAL1 from being damaged during the etching process. The first sacrificial layer SAL1 may include a metal. For example, the first sacrificial layer SAL1 may include at least one of aluminum and silver. Portions of the first hole injection layer HIL1, the first hole transport layer HTL1, the first light emitting layer EL1, the first buffer layer BF1, and the first sacrificial layer SAL1 that are not covered by the first photoresist pattern PR1 may be removed by Figure 11The etching process shown in removes. For example, the first hole injection layer HIL1, the first hole transport layer HTL1, the first light-emitting layer EL1, the first buffer layer BF1, and the first sacrificial layer SAL1 can be patterned by an etching process to be disposed between the first pixel electrode PE1 and the first photoresist pattern PR1.

[0155] As Figure 12 shown in, the first photoresist pattern PR1 can be removed (see Figure 11 ). For example, the first photoresist pattern PR1 can be removed by an ashing process.

[0156] As Figure 13 shown in, the second hole injection layer HIL2, the second hole transport layer HTL2, the second light-emitting layer EL2, the second buffer layer BF2, and the second sacrificial layer SAL2 can be sequentially disposed along the third direction DR3 on the first sacrificial layer SAL1, the second pixel electrode PE2, the third pixel electrode PE3, and the pixel defining layer PDL. For example, the second hole injection layer HIL2, the second hole transport layer HTL2, the second light-emitting layer EL2, the second buffer layer BF2, and the second sacrificial layer SAL2 can be disposed on the entire or substantially entire surface of the substrate SUB.

[0157] Next, as Figure 14 shown in, a second photoresist pattern PR2 can be disposed on the second sacrificial layer SAL2 to correspond to the second light-emitting region EA2 of the second pixel PX2.

[0158] Then, as Figure 15 shown in, an etching process can be performed using the second photoresist pattern PR2 as a mask. The etching process can be a dry etching process. The second sacrificial layer SAL2 can prevent or substantially prevent the second buffer layer BF2 below the second sacrificial layer SAL2 from being damaged during the etching process. The second sacrificial layer SAL2 can include a metal. For example, the second sacrificial layer SAL2 can include at least one of aluminum and silver. The portions of the second hole injection layer HIL2, the second hole transport layer HTL2, the second light-emitting layer EL2, the second buffer layer BF2, and the second sacrificial layer SAL2 that are not covered by the second photoresist pattern PR2 can be removed by an etching process as Figure 15 shown in. For example, the second hole injection layer HIL2, the second hole transport layer HTL2, the second light-emitting layer EL2, the second buffer layer BF2, and the second sacrificial layer SAL2 can be patterned by an etching process to be disposed between the second pixel electrode PE2 and the second photoresist pattern PR2.

[0159] Next, as Figure 16 shown in, the second photoresist pattern PR2 can be removed (see Figure 15)。For example, the second photoresist pattern PR2 can be removed by an ashing process.

[0160] As Figure 17 shown, a third hole injection layer HIL3, a third hole transport layer HTL3, a third light-emitting layer EL3, a third buffer layer BF3, and a third sacrificial layer SAL3 can be sequentially disposed along a third direction DR3 on a first sacrificial layer SAL1, a second sacrificial layer SAL2, a third pixel electrode PE3, and a pixel definition layer PDL. For example, the third hole injection layer HIL3, the third hole transport layer HTL3, the third light-emitting layer EL3, the third buffer layer BF3, and the third sacrificial layer SAL3 can be disposed on the entire or substantially the entire surface of a substrate SUB.

[0161] Next, as Figure 18 shown, a third photoresist pattern PR3 can be disposed on the third sacrificial layer SAL3 to correspond to a third light-emitting region EA3 of a third pixel PX3.

[0162] Then, as Figure 19 shown, an etching process can be performed using the third photoresist pattern PR3 as a mask. The etching process can be a dry etching process. The third sacrificial layer SAL3 can prevent or substantially prevent the third buffer layer BF3 below the third sacrificial layer SAL3 from being damaged during the etching process. The third sacrificial layer SAL3 can include a metal. For example, the third sacrificial layer SAL3 can include at least one of aluminum and silver. A portion of the third hole injection layer HIL3, the third hole transport layer HTL3, the third light-emitting layer EL3, the third buffer layer BF3, and the third sacrificial layer SAL3 that is not covered by the third photoresist pattern PR3 can be removed by Figure 19 the etching process. For example, the third hole injection layer HIL3, the third hole transport layer HTL3, the third light-emitting layer EL3, the third buffer layer BF3, and the third sacrificial layer SAL3 can be patterned by the etching process to be disposed between the third pixel electrode PE3 and the third photoresist pattern PR3.

[0163] Next, as Figure 20 shown, the third photoresist pattern PR3 can be removed (see Figure 19 ). For example, the third photoresist pattern PR3 can be removed by an ashing process.

[0164] Then, as Figure 21As shown, the first sacrificial layer SAL1, the second sacrificial layer SAL2, and the third sacrificial layer SAL3 can be removed. For example, the first sacrificial layer SAL1, the second sacrificial layer SAL2, and the third sacrificial layer SAL3 can be removed by wet etching. At this time, the etchant for wet etching can have a sufficiently large etching rate so that only the first sacrificial layer SAL1, the second sacrificial layer SAL2, and the third sacrificial layer SAL3 can be selectively removed by the etchant.

[0165] Then, the substrate SUB from which the first sacrificial layer SAL1 to the third sacrificial layer SAL3 have been removed can be cleaned. The cleaning solution for the cleaning process can include deionized water.

[0166] The cleaned substrate SUB can be placed inside a vacuum chamber. In a vacuum state, the substrate SUB can be dried at a high temperature. For example, the substrate SUB can be dried at a temperature of about 90 °C. Any moisture remaining in the substrate SUB can be removed through the drying process.

[0167] As Figure 22 shown, a common buffer layer CBF can be disposed on the first buffer layer BF1, the second buffer layer BF2, the third buffer layer BF3, and the pixel defining layer PDL in a vacuum chamber. For example, when in a vacuum state, the common buffer layer CBF can be formed on the first buffer layer BF1, the second buffer layer BF2, the third buffer layer BF3, and the pixel defining layer PDL.

[0168] Then, as Figure 23 shown, an electron transport layer mETL can be disposed on the common buffer layer CBF in a vacuum chamber. For example, the electron transport layer mETL can be formed on the common buffer layer CBF in a vacuum state.

[0169] Then, as Figure 24 shown, a common electrode CE can be disposed on the electron transport layer mETL in a vacuum chamber. For example, the common electrode CE can be formed on the electron transport layer mETL in a vacuum state.

[0170] Next, as Figure 6 shown, a packaging layer ENC can be disposed on the common electrode CE in a vacuum chamber. For example, the packaging layer ENC can be formed on the common electrode CE in a vacuum state.

[0171] In a method for manufacturing a display device according to one or more embodiments, since a light-emitting layer or the like can be manufactured by a photolithography process without using an existing fine metal mask, a high-resolution product having a narrow interval between adjacent pixels can be manufactured. In addition, since the light-emitting layer according to one or more embodiments can be formed by a photolithography process, the light-emitting layer can have a clear side without tail defects, and thus, defects that may be caused by lateral leakage current can be suppressed.

[0172] As used herein, a tail defect may refer to a portion of a material of a light-emitting layer that is formed to overlap a non-light-emitting region in addition to a light-emitting region due to an interval between a fine metal mask and a substrate when the light-emitting layer is formed by a deposition process using the fine metal mask. In other words, a tail defect formed in a portion overlapping the non-light-emitting region may appear as a mask shadow defect. Tail defects and mask shadow defects may cause lateral leakage current as described above.

[0173] The foregoing is an illustration of some embodiments of the present disclosure and should not be construed as a limitation of the present disclosure. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications in the embodiments are possible without departing from the spirit and scope of the present disclosure. It will be understood that unless otherwise described, the description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise specifically stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, it will be understood that the foregoing is an illustration of various example embodiments and should not be construed as limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments as well as other example embodiments are intended to be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents.

Claims

1. A display device, characterized in that: The display device comprises: substrate; a first electrode on the substrate; a light-emitting layer, on the first electrode; a pixel defining layer on the light emitting layer; and a second electrode, on the light-emitting layer, The first side and the second side of the light emitting layer opposite to each other are located on the pixel defining layer, and the first side and the second side of the light emitting layer each have a straight line shape inclined at an angle relative to the upper surface of the pixel defining layer.

2. The display device according to claim 1, characterized in that An angle between the upper surface of the pixel defining layer and the first side of the light emitting layer is greater than 60° and less than or equal to 90°, and Wherein, an angle between the upper surface of the pixel defining layer and the second side of the light emitting layer is greater than 60° and less than or equal to 90°.

3. The display device according to claim 1, characterized in that A distance between the first side of the light emitting layer and the second side of the light emitting layer gradually decreases in a direction away from the pixel defining layer.

4. The display device according to claim 1, characterized in that The display device further includes a first functional layer between the first electrode and the light emitting layer.

5. The display device according to claim 4, characterized in that: A first side and a second side of the first functional layer opposite to each other are located on the pixel defining layer, and the first side and the second side of the first functional layer each have a straight line shape inclined at an angle relative to the upper surface of the pixel defining layer.

6. The display device according to claim 5, characterized in that: An angle between the upper surface of the pixel defining layer and the first side of the first functional layer is greater than 60° and less than or equal to 90°, and Wherein, an angle between the upper surface of the pixel defining layer and the second side of the first functional layer is greater than 60° and less than or equal to 90°.

7. The display device according to claim 5, characterized in that: A distance between the first side of the first functional layer and the second side of the first functional layer gradually decreases in a direction away from the pixel defining layer.

8. The display device according to claim 4, characterized in that: The first functional layer comprises: a hole injection layer on the first electrode; and A hole transport layer is on the hole injection layer.

9. The display device according to claim 1, characterized in that: The display device further includes a second functional layer between the light emitting layer and the second electrode.

10. The display device according to claim 9, characterized in that: The first side and the second side of the second functional layer, which are opposite to each other, are located on the pixel defining layer. wherein the first side and the second side of the second functional layer each have a straight line shape inclined at an angle relative to the upper surface of the pixel defining layer, wherein an angle between the upper surface of the pixel defining layer and the first side of the second functional layer is greater than 60° and less than or equal to 90°, and Wherein, an angle between the upper surface of the pixel defining layer and the second side of the second functional layer is greater than 60° and less than or equal to 90°.

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