Improved LDO circuit without on-chip capacitor

Abstract

The utility model provides an improved on-chip capacitor-free LDO circuit, which comprises an error amplifier EA, a buffer stage Buffer, a PMOS power tube Mp, a resistor R1 and a resistor R2, the buffer stage Buffer is realized by adopting an NMOS + PMOS combination, and an NMOS tube of the buffer stage Buffer is changed into a native NMOS tube from a common NMOS tube. According to the circuit, the problem that the LDO cannot work normally under the conditions of zero load and light load can be solved, and normal work under the conditions of heavy load and low power supply voltage can be ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, in particular to an improved capacitorless LDO circuit. Background Art

[0002] In a capacitorless LDO, there is a structure of operational amplifier + Buffer + power transistor. The structure is as Figure 1 shown, where EA is an error amplifier (operational amplifier). Due to its input virtual short characteristic, Vref≈Vfb. The power transistor is Mp, which is a PMOS (NMOS can also be used. In this case, the inverting terminal and non-inverting terminal of EA need to be swapped to ensure negative feedback in the system). Therefore, Vout = Vref*(R1 + R2) / R1. The function of the buffer stage Buffer is to reduce the impedance of node B. Since Mp is a power transistor with a relatively large size and thus a relatively large gate capacitance, reducing the impedance of node B can pull the parasitic node frequency of node B farther away, which is beneficial to the stability of the LDO and also beneficial to the load transient response of the LDO.

[0003] The Buffer stage is often based on a source follower (SF). Figure 2 It is an LDO circuit that uses super SF (SSF) to implement the Buffer stage. Ibias1 - 3 in the figure are bias currents. Figure 2 Transistors Mp1 and Mn1 in it form a super SF (SSF) structure. Among them, Mp1 is a source follower. After adding Mn1, it becomes an SSF structure, which can greatly reduce the output resistance of the Buffer stage. SSF has better load driving ability compared with an ordinary SF stage. However, this structure has an obvious disadvantage: when the LDO is under a large current load (heavy load), the operating power supply voltage of the entire LDO cannot be made low. The reason is that in the case of a large current, the VGS voltage of the power transistor Mp needs to be very large, so the voltage VB of node B is relatively low. And the source follower structure of Mp1 transistor also requires a VGS voltage, so the voltage VA of node A is lower than VB by a VGS voltage. Estimated by the transistor threshold voltage of 0.7V, when the LDO is under heavy load, the VGS voltage required by the power transistor Mp is assumed to be 1.5V, and the VGS voltage of Mp1 transistor is assumed to be 0.9V. Therefore, the voltage of VA is 1.5 + 0.9 = 2.4V lower than the power supply voltage. Plus, node A is the output of the operational amplifier and also requires a certain voltage. So this architecture is difficult to work at a power supply voltage below 2.5V. Summary of the Utility Model

[0004] In view of the defects in the prior art, the present utility model provides an improved capacitorless LDO circuit, which includes an error amplifier EA, a buffer stage Buffer, a PMOS power transistor Mp, and resistors R1 and R2. The inverting input terminal of the error amplifier EA is connected to a reference voltage Vref, the output terminal of the error amplifier EA is connected to the input terminal of the buffer stage Buffer, the output terminal of the buffer stage Buffer is connected to the gate of the PMOS power transistor Mp, the source terminals of the error amplifier EA, the buffer stage Buffer, and the PMOS power transistor Mp are all connected to a power supply voltage VDD. The resistors R1 and R2 form a feedback network, wherein the first terminal of the resistor R2 is connected to the drain of the PMOS power transistor Mp, the second terminal of the resistor R2 is connected to the first terminal of the resistor R1, and the second terminal of the resistor R2 is connected to the ground terminal. The node voltage between the drain of the PMOS power transistor Mp and the first terminal of the resistor R2 is an output voltage Vout, and the node voltage between the second terminal of the resistor R2 and the first terminal of the resistor R1 is a feedback voltage Vfb. The feedback voltage Vfb is connected to the non-inverting input terminal of the differential amplifier EA;

[0005] The buffer stage Buffer adopts a super source follower, which includes bias currents Ibias1 to 3, a native NMOS transistor Mn_native, and a PMOS transistor Mp1. The gate of the native NMOS transistor Mn_native is connected to the output terminal of the error amplifier EA, the drain of the native NMOS transistor Mn_native and the gate of the PMOS transistor Mp1 are both connected to the bias current Ibias1, the source of the native NMOS transistor Mn_native is connected to the bias current Ibias2, the source of the PMOS transistor Mp1 is connected to the power supply voltage VDD, the drain of the PMOS transistor Mp1 is connected to the bias current Ibias3, and the source of the native NMOS transistor Mn_native and the drain of the PMOS transistor Mp1 are both connected to the gate of the PMOS power transistor Mp.

[0006] Compared with the prior art, the present utility model has the following beneficial effects:

[0007] The buffer stage Buffer of the circuit of the present utility model is implemented by a combination of NMOS and PMOS, and the NMOS transistor of the buffer stage Buffer is changed from an ordinary NMOS transistor to a native NMOS transistor. In this way, the LDO can not only work normally under heavy load and low power supply voltage, but also ensure normal operation under no load or light load. Description of the Drawings

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0009] Figure 1 It is a structural block diagram of an existing LDO structure without on-chip capacitors;

[0010] Figure 2 It is a schematic structural diagram of an existing LDO circuit that uses super SF (SSF) to implement the Buffer stage;

[0011] Figure 3 It is a schematic structural diagram of an improved LDO circuit without on-chip capacitors provided by an embodiment of the present disclosure. Detailed implementation manners

[0012] The following will describe the embodiments of the present invention in more detail with reference to the drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not used to limit the protection scope of the present invention.

[0013] The following will specifically describe the technical solutions of the present invention with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0014] Figure 3 An improved LDO circuit without on-chip capacitors provided by an embodiment of the present disclosure, as Figure 3As shown, it includes an error amplifier EA, a buffer stage Buffer, a PMOS power transistor Mp, and resistors R1 and R2. The inverting input terminal of the error amplifier EA is connected to the reference voltage Vref. The output terminal of the error amplifier EA is connected to the input terminal of the buffer stage Buffer. The output terminal of the buffer stage Buffer is connected to the gate of the PMOS power transistor Mp. The source terminals of the error amplifier EA, the buffer stage Buffer, and the PMOS power transistor Mp are all connected to the power supply voltage VDD. The resistors R1 and R2 form a feedback network. Among them, the first terminal of the resistor R2 is connected to the drain of the PMOS power transistor Mp, the second terminal is connected to the first terminal of the resistor R1, and the second terminal is connected to the ground terminal. The node voltage between the drain of the PMOS power transistor Mp and the first terminal of the resistor R2 is the output voltage Vout. The node voltage between the second terminal of the resistor R2 and the first terminal of the resistor R1 is the feedback voltage Vfb. The feedback voltage Vfb is connected to the non-inverting input terminal of the differential amplifier EA;

[0015] The buffer stage Buffer adopts a super source follower, which includes bias currents Ibias1 to 3, a native NMOS transistor Mn_native, and a PMOS transistor Mp1. The gate of the native NMOS transistor Mn_native is connected to the output terminal of the error amplifier EA. The drain of the native NMOS transistor Mn_native and the gate of the PMOS transistor Mp1 are both connected to the bias current Ibias1. The source of the native NMOS transistor Mn_native is connected to the bias current Ibias2. The source of the PMOS transistor Mp1 is connected to the power supply voltage VDD. The drain of the PMOS transistor Mp1 is connected to the bias current Ibias3. The source of the native NMOS transistor Mn_native and the drain of the PMOS transistor Mp1 are both connected to the gate of the PMOS power transistor Mp.

[0016] In this embodiment, the buffer stage Buffer is implemented by a combination of native NMOS + PMOS. The problem that the LDO cannot work properly under heavy load and low voltage no longer exists. Because when under heavy load, the PMOS power transistor Mp requires a large VGS, and the voltage VA at node A is higher than the voltage VB at node B. At this time, the power supply voltage only needs to satisfy the VGS of the PMOS power transistor Mp. And the NMOS transistor in the buffer stage Buffer is changed from an ordinary NMOS transistor to a native NMOS transistor. The native NMOS transistor is a special NMOS transistor in the standard CMOS process. The difference between it and the ordinary NMOS transistor is that the threshold voltage of the native NMOS transistor is near 0 (depending on the process and process corner, the threshold voltage of the native transistor can be negative, zero, or positive, but generally fluctuates in a small range near 0 voltage or negative voltage).

[0017] If the NMOS transistor of the buffer stage Buffer does not use a native NMOS transistor but directly uses a common NMOS transistor, the LDO cannot work properly under no-load or light-load conditions. The following analyzes the operating state of the LDO with a common NMOS transistor under no-load (the principle of light-load is the same): Under no-load conditions, the PMOS power transistor Mp requires a very small VGS voltage. Roughly estimated, assuming that VGS is slightly lower than the threshold voltage of 0.7V, it is 0.6V, that is, VB = VDD - 0.6V. And the voltage of the VA node is about 0.9V higher than the VB voltage, that is, VA ≈ VB + 0.9V = VDD + 0.3V. In this way, the required VA voltage is higher than the VDD voltage, which is impossible to achieve. The entire LDO circuit cannot work properly under no-load conditions (regardless of the power supply voltage). This is also the reason why the buffer stage Buffer in practice commonly uses a PMOS+NMOS combination instead of an NMOS+PMOS, but the PMOS+NMOS used in the buffer stage Buffer cannot work properly under heavy-load and low power supply voltage conditions.

[0018] Changing the NMOS transistor of the buffer stage Buffer from a common NMOS transistor to a native NMOS transistor can solve the problem that the LDO cannot work properly under no-load and light-load conditions, and there is no problem that the working voltage cannot be lowered under heavy-load conditions. The following is the analysis: Under no-load conditions, the VGS voltage required by the PMOS power transistor Mp is still estimated to be 0.6V, that is, VB = VDD - 0.6V. Due to the 0-threshold voltage characteristic of the native NMOS transistor Mn_native, VA ≈ VB + 0.2V (0.7V less than the 0.9V in the above analysis, which is the threshold voltage), so VA ≈ VDD - 0.6V + 0.2V = VDD - 0.4V. Such a VA is easily achievable, and at this time the LDO circuit can work properly. Considering that the threshold voltage of the native NMOS transistor has a small range of fluctuations, even if a margin of 0.2V is reserved, VA ≈ VDD - 0.2V. At this time, the error amplifier EA using a CLASS AB output structure can still meet the requirements.

[0019] So far in the embodiments of the present invention, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. An improved LDO circuit without on-chip capacitor, characterized in that: It includes an error amplifier EA, a buffer stage Buffer, a PMOS power tube Mp, and resistors R1 and R2, wherein the inverting input terminal of the error amplifier EA is connected to a reference voltage Vref, the output terminal of the error amplifier EA is connected to the input terminal of the buffer stage Buffer, the output terminal of the buffer stage Buffer is connected to the gate of the PMOS power tube Mp, the sources of the error amplifier EA, the buffer stage Buffer, and the PMOS power tube Mp are all connected to a power supply voltage VDD, the resistors R1 and R2 form a feedback network, wherein the first terminal of the resistor R2 is connected to the drain of the PMOS power tube Mp, the second terminal is connected to the first terminal of the resistor R1, and the second terminal is connected to the ground, the node voltage between the drain of the PMOS power tube Mp and the first terminal of R2 is the output voltage Vout, the node voltage between the second terminal of the resistor R2 and the first terminal of the resistor R1 is the feedback voltage Vfb, and the feedback voltage Vfb is connected to the non-inverting input terminal of the difference amplifier EA; The buffer stage Buffer adopts a super source follower, including bias currents Ibias1~3, a native NMOS tube Mn_native and a PMOS tube Mp1, the gate of the native NMOS tube Mn_native is connected to the output end of the error amplifier EA, the drain of the native NMOS tube Mn_native and the gate of the PMOS tube Mp1 are both connected to the bias current Ibias1, the source of the native NMOS tube Mn_native is connected to the bias current Ibias2, the source of the PMOS tube Mp1 is connected to the power supply voltage VDD, the drain of the PMOS tube Mp1 is connected to the bias current Ibias3, and the source of the native NMOS tube Mn_native and the drain of the PMOS tube Mp1 are both connected to the gate of the PMOS power tube Mp.

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