Memory module and electronic equipment
By designing incompletely overlapping chip stacking structures and electrical connection positions in electronic devices, the problem of excessive chip package thickness is solved, and space saving, signal quality improvement and battery usage space are achieved.
Patent Information
- Application Number
- CN202420306557.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-19
- Publication Date
- 2025-06-20
- Estimated Expiration
- 2034-02-19
AI Technical Summary
In existing electronic devices, the chip packaging size is large, the thickness is too high, and the internal space is occupied, which affects the development of the miniaturization of the equipment.
A package structure is designed in which a plurality of chips are stacked on the substrate, and adjacent chips do not completely overlap, forming overlapping regions and non-overlapping regions, and electrical connections are arranged in non-overlapping regions to reduce the need for trace space.
Through this structure, the space occupied during chip stacking is reduced, the thickness is thinner, the trace length is shortened, signal loss is reduced, signal quality is improved, substrate size is saved, and battery space is increased.
Smart Images
Figure CN223006771U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of packaging structures, and in particular, to a packaging structure, a memory module, and an electronic device. Background Art
[0002] Currently, the chip packaging size of electronic devices is relatively large and the thickness is too high, thus occupying too much space inside the electronic device and affecting the miniaturization development of the electronic device.
[0003] Therefore, how to provide a packaging structure that can reduce space occupation has become an urgent problem to be solved. Summary of the Utility Model
[0004] The purpose of the embodiments of this application is to provide a packaging structure, a memory module, and an electronic device.
[0005] To solve the above technical problems, the embodiments of this application provide the following technical solutions:
[0006] The first aspect of this application provides a packaging structure, including:
[0007] A substrate;
[0008] Multiple chips, stacked on the substrate, and at least two adjacent chips among the multiple chips include an overlapping area and a non-overlapping area in the orthographic projection area on the substrate. The chip has an electrical connection part, and the electrical connection part is arranged in the non-overlapping area of the chip.
[0009] In some modified embodiments of the first aspect of this application, the multiple chips are stacked on the substrate in a staggered manner, and the orthographic projection area of each chip on the substrate and the adjacent chip includes the overlapping area and the non-overlapping area.
[0010] In some modified embodiments of the first aspect of this application, an insulating layer is arranged between the overlapping areas of the adjacent chips.
[0011] The second aspect of this application provides a memory module, including:
[0012] A packaging structure, the packaging structure includes a substrate and multiple chips, the multiple chips are stacked on the substrate, and at least two adjacent chips among the multiple chips include an overlapping area and a non-overlapping area in the orthographic projection area on the substrate. The chip has an electrical connection part, and the electrical connection part is arranged in the non-overlapping area of the chip;
[0013] Each chip of the packaging structure is electrically connected to the substrate through the electrical connection part.
[0014] In some modified embodiments of the first aspect of the present application, the multiple chips are stacked in a staggered manner in sequence on the substrate;
[0015] The memory module further includes a plurality of first connection lines, one end of each first connection line is connected to the substrate, and the other end is connected to an electrical connection portion in a non-overlapping area of one of the chips.
[0016] In some modified embodiments of the first aspect of the present application, the chip further has a redistribution layer and an initial electrical connection point located in the middle area, one end of the redistribution layer is connected to the initial electrical connection point, and the other end extends to the non-overlapping area to form the electrical connection portion.
[0017] In some modified embodiments of the first aspect of the present application, the multiple chips are stacked in a staggered manner between adjacent two of the multiple chips; or
[0018] The multiple chips include a first chip, a second chip, a third chip, and a fourth chip stacked in sequence in the thickness direction on the substrate. The first chip has a non-overlapping area on a first side along the first direction of the chip relative to the second chip, and the third chip has a non-overlapping area on a second side along the first direction relative to the fourth chip. The first direction is perpendicular to the thickness direction of the chip.
[0019] In some modified embodiments of the first aspect of the present application, the multiple chips at least include a first chip and a second chip arranged adjacent to each other;
[0020] The memory module further includes a plurality of second connection lines and a plurality of third connection lines. The first end of the second connection line is connected to the substrate, the second end of the second connection line is connected to the electrical connection portion of the first chip, the first end of the third connection line is connected to the second end of the second connection line, and the second end of the third connection line is connected to the electrical connection portion of the second chip.
[0021] In some modified embodiments of the first aspect of the present application, when at least one of the first connection line, the second connection line, or the third connection line is connected to the electrical connection portion, the at least one has a length along the thickness direction above the corresponding electrical connection portion that is at least greater than the thickness of the insulating layer of the corresponding encapsulation structure.
[0022] A third aspect of the present application provides an electronic device, including a memory module, the memory module including a package structure, the package structure including a substrate and a plurality of chips, the plurality of chips being stacked on the substrate, at least two adjacent chips among the plurality of chips having a projection area on the substrate including an overlapping area and a non-overlapping area, the chip having an electrical connection portion, the electrical connection portion being disposed in the non-overlapping area of the chip; each of the chips of the package structure is electrically connected to the substrate through the electrical connection portion. Description of the Drawings
[0023] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood. In the drawings, several embodiments of the present application are shown in an exemplary rather than restrictive manner, with the same or corresponding reference numerals representing the same or corresponding parts, wherein:
[0024] Figure 1 A side view of a memory module provided by the present application is schematically shown;
[0025] Figure 2 A side view of another memory module provided by the present application is schematically shown;
[0026] Figure 3 A schematic structural diagram of a memory module provided by the present application is schematically shown;
[0027] Figure 4 A surface schematic diagram of a chip provided by the present application is schematically shown;
[0028] Description of the Reference Numerals in the Drawings:
[0029] Memory module 1, substrate 11, pins 111, chips 12, first chip 121, second chip 122, third chip 123, fourth chip 124, overlapping area 125, non-overlapping area 126, redistribution line 127, initial electrical connection point 128, electrical connection portion 129, insulating layer 13, first connection line 14, second connection line 15, third connection line 16. Detailed Embodiments
[0030] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application can be fully conveyed to those skilled in the art.
[0031] In the related art, an encapsulation structure (for example, a chip encapsulation structure, etc.) needs to achieve electrical connection through wires, and the wires need to be connected to the electrical connection parts of the chips. The encapsulation structures are adjacent to each other in a stacked form layer by layer. In order to enable the wires to be connected to the electrical connection parts of the chips, a certain gap is usually required between multiple chips to allow the wires to pass through.
[0032] However, due to the large number of chips, the gaps between multiple chips accumulated will cause the thickness of the encapsulation structure to be too large, and then cause the encapsulation structure to be large in volume and occupy too much space inside the electronic device.
[0033] In view of the above technical problems, as Figures 1 to 4 shown, the present application provides an encapsulation structure, including:
[0034] A substrate 11;
[0035] Multiple chips 12, stacked on the substrate 11. The orthographic projection areas of at least two adjacent chips 12 among the multiple chips 12 on the substrate 11 include an overlapping area 125 and a non-overlapping area 125. The chip 12 has an electrical connection part 129, and the electrical connection part 129 is arranged in the non-overlapping area 125 of the chip 12.
[0036] An encapsulation structure provided by an embodiment of the present application includes a substrate 11 and multiple chips 12. Multiple chips 12 are stacked on the substrate 11. The orthographic projection areas of at least two adjacent chips 12 among the multiple chips 12 on the substrate 11 may include an overlapping area 125 and a non-overlapping area 125, that is, two adjacent chips 12 do not completely overlap, and the chip 12 has an electrical connection part 129, and the electrical connection part 129 may be arranged in the non-overlapping area 125 between each chip 12 and the adjacent chip 12. The non-overlapping area 125 may be located at the edge part of the chip 12. The chip 12 can be connected to the substrate 11 through the electrical connection part 129. Since the electrical connection part 129 is located in the non-overlapping area 125 of the chip 12, and the non-overlapping area 125 is located at the edge part of the chip 12, it is thus avoided that extra space needs to be reserved for wire routing between two chips. Furthermore, when multiple chips are stacked together, the occupied space is smaller and the thickness is thinner.
[0037] Therefore, in the encapsulation structure provided by the present application, by making two adjacent chips 12 not completely overlap, so that each chip 12 has a non-overlapping area 125 located at the edge part, and arranging the electrical connection part 129 of the chip 12 in the non-overlapping area 125, the non-overlapping area 125 provides space for wire routing, avoiding the need to reserve extra space for wire routing between two chips. Furthermore, when multiple chips are stacked together, the occupied space is smaller, the thickness is thinner, and the multiple chips 12 stacked together enable the size of the substrate 11 to be made smaller, thus saving space and increasing the usable space of the battery.
[0038] In the embodiment of the present application, a plurality of chips 12 are stacked on the substrate 11 in a staggered manner in sequence. The positive projection areas of each chip 12 and the adjacent chips 12 on the substrate 11 both include an overlapping area 125 and a non-overlapping area 125.
[0039] In this embodiment, a plurality of chips 12 can be stacked on the substrate 11, and two adjacent chips 12 can be arranged in a staggered manner. Each chip 12 has a positive projection area on the substrate 11, and the positive projections of two adjacent chips 12 on the substrate 11 can have an overlapping area 125 and a non-overlapping area 125. The overlapping area 125 between two adjacent chips 12 is located in the first partial area of each chip 12 along the first direction, and the non-overlapping area 125 is the second partial area of each chip 12 along the first direction. The first partial area and the second partial area of each chip 12 are adjacent to each other, and the first partial area is at least larger than the second partial area to ensure the stability of the stacking of the plurality of chips 12. The first areas between two adjacent chips 12 overlap, and the two second partial areas of two adjacent chips 12 can be respectively located on both sides along the first direction. The electrical connection portions 129 are arranged on the non-overlapping areas 125 of the chips 12, so that the electrical connection portions 129 connecting two adjacent chips 12 and the substrate 11 are respectively located on both sides, which is more conducive to wire winding and avoids the entanglement of wire winding.
[0040] As Figures 1 to 4 shown, in the embodiment of the present application, an insulating layer 13 is arranged between the overlapping areas 125 of adjacent chips 12.
[0041] In this embodiment, there are an overlapping area and a non-overlapping area between two adjacent chips. An insulating layer is arranged between the overlapping areas of two adjacent chips, so as to achieve an insulating effect and avoid short circuit or interference caused by contact between two adjacent chips 12, ensuring signal transmission. The insulating layer may not be correspondingly arranged above the non-overlapping area, so that there is no need for the insulating layer as the space for wire routing. Furthermore, the insulating layer can be thinned compared with the related art, thus saving materials.
[0042] In a second aspect, the present application further provides a memory module 1, including a packaging structure. The packaging structure includes a substrate 11 and a plurality of chips 12. The plurality of chips 12 are stacked on the substrate 11. The positive projection areas of at least two adjacent chips 12 among the plurality of chips 12 on the substrate 11 include an overlapping area 125 and a non-overlapping area 125. The chip 12 has an electrical connection portion 129, and the electrical connection portion 129 is arranged on the non-overlapping area 125 of the chip 12;
[0043] Each chip 12 of the packaging structure is electrically connected to the substrate 11 through the electrical connection portion 129.
[0044] A memory module 1 provided by an embodiment of the present application includes a packaging structure, and the packaging structure includes a substrate 11 and multiple chips 12. Multiple chips 12 are stacked on the substrate 11. The orthographic projection areas of at least two adjacent chips 12 on the substrate 11 may include an overlapping area 125 and a non-overlapping area 125, that is, the two adjacent chips 12 do not completely overlap. Moreover, the chip 12 has an electrical connection portion 129, and the electrical connection portion 129 may be arranged in the non-overlapping area 125 between each chip 12 and the adjacent chip 12, and the non-overlapping area 125 may be located at the edge portion of the chip 12. The chip 12 is connected to the substrate 11 through the electrical connection portion 129. Since the electrical connection portion 129 is located in the non-overlapping area 125 of the chip 12 and the non-overlapping area 125 is located at the edge portion of the chip 12, it is thus avoided that extra space needs to be reserved for wiring between two chips. Furthermore, when multiple chips are stacked together, the occupied space is smaller and the thickness is thinner. Since the thickness becomes thinner, the length of the wiring is shortened, the signal loss is reduced, and thus the signal quality is improved.
[0045] Therefore, in a memory module 1 provided by the present application, by making two adjacent chips 12 not completely overlap, so that each chip 12 has a non-overlapping area 125 located at the edge portion, and arranging the electrical connection portion 129 of the chip 12 in the non-overlapping area 125, the non-overlapping area 125 provides space for wiring, avoiding the need to reserve extra space for wiring between two chips. Furthermore, when multiple chips are stacked together, the occupied space is smaller and the thickness is thinner, thus shortening the length of the wiring, reducing signal loss, and improving signal quality. And the multiple chips 12 stacked together enable the size of the substrate 11 to be made smaller, thus saving space and increasing the usable space of the battery.
[0046] Moreover, for the memory module 1 provided by the present application, when the initial shipment volume is less than 1 million pieces, there will be a 5% cost increase compared to 4 standard-packaged memories; when the shipment volume is greater than 1 million pieces, the price will be the same. Thus, the cost will not increase. In addition, the memory module 1 provided by the present application has better performance than 8 or 4 memories in the related art. At the same time, the memory is optimized, and the overclocking performance of the chip 12 is improved. At the same time, the saved motherboard area and system space can be used to increase the battery capacity, extend the battery life of the whole machine, and provide a better user experience.
[0047] Such as Figure 1 and Figure 3 shown, in the embodiment of the present application, it further includes:
[0048] Multiple first connection lines 14, one end of each first connection line 14 is connected to the substrate 11, and the other end is connected to the electrical connection portion 129 in the non-overlapping area 125 of a chip 12.
[0049] In this embodiment, the memory module 1 includes a package structure and a first connection line 14. The package structure includes a substrate 11 and multiple chips 12. The multiple chips 12 are stacked in a staggered manner on the substrate 11. Each chip 12 is connected to the substrate 11 through the first connection line 14 to achieve signal transmission. Each chip 12 has a positive projection on the substrate 11. The positive projections of two adjacent chips 12 on the chip 12 may have an overlapping area 125 and a non-overlapping area 125. The overlapping area 125 between two adjacent chips 12 may be located in the first partial area of each chip 12 along the first direction. The non-overlapping area 125 may be the second partial area of each chip 12 along the first direction. The first partial area and the second partial area of each chip 12 may be adjacently arranged, and the first partial area is at least larger than the second partial area to ensure the stability of the stacking between the multiple chips 12. The first areas between two adjacent chips 12 are overlapped, and the two second partial areas of two adjacent chips 12 are respectively located on both sides along the first direction. An electrical connection portion 129 is provided on the non-overlapping area 125 of the chip 12. One end of the first connection line 14 is connected to the substrate 11, and the other end of the first connection line 14 is connected to the electrical connection portion 129 of the non-overlapping area 125 of the chip 12. The electrical connection portions 129 of two adjacent chips 12 connected to the substrate 11 are respectively located on both sides. Thus, the first connection lines 14 connecting two adjacent chips 12 are respectively located on both sides, which is more conducive to wire winding and avoids the entanglement of wire winding. Moreover, the two chips 12 arranged in a staggered manner can further reduce the length of the first connection line 14, thereby reducing signal loss and improving signal quality.
[0050] As Figure 4 shown, in the embodiment of the present application, the chip 12 further has a redistribution line 127 and an initial electrical connection point 128 located in the middle area. One end of the redistribution line 127 is connected to the initial electrical connection point 128, and the other end extends to the non-overlapping area 125 to form an electrical connection portion 129.
[0051] In this embodiment, the memory module 1 is a DDR5 memory module 1. The initial electrical connection point 128 of the DDR5 memory module 1 is located in the central area of the chip 12. The memory module 1 of the present application further includes a redistribution line 127. The first end of the redistribution line 127 is connected to the initial electrical connection point 128 located in the central area of the chip 12, and the second end extends to the non-overlapping area 125 of the chip 12. At this time, the second end of the redistribution line 127 becomes the electrical connection portion 129 of the chip 12. By changing the position of the electrical connection point through the redistribution line 127, it is convenient to make electrical connection with the substrate 11 to achieve signal transmission, avoid problems such as too long wire winding, and reduce signal loss.
[0052] In the embodiment of the present application, two adjacent chips 12 among the multiple chips 12 are stacked in a staggered manner; or
[0053] The plurality of chips 12 include a first chip 121, a second chip 122, a third chip 123, and a fourth chip 124 that are sequentially stacked in the thickness direction on a substrate 11. The first chip 121 has a non-overlapping region 125 on a first side in a first direction relative to the second chip 122. The third chip 123 has a non-overlapping region 125 on a second side in the first direction relative to the fourth chip 124. The first direction may be a direction perpendicular to the thickness of the chip.
[0054] In an embodiment of the present application, the memory module 1 includes a substrate 11 and a plurality of chips 12. Four groups of 4-layer stacked chips 12 are provided on the upper surface of the substrate 11, that is, a total of 16 chips 12 are provided on the substrate 11. Every 4 chips 12 are stacked in an interleaved manner. There may be an overlapping region 125 and a non-overlapping region 125 between each chip 12 and an adjacent chip 12. The non-overlapping regions 125 of two adjacent chips 12 may be respectively on both sides in the first direction. An electrical connection portion 129 may be provided on the non-overlapping region 125 of each chip 12. One end of the first connection line 14 may be connected to the electrical connection portion 129 of each chip 12, and the other end may pass through a via hole in the substrate 11 and be connected to a connection pin 111 on the lower surface of the substrate 11. Thus, in the plurality of chips 12 stacked in an interleaved manner, each chip 12 has a non-overlapping region 125 with an electrical connection portion 129 at the edge. The non-overlapping region 125 provides extra space for routing, so that the space occupied by the plurality of chips when stacked together is smaller and the thickness is thinner. Since the thickness is thinned, it is convenient to connect the first connection line 14, reduce the length of the first connection line 14, reduce signal loss, and improve signal quality.
[0055] In another embodiment of the present application, the memory module 1 includes a substrate 11 and a plurality of chips 12. Four groups of chips 12 arranged in a 4-layer stack are provided on the upper surface of the substrate 11, that is, a total of 16 chips 12 are provided on the substrate 11. Every 4 chips 12 include a first chip 121, a second chip 122, a third chip 123, and a fourth chip 124 that can be sequentially stacked on the substrate 11 in the thickness direction. That is, on the substrate 11, the first chip 121, the second chip 122, the third chip 123, and the fourth chip 124 of each chip 12 can be sequentially stacked. The first chip 121 and the second chip 122 can be staggered. There are an overlapping area 125 and a non-overlapping area 125 between the first chip 121 and the second chip 122. The non-overlapping area 125 of the first chip 121 relative to the second chip 122 can be located on the first side of the chip 12 along the first direction. The electrical connection portions 129 of the first chip 121 and the second chip 122 are located on the first side of the chip 12 along the first direction. Thus, the first chip 121 and the second chip 122 can be connected to the substrate 11 through a second connection line 15 and a third connection line 16 on the first side along the first direction. The third chip 123 and the fourth chip 124 can be staggered. There can be an overlapping area 125 and a non-overlapping area 125 between the third chip 123 and the fourth chip 124. The non-overlapping area 125 of the third chip 123 relative to the fourth chip 124 is located on the second side of the chip 12 along the first direction. The electrical connection portions 129 of the third chip 123 and the fourth chip 124 are located on the second side of the chip 12 along the first direction. The third chip 123 and the fourth chip 124 are connected to the substrate 11 through the second connection line 15 and the third connection line 16 on the second side along the first direction. Thus, every two adjacent chips 12 are connected to the substrate 11 through the second connection line 15 and the third connection line 16 on one side in the first direction of the chip 12, thereby avoiding the entanglement of the connection lines, saving the space for wire winding, and through the setting of the electrical connection portions 129 on the non-overlapping area 125 that is located at the edge and extends relatively into the adjacent chips 12, extra space is provided for wire routing. Furthermore, when multiple chips are stacked together, the occupied space is smaller and the thickness is thinner. Since the thickness becomes thinner, the length of the connection lines is reduced. In addition, the stepped connection of the second connection line 15 and the third connection line 16 further reduces the length of the connection lines, thereby reducing signal loss and improving signal quality.
[0056] In this embodiment, the substrate 11 has an upper surface and a lower surface. A plurality of chips 12 are stacked on the upper surface, and a plurality of pins 111 connected to the chips 12 are provided on the lower surface. The plurality of pins 111 may include data signal pins, command address signal pins, control signal pins, clock signal pins, power signal pins, and ground signal pins. The data signal pins are arranged on the periphery of the plurality of pins 111, surrounding the command address signal pins, control signal pins, clock signal pins, power signal pins, and ground signal pins 111, thereby facilitating the connection between the data pins 111 and the electrical connection portions 129 of the chips 12. The data signal pins may have 16-bit data.
[0057] In this embodiment, when the memory module 1 is LP5X, the specific specifications of the memory module 1 are: - Solder Ball Count: 2200 balls, Solder Ball Pitch: 0.4 mm x / y, Solder Ball Height: 0.22 mm, Package Size: 18.0 x 30.0 mm, and Package Height: max 1.2 mm. At this time, the number of pins 111 on the lower surface of the substrate 11 is 2200. The data signal pins need to be connected to the electrical connection portions 129 located in the non-overlapping region 125 of the chips 12. There are 16 data signal pins.
[0058] In this embodiment, when the memory module 1 is DDR5, the specific specifications of the memory module 1 are: Solder Ball Count: 396 balls, Solder Ball Pitch: 0.4 mm x / y, Solder Ball Height: 0.22 mm, Package Size: 15.0 x 18.0 mm, and Package Height: max 1.2 mm. At this time, the number of pins 111 on the lower surface of the substrate 11 is 396. The data signal pins need to be connected to the electrical connection portions 129 located in the non-overlapping region 125 of the chips 12, and there are 2 data signal pins. For the other electrical connection points on the chips 12, no re-routing 127 is used. The electrical connection points located in the central region are led to the edge region, and the other pins 111 are directly connected to the corresponding connection points on the chips 12, thereby shortening the length of the connection lines, reducing signal loss, and improving signal quality.
[0059] As Figure 2 shown, in the embodiment of the present application, the plurality of chips 12 at least include a first chip 121 and a second chip 122 arranged adjacent to each other;
[0060] The memory module 1 further includes a plurality of second connection lines 15 and a plurality of third connection lines 16. The first end of the second connection line 15 is connected to the substrate 11, the second end of the second connection line 15 is connected to the electrical connection portion 129 of the first chip 121, the first end of the third connection line 16 is connected to the second end of the second connection line 15, and the second end of the third connection line 16 is connected to the electrical connection portion 129 of the second chip 122.
[0061] In this embodiment, the memory module 1 includes a packaging structure, second connection lines 15 and third connection lines 16. The packaging structure includes a substrate 11 and a plurality of chips 12. The plurality of chips 12 are staggeredly stacked on the substrate 11. The plurality of chips 12 at least include a first chip 121 and a second chip 122. The first chip 121 and the second chip 122 are arranged adjacent to each other. The first end of the second connection line 15 is connected to the substrate 11, the second end of the second connection line 15 is connected to the electrical connection portion 129 provided on the non-overlapping area 125 of the first chip 121, the first end of the third connection line 16 is connected to the second end of the second connection line 15, and the second end of the third connection line 16 is connected to the electrical connection portion 129 provided on the non-overlapping area 125 of the second chip 122. Thus, through the stepped connection of the second connection line 15 and the third connection line 16, the adjacent first chip 121 and second chip 122 are connected to the substrate 11 in a stepped connection manner, thereby shortening the length of the wire winding, reducing the signal loss, improving the signal quality, and at the same time reducing the space occupied by the wire winding.
[0062] In the embodiment of the present application, when at least one of the first connection line 14, the second connection line 15 or the third connection line 16 is connected to the electrical connection portion 129, at least one of them has a length in the thickness direction above the corresponding electrical connection portion 129 that is at least greater than the thickness of the insulating layer 13 of the packaging structure.
[0063] In this embodiment, there is a packaging structure of the memory module 1. The packaging structure includes a substrate 11 and multiple chips 12. Adjacent chips 12 are arranged staggeredly, and there may be an overlapping area 125 and a non - overlapping area 125. The non - overlapping area 125 of each chip 12 is located at the edge part, and the non - overlapping area 125 of each chip 12 has an electrical connection part 129. Thus, the edge chip 12 is connected to the substrate 11 through the electrical connection part 129, reducing the lengths of the first connection line 14, the second connection line 15, or the third connection line 16 used to connect the substrate 11 and the electrical connection part 129. When at least one of the first connection line 14, the second connection line 15, or the third connection line 16 is connected to the electrical connection part 129, it has a certain length in the thickness direction above the corresponding electrical connection part 129, and this length is at least greater than the thickness of the corresponding insulating layer 13. Thus, compared with multiple directly stacked chips 12, for the multiple staggeredly arranged chips 12 in the present application, since the electrical connection part 129 can be arranged in the non - overlapping area 125 at the edge of the chip 12, it does not need to extend into the insulating layer 13. Therefore, compared with the prior art, the thickness of the insulating layer 13 can be reduced. After the thickness of the insulating layer 13 is reduced, the upper - layer chip 12 is closer to the substrate 11, which can further reduce the length of the connection line. The reduction of the connection line length can reduce signal loss and improve signal quality. Moreover, the reduction of the distance between the substrate 11 and the chip 12 can also increase the range of the memory frequency, facilitating the full performance of the memory. At the same time, the occupied space is reduced, facilitating the addition of more battery usage space.
[0064] In a third aspect, the present application also provides an electronic device, including a memory module 1. The memory module 1 includes a packaging structure. The packaging structure includes a substrate 11 and multiple chips 12. The multiple chips 12 are stacked on the substrate 11. The positive - projection areas of at least two adjacent chips 12 among the multiple chips 12 on the substrate 11 include an overlapping area 125 and a non - overlapping area 125. The chip 12 has an electrical connection part 129, and the electrical connection part 129 is arranged in the non - overlapping area 125 of the chip 12;
[0065] Each chip 12 of the packaging structure is electrically connected to the substrate 11 through the electrical connection part 129.
[0066] An electronic device provided by an embodiment of the present application includes a memory module 1. The memory module 1 includes a packaging structure, which includes a substrate 11 and multiple chips 12. Multiple chips 12 are stacked on the substrate 11. The orthographic projection areas of at least two adjacent chips 12 among the multiple chips 12 on the substrate 11 may include an overlapping area 125 and a non-overlapping area 125, that is, the two adjacent chips 12 do not completely overlap. Moreover, the chip 12 has an electrical connection portion 129, and the electrical connection portion 129 may be arranged in the non-overlapping area 125 between each chip 12 and the adjacent chip 12. The non-overlapping area 125 may be located at the edge portion of the chip 12. The chip 12 is connected to the substrate 11 through the electrical connection portion 129. Since the electrical connection portion 129 is located in the non-overlapping area 125 of the chip 12, and the non-overlapping area 125 is located at the edge portion of the chip 12, it is thus avoided that extra space needs to be reserved for wiring between two chips. Furthermore, when multiple chips are stacked together, the occupied space is smaller and the thickness is thinner. Since the thickness becomes thinner, the length of the wiring is shortened, the signal loss is reduced, and thus the signal quality is improved.
[0067] Therefore, for an electronic device provided by the present application, by making the two adjacent chips 12 not completely overlap, so that each chip 12 has a non-overlapping area 125 located at the edge portion, and arranging the electrical connection portion 129 of the chip 12 in the non-overlapping area 125, the non-overlapping area 125 provides space for wiring, avoiding the need to reserve extra space for wiring between two chips. Furthermore, when multiple chips are stacked together, the occupied space is smaller and the thickness is thinner, thus shortening the length of the wiring, reducing the signal loss, and improving the signal quality. And the multiple chips 12 stacked together enable the size of the substrate 11 to be made smaller, thus saving space and increasing the usable space of the battery.
[0068] As described above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A memory module, characterized in that: include: A packaging structure, the packaging structure comprising a substrate and a plurality of chips, the plurality of chips are stacked and arranged on the substrate, the orthographic projection areas of at least two adjacent chips among the plurality of chips onto the substrate include overlapping areas and non-overlapping areas, the chip has an electrical connection portion, and the electrical connection portion is arranged in the non-overlapping area of the chip; Each chip of the package structure is electrically connected to the substrate through the electrical connection portion; The chip also has a redistribution wiring and an initial electrical connection point located in the middle area. One end of the redistribution wiring is connected to the initial electrical connection point, and the other end extends to the non-overlapping area to form the electrical connection portion.
2. The memory module according to claim 1, characterized in that: The plurality of chips are stacked and arranged on the substrate in sequence; The memory module further includes a plurality of first connection lines, one end of each of the first connection lines is connected to the substrate, and the other end is connected to an electrical connection portion of a non-overlapping region of the chip.
3. The memory module according to claim 2, wherein: Two adjacent chips among the plurality of chips are stacked alternately; or The multiple chips include a first chip, a second chip, a third chip and a fourth chip stacked in sequence on the substrate along the thickness direction, the first chip has a non-overlapping area on a first side along the first direction relative to the second chip, the third chip has a non-overlapping area on a second side along the first direction relative to the fourth chip, and the first direction is perpendicular to the thickness direction of the chip.
4. The memory module according to claim 2, wherein: The plurality of chips at least include a first chip and a second chip disposed adjacent to each other; The memory module also includes multiple second connecting wires and multiple third connecting wires, the first end of the second connecting wire is connected to the substrate, the second end of the second connecting wire is connected to the electrical connection part of the first chip, the first end of the third connecting wire is connected to the second end of the second connecting wire, and the second end of the third connecting wire is connected to the electrical connection part of the second chip.
5. The memory module according to claim 4, characterized in that: When at least one of the first connecting wire, the second connecting wire or the third connecting wire is connected to the electrical connecting portion, the length of the at least one along the thickness direction above the corresponding electrical connecting portion is at least greater than the thickness of the insulating layer of the corresponding packaging structure.
6. The memory module according to claim 1, wherein: An insulating layer is arranged between overlapping regions of adjacent chips.
7. An electronic device, characterized in that: include: A memory module, wherein the memory module comprises a packaging structure, wherein the packaging structure comprises a substrate and a plurality of chips, wherein the plurality of chips are stacked and arranged on the substrate, wherein the orthographic projection areas of at least two adjacent chips among the plurality of chips onto the substrate comprise overlapping areas and non-overlapping areas, wherein the chip has an electrical connection portion, wherein the electrical connection portion is arranged in the non-overlapping area of the chip, and each chip of the packaging structure is electrically connected to the substrate via the electrical connection portion; The chip also has a redistribution wiring and an initial electrical connection point located in the middle area. One end of the redistribution wiring is connected to the initial electrical connection point, and the other end extends to the non-overlapping area to form the electrical connection portion.