Overcurrent protection circuit, photovoltaic inverter and photovoltaic system

Abstract

The utility model discloses an over-current protection circuit, a photovoltaic inverter and a photovoltaic system, and the over-current protection circuit comprises a sampling module which receives an input current and generates an in-phase sampling signal and an inverted sampling signal based on the input current; the selection module is connected with the sampling module and is used for generating a peak value sampling signal according to the in-phase sampling signal and the anti-phase sampling signal; the holding module is connected with the selection module and is used for holding the peak value sampling signal and generating a peak value holding signal; and the comparison module is connected with the holding module and is used for comparing the peak holding signal with the reference signal and generating an overcurrent protection signal. According to the utility model, the over-current protection signal is kept within a certain time after the input current is recovered to be normal through the keeping module, so that the problem that the protection delay time of a common circuit is not enough is solved; the reverse flow of charges in the holding capacitor is prevented through the current anti-backflow device, the voltage drop generated by the current anti-backflow device is counteracted through the voltage drop compensation device, and the accuracy of an actual protection value is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuits, and specifically relates to an overcurrent protection circuit, a photovoltaic inverter and a photovoltaic system. Background Art

[0002] The string-type three-phase photovoltaic inverter converts the direct current output by the solar photovoltaic cell panel assembly into three-phase alternating current consistent with the grid voltage and frequency. The inverter uses sensors to convert the three-phase voltage and current signals into corresponding and recognizable signals and inputs them to the digital signal processing chip (DSP). The digital signal processing chip controls the input and output current, voltage, power, etc. through these analog signals. However, due to the fluctuations in the general load-side power grid, there are situations such as high-voltage ride-through, low-voltage ride-through, short-circuit power-off, open-circuit power-off, etc., and it is necessary to effectively and quickly protect the inverter output current to prevent damage to the inverter itself and the load.

[0003] The currently used protection circuits have the following two problems:

[0004] 1. A large number of diodes are generally used inside the circuit. The diode itself has a voltage drop, and the voltage drop is inconsistent at different currents and temperatures. If precise compensation is not carried out, it will cause a large deviation between the actual protection value and the theoretical calculated value;

[0005] 2. The inverter trigger overcurrent protection generally has two levels of protection. The first level is fast protection, generally implemented by hardware, and the second level is system protection, generally judged by software. The connection between the first-level protection and the second-level protection is very important. The second-level protection must be entered before the end of the first-level protection. In actual operation, the current is sudden. When the current suddenly increases, the first-level protection of the inverter is triggered and blocked. As Figure 1 shown, the current then drops rapidly, resulting in a situation where the first-level protection has recovered but the second-level protection has not been triggered. Eventually, the current suddenly rises for the second time, triggering the first-level protection again. Eventually, the current continues to increase, causing the inverter protection to be untimely or directly damaged.

[0006] Therefore, in view of the above technical problems, it is necessary to provide an overcurrent protection circuit, a photovoltaic inverter and a photovoltaic system. Summary of the Utility Model

[0007] The purpose of the utility model is to provide an overcurrent protection circuit, a photovoltaic inverter and a photovoltaic system, which can solve the problems of large deviation between the actual protection value and the theoretical calculated value and insufficient protection time.

[0008] In order to achieve the above purpose, the technical solutions provided by an embodiment of the utility model are as follows:

[0009] An overcurrent protection circuit, characterized in that the overcurrent protection circuit includes a sampling module, a selection module, a holding module and a comparison module; wherein,

[0010] The sampling module receives an input current and generates a non-inverting sampling signal and an inverting sampling signal based on the input current;

[0011] The selection module is connected to the sampling module and is used to generate a peak sampling signal according to the non-inverting sampling signal and the inverting sampling signal;

[0012] The holding module is connected to the selection module and is used to hold the peak sampling signal and generate a peak hold signal;

[0013] The comparison module is connected to the holding module and is used to compare the peak hold signal with a reference signal and generate an overcurrent protection signal.

[0014] In one or more embodiments of the present invention, the holding module includes a first operational amplifier, a holding capacitor, a current anti-backflow device, a second operational amplifier and a voltage drop compensation device; wherein,

[0015] The non-inverting input terminal of the first operational amplifier is directly or indirectly connected to the selection module to receive the peak sampling signal, the inverting input terminal of the first operational amplifier is connected to the first end of the voltage drop compensation device, and the output terminal of the first operational amplifier is connected to the second end of the voltage drop compensation device;

[0016] The first end of the current anti-backflow device is directly or indirectly connected to the output terminal of the first operational amplifier, the second end of the current anti-backflow device is connected to the first end of the holding capacitor, and the second end of the holding capacitor is connected to the reference potential;

[0017] The inverting input terminal of the second operational amplifier is connected to the inverting input terminal of the second operational amplifier, the non-inverting input terminal of the second operational amplifier is connected to the second end of the current anti-backflow device, and the output terminal of the second operational amplifier is directly or indirectly connected to the inverting input terminal of the connected first operational amplifier.

[0018] In one or more embodiments of the present invention, the voltage drop compensation device includes a first diode, the first end of the first diode is connected to the inverting input terminal of the first operational amplifier, and the second end of the first diode is connected to the output terminal of the first operational amplifier; and / or,

[0019] The current anti-backflow device includes a second diode, the first end of the second diode is directly or indirectly connected to the output terminal of the first operational amplifier, and the second end of the second diode is connected to the first end of the holding capacitor and the non-inverting input terminal of the second operational amplifier.

[0020] In one or more embodiments of the present utility model, the holding module further includes a first resistor, a first capacitor, a second resistor, and a third resistor; wherein,

[0021] A first end of the first resistor is connected to the selection module, and a second end of the first resistor is connected to a non-inverting input terminal of a first operational amplifier;

[0022] A first end of the first capacitor is connected to an inverting input terminal of the first operational amplifier, and a second end of the first capacitor is connected to an output terminal of the first operational amplifier;

[0023] A first end of the second resistor is connected to the inverting input terminal of the first operational amplifier, and a second end of the second resistor is connected to an inverting input terminal of a second operational amplifier;

[0024] A first end of the third resistor is connected to the output terminal of the first operational amplifier, and a second end of the third resistor is connected to a first end of a current anti-backflow device.

[0025] In one or more embodiments of the present utility model, the sampling module includes a current sensor, a differential operational amplifier unit, a non-inverting operational amplifier unit, and an inverting operational amplifier unit; wherein,

[0026] The current sensor is configured to collect an input current;

[0027] The differential operational amplifier unit is connected to the current sensor and is configured to perform gain amplification on the input current and generate a first signal;

[0028] The non-inverting operational amplifier unit is connected to the differential operational amplifier unit and is configured to generate a non-inverting sampling signal based on the first signal;

[0029] The inverting operational amplifier unit is connected to the differential operational amplifier unit and is configured to invert the first signal to generate an inverting sampling signal, and the phase difference between the non-inverting sampling signal and the inverting sampling signal is 180°.

[0030] In one or more embodiments of the present utility model, the differential operational amplifier unit includes a twelfth resistor, a second capacitor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third capacitor, and a seventh operational amplifier; wherein,

[0031] A first end of the twelfth resistor is connected to a reference potential, a second end of the twelfth resistor is connected to a non-inverting input terminal of the seventh operational amplifier, a first end of the second capacitor is connected to the reference potential, and a second end of the second capacitor is connected to the non-inverting input terminal of the seventh operational amplifier;

[0032] A first end of the thirteenth resistor is connected to the current sensor, a second end of the thirteenth resistor is connected to the non-inverting input terminal of the seventh operational amplifier, a first end of the fourteenth resistor is connected to the current sensor, and a second end of the fourteenth resistor is connected to an inverting input terminal of the seventh operational amplifier;

[0033] The first end of the fifteenth resistor is connected to the inverting input terminal of the seventh operational amplifier, the second end of the fifteenth resistor is connected to the output terminal of the seventh operational amplifier, the first end of the third capacitor is connected to the inverting input terminal of the seventh operational amplifier, and the second end of the third capacitor is connected to the output terminal of the seventh operational amplifier and generates a first signal through the output terminal of the seventh operational amplifier.

[0034] In one or more embodiments of the present invention, the non-inverting operational amplifier unit includes a fourth resistor and a third operational amplifier; wherein,

[0035] The first end of the fourth resistor is connected to the differential operational amplifier unit to receive the first signal, and the second end of the fourth resistor is connected to the non-inverting input terminal of the third operational amplifier;

[0036] The inverting input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier and generates a non-inverting sampling signal.

[0037] In one or more embodiments of the present invention, the inverting operational amplifier unit includes a fifth resistor, a sixth resistor, and a fourth operational amplifier; wherein,

[0038] The first end of the fifth resistor is connected to the differential operational amplifier unit to receive the first signal, and the second end of the fifth resistor is connected to the inverting input terminal of the fourth operational amplifier,

[0039] The first end of the sixth resistor is connected to the inverting input terminal of the fourth operational amplifier, and the second end of the sixth resistor is connected to the output terminal of the fourth operational amplifier;

[0040] The non-inverting input terminal of the fourth operational amplifier is connected to the reference potential, and the output terminal of the fourth operational amplifier generates an inverting sampling signal.

[0041] In one or more embodiments of the present invention, the selection module includes a fifth operational amplifier, a third diode, a sixth operational amplifier, and a fourth diode; wherein,

[0042] The non-inverting input terminal of the fifth operational amplifier is connected to the sampling module to receive the non-inverting sampling signal, the inverting input terminal of the fifth operational amplifier is connected to the second end of the third diode, and the output terminal of the fifth operational amplifier is connected to the first end of the third diode;

[0043] The non-inverting input terminal of the sixth operational amplifier is connected to the sampling module to receive the inverting sampling signal, the inverting input terminal of the sixth operational amplifier is connected to the second end of the fourth diode, and the output terminal of the sixth operational amplifier is connected to the first end of the fourth diode.

[0044] In one or more embodiments of the present invention, the comparison module includes a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a comparator; wherein,

[0045] The first end of the seventh resistor is connected to the holding module, the second end of the seventh resistor is connected to the non-inverting input terminal of the comparator and the first end of the eighth resistor, the second end of the eighth resistor is connected to the output terminal of the comparator, the first end of the ninth resistor is used to receive a reference signal, and the second end of the ninth resistor is connected to the inverting input terminal of the comparator;

[0046] The first end of the tenth resistor is connected to the input voltage, the second end of the tenth resistor is connected to the output terminal of the comparator and generates an overcurrent protection signal, the first end of the eleventh resistor is connected to the output terminal of the comparator, and the second end of the eleventh resistor is connected to the reference potential.

[0047] In one or more embodiments of the present invention, the overcurrent protection circuit includes three sampling modules to respectively receive one of the three-phase input currents, and a selection module is connected between each sampling module and the holding module.

[0048] The technical solution provided by another embodiment of the present invention is as follows:

[0049] A photovoltaic inverter, the photovoltaic inverter includes the overcurrent protection circuit described above.

[0050] The technical solution provided by another embodiment of the present invention is as follows:

[0051] A photovoltaic system, the photovoltaic system includes the photovoltaic inverter described above.

[0052] Compared with the prior art, the overcurrent protection circuit, photovoltaic inverter and photovoltaic system of the present invention control the overcurrent protection signal to remain for a certain period of time even after the input current returns to normal through the holding module, solve the problem that the protection delay time of general circuits is insufficient, and avoid the first-stage protection from recovering when the subsequent protection is not triggered;

[0053] Prevent the charge in the holding capacitor from flowing backward through the current anti-backflow device, and at the same time offset the voltage drop generated by the current anti-backflow device through the voltage drop compensation device to improve the accuracy of the actual protection value;

[0054] Rectify the sine wave into a sine half-wave through the inverting op-amp unit, so as to realize correct overcurrent detection even when overcurrent or short circuit occurs in the negative half-axis of the sine wave. Description of the Drawings

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0056] Figure 1 It is the signal simulation diagram of the overcurrent protection circuit in the prior art;

[0057] Figure 2 It is the circuit schematic diagram of the overcurrent protection circuit in Embodiment 1 of the present invention;

[0058] Figure 3 It is the circuit schematic diagram of the overcurrent protection circuit in Embodiment 2 of the present invention;

[0059] Figure 4 It is the peak sampling signal simulation diagram of the overcurrent protection circuit in Embodiment 2 of the present invention;

[0060] Figure 5 It is the signal simulation diagram of the overcurrent protection circuit in Embodiment 2 of the present invention. Detailed implementation manners

[0061] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0062] "Coupled", "connected", or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0063] Embodiment 1:

[0064] Such as Figure 2As shown in the figure, an overcurrent protection circuit in an embodiment of the present utility model includes a sampling module 10, a selection module 20, a holding module 30, and a comparison module 40.

[0065] The sampling module 10 receives an input current and generates a in-phase sampling signal and an anti-phase sampling signal based on the input current. Further, the sampling module 10 includes a current sensor A, a differential operational amplifier unit 11, an in-phase operational amplifier unit 12, and an anti-phase operational amplifier unit 13.

[0066] The current sensor A is used to collect the phase A input current. The differential operational amplifier unit 11 is connected to the current sensor A and is used to amplify the phase A input current and generate a first signal. The in-phase operational amplifier unit 12 is connected to the differential operational amplifier unit 11 and is used to generate an in-phase sampling signal based on the first signal. The anti-phase operational amplifier unit 13 is connected to the differential operational amplifier unit 11 and is used to invert the first signal to generate an anti-phase sampling signal, where the phase difference between the in-phase sampling signal and the anti-phase sampling signal is 180°.

[0067] The selection module 20 is connected to the sampling module 10 and is used to generate a peak sampling signal according to the in-phase sampling signal and the anti-phase sampling signal. Further, the selection module 20 includes a fifth operational amplifier Amp5, a third diode D3, a sixth operational amplifier Amp6, and a fourth diode D4. The selection module 20 forms a peak sampling signal by taking the maximum value of the in-phase sampling signal and the anti-phase sampling signal as the output of the selection module 20 based on the reverse cut-off capabilities of the third diode D3 and the fourth diode D4.

[0068] The holding module 30 is connected to the selection module 20 and is used to hold the peak sampling signal and generate a peak hold signal. Further, the holding module 30 includes a first operational amplifier Amp1, a holding capacitor Cs, a current anti-backflow device, a second operational amplifier Amp2, and a voltage drop compensation device.

[0069] The comparison module 40 is connected to the holding module 30 and is used to compare the peak hold signal with a reference signal Vcomp and generate an overcurrent protection signal Sp.

[0070] Preferably, the overcurrent protection circuit in this embodiment includes three sampling modules 10 to respectively receive one of the three-phase input currents, and a selection module 20 is connected between each sampling module 10 and the holding module 30.

[0071] Embodiment 2:

[0072] As Figure 3 shown, an overcurrent protection circuit in this embodiment includes a sampling module 10, a selection module 20, a holding module 30, and a comparison module 40.

[0073] The sampling module 10 receives an input current and generates an in-phase sampling signal and an anti-phase sampling signal based on the input current. The selection module 20 is connected to the sampling module 10 and is configured to generate a peak sampling signal according to the in-phase sampling signal and the anti-phase sampling signal. The holding module 30 is connected to the selection module 20 and is configured to hold the peak sampling signal and generate a peak hold signal. The comparison module 40 is connected to the holding module 30 and is configured to compare the peak hold signal with a reference signal Vcomp and generate an overcurrent protection signal Sp.

[0074] The sampling module 10 in this embodiment includes a current sensor V1, a differential operational amplifier unit 11, an in-phase operational amplifier unit 12, and an anti-phase operational amplifier unit 13.

[0075] The current sensor V1 is configured to collect the input current. Further, the current sensor V1 is an alternating current sensor.

[0076] The differential operational amplifier unit 11 is connected to the current sensor V1 to amplify the input current and generate a first signal.

[0077] The in-phase operational amplifier unit 12 is configured to generate an in-phase sampling signal based on the first signal. The anti-phase operational amplifier unit 13 is configured to invert the first signal to generate an anti-phase sampling signal, and the phase difference between the in-phase sampling signal and the anti-phase sampling signal is 180°.

[0078] As Figure 3 shown, the differential operational amplifier unit 11 in this embodiment includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a second capacitor C2, a fifteenth resistor R15, a third capacitor C3, and a seventh operational amplifier Amp7.

[0079] Specifically, the first end of the twelfth resistor R12 is connected to a reference potential, the second end of the twelfth resistor R12 is connected to the non-inverting input terminal of the seventh operational amplifier Amp7, the first end of the second capacitor C2 is connected to the reference potential, and the second end of the second capacitor C2 is connected to the non-inverting input terminal of the seventh operational amplifier Amp7. The reference potential in this embodiment is the ground potential.

[0080] The first end of the thirteenth resistor R13 is connected to the current sensor V1, the second end of the thirteenth resistor R13 is connected to the non-inverting input terminal of the seventh operational amplifier Amp7, the first end of the fourteenth resistor R14 is connected to the current sensor V1, and the second end of the fourteenth resistor R14 is connected to the inverting input terminal of the seventh operational amplifier Amp7.

[0081] The first terminal of the fifteenth resistor R15 is connected to the inverting input terminal of the seventh operational amplifier Amp7, the second terminal of the fifteenth resistor R15 is connected to the output terminal of the seventh operational amplifier Amp7, the first terminal of the third capacitor C3 is connected to the inverting input terminal of the seventh operational amplifier Amp7, and the second terminal of the third capacitor C3 is connected to the output terminal of the seventh operational amplifier Amp7 and generates a first signal through the output terminal of the seventh operational amplifier Amp7.

[0082] As Figure 3 shown, the non-inverting operational amplifier unit 12 in this embodiment includes a fourth resistor R4 and a third operational amplifier Amp3.

[0083] The first terminal of the fourth resistor R4 is connected to the differential operational amplifier unit 11 to receive the first signal, the second terminal of the fourth resistor R4 is connected to the non-inverting input terminal of the third operational amplifier Amp3, and the inverting input terminal of the third operational amplifier Amp3 is connected to the output terminal of the third operational amplifier Amp3 and generates a non-inverting sampling signal through the output terminal of the third operational amplifier Amp3.

[0084] As Figure 3 shown, the inverting operational amplifier unit 13 in this embodiment includes a fifth resistor R5, a sixth resistor R6, and a fourth operational amplifier Amp4.

[0085] The first terminal of the fifth resistor R5 is connected to the differential operational amplifier unit 11 to receive the first signal, the second terminal of the fifth resistor R5 is connected to the inverting input terminal of the fourth operational amplifier Amp4. The first terminal of the sixth resistor R6 is connected to the inverting input terminal of the fourth operational amplifier Amp4, and the second terminal of the sixth resistor R6 is connected to the output terminal of the fourth operational amplifier Amp4. The non-inverting input terminal of the fourth operational amplifier Amp4 is connected to the reference potential, and the output terminal of the fourth operational amplifier Amp4 generates an inverting sampling signal.

[0086] It can be understood that the non-inverting operational amplifier unit 12 can enhance the first signal. Since the fundamental wave of the three-phase current is a sine wave, overcurrent or short circuit may occur in the negative half-axis of the sine wave. The waveform of the first signal is inverted by the inverting operational amplifier unit 13 so that the subsequent comparison module 40 can compare the sine wave valley value.

[0087] As Figure 3 shown, the selection module 20 in this embodiment includes a fifth operational amplifier Amp5, a third diode D3, a sixth operational amplifier Amp6, and a fourth diode D4.

[0088] The non-inverting input terminal of the fifth operational amplifier Amp5 is connected to the sampling module 10 to receive the non-inverting sampling signal, the inverting input terminal of the fifth operational amplifier Amp5 is connected to the second terminal of the third diode D3, and the output terminal of the fifth operational amplifier Amp5 is connected to the first terminal of the third diode D3.

[0089] The non-inverting input terminal of the sixth operational amplifier Amp6 is connected to the sampling module 10 to receive the inverting sampling signal. The inverting input terminal of the sixth operational amplifier Amp6 is connected to the second terminal of the fourth diode D4, and the output terminal of the sixth operational amplifier Amp6 is connected to the first terminal of the fourth diode D4.

[0090] As Figure 4 shown, it can be understood that the fifth operational amplifier Amp5 and the third diode D3 convert the in-phase sampling signal from a sine signal to a sine half-wave signal, and the sixth operational amplifier Amp6 and the fourth diode D4 convert the inverting sampling signal from a sine signal to a sine half-wave signal. And based on the reverse cut-off ability of the third diode D3 and the fourth diode D4, the maximum value in the in-phase sampling signal and the inverting sampling signal is used as the output of the selection module 20 to form a peak sampling signal.

[0091] As Figure 3 shown, the holding module 30 in this embodiment includes a first operational amplifier Amp1, a holding capacitor Cs, a current anti-backflow device, a second operational amplifier Amp2, and a voltage drop compensation device.

[0092] The non-inverting input terminal of the first operational amplifier Amp1 is directly or indirectly connected to the selection module 20 to receive the peak sampling signal. The inverting input terminal of the first operational amplifier Amp1 is connected to the first terminal of the voltage drop compensation device, and the output terminal of the first operational amplifier Amp1 is connected to the second terminal of the voltage drop compensation device.

[0093] The first terminal of the current anti-backflow device is directly or indirectly connected to the output terminal of the first operational amplifier Amp1. The second terminal of the current anti-backflow device is connected to the first terminal of the holding capacitor Cs, and the second terminal of the holding capacitor Cs is connected to the reference potential.

[0094] The inverting input terminal of the second operational amplifier Amp2 is connected to the inverting input terminal of the second operational amplifier Amp2. The non-inverting input terminal of the second operational amplifier Amp2 is connected to the second terminal of the current anti-backflow device, and the output terminal of the second operational amplifier Amp2 is directly or indirectly connected to the inverting input terminal of the first operational amplifier Amp1.

[0095] Preferably, the voltage drop compensation device includes a first diode D1, and the current anti-backflow device includes a second diode D2.

[0096] Wherein, the first terminal and the second terminal of the first diode D1 are the first terminal and the second terminal of the voltage drop compensation device. The first terminal of the first diode D1 is connected to the inverting input terminal of the first operational amplifier Amp1, and the second terminal of the first diode D1 is connected to the output terminal of the first operational amplifier Amp1.

[0097] The first terminal and the second terminal of the second diode D2 are respectively the first terminal and the second terminal of the current anti-backflow device. The first terminal of the second diode D2 is directly or indirectly connected to the output terminal of the first operational amplifier Amp1, and the second terminal of the second diode D2 is connected to the first terminal of the holding capacitor Cs and the non-inverting input terminal of the second operational amplifier Amp2.

[0098] Preferably, the holding module 30 in this embodiment further includes a first resistor R1, a first capacitor C1, a second resistor R2, and a third resistor R3.

[0099] Specifically, the first terminal of the first resistor R1 is connected to the selection module 20, and the second terminal of the first resistor R1 is connected to the non-inverting input terminal of the first operational amplifier Amp1.

[0100] The first terminal of the first capacitor C1 is connected to the inverting input terminal of the first operational amplifier Amp1, and the second terminal of the first capacitor C1 is connected to the output terminal of the first operational amplifier Amp1.

[0101] The first terminal of the second resistor R2 is connected to the inverting input terminal of the first operational amplifier Amp1, and the second terminal of the second resistor R2 is connected to the inverting input terminal of the second operational amplifier Amp2.

[0102] The first terminal of the third resistor R3 is connected to the output terminal of the first operational amplifier Amp1, and the second terminal of the third resistor R3 is connected to the first terminal of the current anti-backflow device.

[0103] As Figure 3 shown, the comparison module 40 in this embodiment includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a comparator comp.

[0104] Specifically, the first terminal of the seventh resistor R7 is connected to the holding module 30, the second terminal of the seventh resistor R7 is connected to the non-inverting input terminal of the comparator comp and the first terminal of the eighth resistor R8, the second terminal of the eighth resistor R8 is connected to the output terminal of the comparator comp, the first terminal of the ninth resistor R9 is used to receive the reference signal Vcomp, and the second terminal of the ninth resistor R9 is connected to the inverting input terminal of the comparator comp.

[0105] The first terminal of the tenth resistor R10 is connected to the input voltage SV, the second terminal of the tenth resistor R10 is connected to the output terminal of the comparator comp, an overcurrent protection signal Sp is generated through the output terminal of the comparator comp, the first terminal of the eleventh resistor R11 is connected to the output terminal of the comparator comp, and the second terminal of the eleventh resistor R11 is connected to the reference potential.

[0106] As Figure 5 shown, in the initial stage (T0 - T1), the peak hold signal in this embodiment follows the input current change.

[0107] When the input current exceeds the set threshold (T1 - T2), the comparison module 40 compares the peak hold signal with the reference signal Vcomp and generates an overcurrent protection signal Sp with a high level.

[0108] After the input current starts to decrease from the maximum value (T2 - T3 and T3 - T4), the peak hold signal remains at the highest value for a certain period of time. Therefore, the overcurrent protection signal Sp also remains at a high level for a certain period of time.

[0109] When the set hold time ends (at time T4), the peak hold signal decreases and the overcurrent hold signal jumps from a high level to a low level. It can be understood that the hold time of the peak hold signal and the overcurrent protection signal Sp can be controlled by adjusting the capacitance value of the hold capacitor Cs.

[0110] In addition, it is worth noting that in the above - mentioned embodiment, the overcurrent protection circuit is described with three sampling modules 10 and three selection modules 20. The three sampling modules 10 respectively receive one of the three - phase input currents, and a selection module 20 is connected between each sampling module 10 and the hold module 30. It can be understood that in other alternative embodiments, the overcurrent protection circuit can include one sampling module 10 to receive one of the three - phase input currents, or the overcurrent protection circuit can include multiple sampling modules 10 to receive multiple sets of three - phase input currents.

[0111] Another embodiment of the present utility model further provides a photovoltaic inverter, and the photovoltaic inverter includes the above - mentioned overcurrent protection circuit.

[0112] Another embodiment of the present utility model further provides a photovoltaic system, and the photovoltaic system includes the above - mentioned photovoltaic inverter.

[0113] From the above technical solutions, it can be seen that the present utility model has the following beneficial effects:

[0114] The overcurrent protection circuit, photovoltaic inverter and photovoltaic system of the present utility model control the overcurrent protection signal to remain for a certain period of time even after the input current returns to normal through the hold module, solving the problem of insufficient protection delay time in general circuits and avoiding the situation where the first - stage protection has recovered while the subsequent - stage protection has not been triggered.

[0115] The present utility model prevents the reverse flow of charges in the hold capacitor through a current anti - backflow device, and at the same time offsets the voltage drop generated by the current anti - backflow device through a voltage - drop compensation device, improving the accuracy of the actual protection value.

[0116] The present utility model rectifies a sine wave into a sine half - wave through an inverting operational amplifier unit, realizing correct overcurrent detection even when overcurrent or short - circuit occurs in the negative half - axis of the sine wave.

[0117] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above-described exemplary embodiments, and the present utility model can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present utility model. Any reference signs in the claims should not be construed as limiting the claims involved.

[0118] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An overcurrent protection circuit, characterized in that: The overcurrent protection circuit includes a sampling module, a selection module, a holding module and a comparison module; wherein, The sampling module receives an input current and generates an in-phase sampling signal and an anti-phase sampling signal based on the input current; The selection module is connected to the sampling module and is used to generate a peak sampling signal according to the in-phase sampling signal and the anti-phase sampling signal; The holding module is connected to the selection module and is used to hold the peak sampling signal and generate a peak holding signal; The comparison module is connected to the holding module and is used for comparing the peak holding signal with the reference signal and generating an overcurrent protection signal.

2. The overcurrent protection circuit according to claim 1, characterized in that: The holding module includes a first operational amplifier, a holding capacitor, a current backflow prevention device, a second operational amplifier and a voltage drop compensation device; wherein, The non-inverting input terminal of the first operational amplifier is directly or indirectly connected to the selection module to receive the peak sampling signal, the inverting input terminal of the first operational amplifier is connected to the first terminal of the voltage drop compensation device, and the output terminal of the first operational amplifier is connected to the second terminal of the voltage drop compensation device; The first end of the current backflow prevention device is directly or indirectly connected to the output end of the first operational amplifier, the second end of the current backflow prevention device is connected to the first end of the holding capacitor, and the second end of the holding capacitor is connected to the reference potential; The inverting input terminal of the second operational amplifier is connected to the inverting input terminal of the second operational amplifier, the non-inverting input terminal of the second operational amplifier is connected to the second terminal of the current backflow prevention device, and the output terminal of the second operational amplifier is directly or indirectly connected to the inverting input terminal of the connected first operational amplifier.

3. The overcurrent protection circuit according to claim 2, characterized in that: The voltage drop compensation device includes a first diode, a first end of the first diode is connected to the inverting input end of the first operational amplifier, and a second end of the first diode is connected to the output end of the first operational amplifier; and / or, The current backflow prevention device includes a second diode, a first end of the second diode is directly or indirectly connected to the output end of the first operational amplifier, and a second end of the second diode is connected to the first end of the holding capacitor and the non-inverting input end of the second operational amplifier.

4. The overcurrent protection circuit according to claim 2, characterized in that: The holding module further includes a first resistor, a first capacitor, a second resistor and a third resistor; wherein, A first end of the first resistor is connected to the selection module, and a second end of the first resistor is connected to the non-inverting input end of the first operational amplifier; The first end of the first capacitor is connected to the inverting input end of the first operational amplifier, and the second end of the first capacitor is connected to the output end of the first operational amplifier; The first end of the second resistor is connected to the inverting input terminal of the first operational amplifier, and the second end of the second resistor is connected to the inverting input terminal of the second operational amplifier; A first end of the third resistor is connected to the output end of the first operational amplifier, and a second end of the third resistor is connected to a first end of the current backflow prevention device.

5. The overcurrent protection circuit according to claim 1, characterized in that: The sampling module includes a current sensor, a differential operational amplifier unit, a common-phase operational amplifier unit and an inverting operational amplifier unit; wherein, The current sensor is used to collect input current; The differential operational amplifier unit is connected to the current sensor and is used to perform gain amplification on the input current and generate a first signal; The in-phase operational amplifier unit is connected to the differential operational amplifier unit, and is used to generate an in-phase sampling signal based on the first signal; The inverting operational amplifier unit is connected to the differential operational amplifier unit and is used to invert the first signal to generate an inverted sampling signal, and the phase difference between the in-phase sampling signal and the inverted sampling signal is 180°.

6. The overcurrent protection circuit according to claim 5, characterized in that: The differential operational amplifier unit includes a twelfth resistor, a second capacitor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third capacitor and a seventh operational amplifier; wherein, The first end of the twelfth resistor is connected to the reference potential, the second end of the twelfth resistor is connected to the non-inverting input terminal of the seventh operational amplifier, the first end of the second capacitor is connected to the reference potential, and the second end of the second capacitor is connected to the non-inverting input terminal of the seventh operational amplifier; The first end of the thirteenth resistor is connected to the current sensor, the second end of the thirteenth resistor is connected to the non-inverting input terminal of the seventh operational amplifier, the first end of the fourteenth resistor is connected to the current sensor, and the second end of the fourteenth resistor is connected to the inverting input terminal of the seventh operational amplifier; The first end of the fifteenth resistor is connected to the inverting input terminal of the seventh operational amplifier, the second end of the fifteenth resistor is connected to the output terminal of the seventh operational amplifier, the first end of the third capacitor is connected to the inverting input terminal of the seventh operational amplifier, the second end of the third capacitor is connected to the output terminal of the seventh operational amplifier and generates a first signal through the output terminal of the seventh operational amplifier.

7. The overcurrent protection circuit according to claim 5, characterized in that: The in-phase operational amplifier unit includes a fourth resistor and a third operational amplifier; wherein, A first end of the fourth resistor is connected to the differential operational amplifier unit to receive the first signal, and a second end of the fourth resistor is connected to the non-inverting input end of the third operational amplifier; The inverting input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier and generates an in-phase sampling signal.

8. The overcurrent protection circuit according to claim 5, characterized in that: The inverting operational amplifier unit includes a fifth resistor, a sixth resistor and a fourth operational amplifier; wherein, The first end of the fifth resistor is connected to the differential operational amplifier unit to receive the first signal, and the second end of the fifth resistor is connected to the inverting input end of the fourth operational amplifier; The first end of the sixth resistor is connected to the inverting input end of the fourth operational amplifier, and the second end of the sixth resistor is connected to the output end of the fourth operational amplifier; The non-inverting input terminal of the fourth operational amplifier is connected to the reference potential, and the output terminal of the fourth operational amplifier generates an inverted sampling signal.

9. The overcurrent protection circuit according to claim 1, characterized in that: The selection module includes a fifth operational amplifier, a third diode, a sixth operational amplifier and a fourth diode; wherein, The in-phase input terminal of the fifth operational amplifier is connected to the sampling module to receive the in-phase sampling signal, the inverting input terminal of the fifth operational amplifier is connected to the second end of the third diode, and the output terminal of the fifth operational amplifier is connected to the first end of the third diode; The non-inverting input terminal of the sixth operational amplifier is connected to the sampling module to receive the inverted sampling signal, the inverting input terminal of the sixth operational amplifier is connected to the second terminal of the fourth diode, and the output terminal of the sixth operational amplifier is connected to the first terminal of the fourth diode.

10. The overcurrent protection circuit according to claim 1, characterized in that: The comparison module includes a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a comparator; wherein, The first end of the seventh resistor is connected to the holding module, the second end of the seventh resistor is connected to the non-inverting input terminal of the comparator and the first end of the eighth resistor, the second end of the eighth resistor is connected to the output terminal of the comparator, the first end of the ninth resistor is used to receive the reference signal, and the second end of the ninth resistor is connected to the inverting input terminal of the comparator; The first end of the tenth resistor is connected to the input voltage, the second end of the tenth resistor is connected to the output end of the comparator and generates an overcurrent protection signal, the first end of the eleventh resistor is connected to the output end of the comparator, and the second end of the eleventh resistor is connected to the reference potential.

11. The overcurrent protection circuit according to claim 1, characterized in that: The overcurrent protection circuit includes three sampling modules to respectively receive one phase of the three-phase input current, and a selection module is connected between each sampling module and the holding module.

12. A photovoltaic inverter, characterized in that: The photovoltaic inverter comprises the overcurrent protection circuit according to any one of claims 1 to 11.

13. A photovoltaic system, characterized in that: The photovoltaic system comprises the photovoltaic inverter according to claim 12.

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