Superspeed ultra-wideband radio cluster concurrent detection analysis and countering system

Abstract

The utility model is suitable for the technical field of radio attack and anti-penetration technology and electronic warfare application, and relates to an ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countering system, which comprises a core subnet cluster control system, the wireless communication module is responsible for man-machine interface interaction operation related to radio detection and countering, radio bottom layer detection and countering related parameter configuration, internal subnet communication, child node control, child node state detection query, system state monitoring, radar scanning and external communication; the ultra-wideband cluster radio frequency power amplification system is used for amplifying the power of radio frequency signals output by each sub-node of the core sub-network cluster control system so as to meet the requirements of long-distance radio cluster concurrent detection, countering, penetration testing and analysis; and the NAS storage server is used for receiving the spectrum detection data of the central control node in the core subnet cluster control system and realizing the function of a radio detection spectrum recorder. The detection analysis and countering system provided by the utility model is high in flexibility, expansibility and compatibility.

Description

Technical Field

[0001] The utility model belongs to the technical fields of radio attack and defense penetration technology and electronic warfare application technology, and particularly relates to a super-high-speed and super-wideband radio cluster concurrent detection, analysis and countermeasure system. Background Art

[0002] Wireless communication has been widely applied in various fields (including but not limited to automotive electronics, intelligent security, smart home, military electronics, satellite communication, wireless radar, radio countermeasure, industrial control power, etc.). The detection and countermeasure of traditional wireless signals mainly have two design concepts based on Hardware Defination Radio (HDR for short) and Software Defination Radio (SDR for short). The main characteristics of the SDR software-defined radio detection and countermeasure system are that it seriously depends on the CPU computing power and the efficiency of modulation and demodulation detection or countermeasure algorithms, and has high requirements for the professional qualities and R & D and test experience of R & D personnel. At the same time, it has extremely high requirements for software high-end processing capabilities such as software programming ability, underlying driver optimization, mathematics discipline, and CPU instruction set operation optimization. Moreover, the real-time performance and quality of radio detection and countermeasure are relatively lower than those of the hardware-defined radio detection and countermeasure system under the same hardware platform. The main characteristics of the HDR hardware-defined radio reconnaissance and countermeasure system are that the radio detection and countermeasure efficiency and comprehensive performance are very high, but it has deficiencies in flexibility and scalability, and at the same time has high requirements for the professional qualities of RF R & D personnel.

[0003] The underlying technology hardware architectures of traditional radio detection and countermeasure systems mostly consist of three parts: RF front-end, intermediate frequency conversion, and baseband processing. The overall design is relatively complex, with high costs, long R & D and debugging cycles, and great difficulties. After the key indicators of relevant radio underlying detection and countermeasures are designed and formed, they cannot be changed extensively and flexibly, resulting in the fact that their related products or technologies can only be applicable to a single radio detection and countermeasure application scenario. Although there are many similar radio reconnaissance and countermeasure products on the market (such as unmanned aerial vehicle countermeasure guns), most of them can only meet specific or single radio reconnaissance and countermeasure application scenarios, have great limitations, cannot meet the requirements of large-scale application and promotion, and are even less capable of meeting the requirements of future complex radio countermeasures. For the core technical indicators related to radio underlying detection and countermeasures, such as the underlying signal link, transmission rate, bit error rate, throughput, bit stream, effective bit payload rate, analog baseband signal, bandwidth, signal-to-noise ratio, backdoor Bug, and other real baseband signal transmission characteristics are invisible to users, and mainly rely on the unilateral interpretation of the technical manuals provided by manufacturers.

[0004] Therefore, how to provide a radio detection and countermeasure system with high flexibility, scalability, and compatibility, which combines software-defined radio (SDR) and high-speed hardware-defined radio (HDR), is an urgent problem to be solved by those skilled in the art. Summary of the Utility Model

[0005] The purpose of the present utility model is to provide an ultra-high-speed and ultra-wideband radio cluster concurrent detection, analysis, and countermeasure system to solve the problems of insufficient flexibility, scalability, and compatibility in the existing radio signal detection and countermeasure systems.

[0006] To solve the above technical problems, the present utility model adopts the following technical solutions:

[0007] The present utility model provides an ultra-high-speed and ultra-wideband radio cluster concurrent detection, analysis, and countermeasure system, including:

[0008] A core subnet cluster control system, including a central control node and radio reconnaissance and countermeasure sub-nodes, which is responsible for human-machine interface interaction operations related to radio detection and countermeasure, configuration of radio underlying detection and countermeasure related parameters, internal subnet communication, sub-node control, sub-node status detection and query, system status monitoring, radar scanning, and external communication;

[0009] An ultra-wideband cluster radio frequency power amplification system, including several ultra-wideband radio frequency power amplification modules, which is used to amplify the power of the radio frequency signals output by each sub-node of the core subnet cluster control system to meet the requirements of long-distance radio cluster concurrent detection, countermeasure, penetration testing, and analysis;

[0010] A NAS storage server, which is used to receive the spectrum detection data of the central control node in the core subnet cluster control system and implement the function of a radio detection spectrum recorder;

[0011] The core subnet cluster control system is respectively communicatively connected to the ultra-wideband cluster radio frequency power amplification system and the NAS storage server.

[0012] Further, the central control node includes a CPU / MCU module unit, an LCD display module, an external PS / 2 keyboard, a VGA interface driver chip circuit, a CANFD driver circuit, an Ethernet driver circuit, an ADC voltage division and IO detection circuit, an RTC clock circuit, a FLASH storage circuit, and a first power management module. The CPU / MCU module unit is respectively communicatively connected to the LCD display module, the external PS / 2 keyboard, the VGA interface driver chip circuit, the CANFD driver circuit, the Ethernet driver circuit, the ADC voltage division and IO detection circuit, the RTC clock circuit, and the FLASH storage circuit.

[0013] Further, the rated input voltage of the first power management module is +5V, and the output voltage is +3.3V, which is used to supply power to the CPU / MCU module unit, LCD display module, external PS / 2 keyboard, VGA interface driver chip circuit, CANFD driver circuit, Ethernet driver circuit, ADC voltage division and IO detection circuit, RTC clock circuit, and FLASH storage circuit.

[0014] Further, the radio reconnaissance and countermeasure sub-node includes a wireless receiving link and a wireless transmitting link. The wireless receiving link includes a first high-performance zero-IF architecture wireless transceiver integrated chip circuit, a high-speed parallel accumulator circuit module, a high-speed DAC module, a high-speed FIFO receiving module, a high-speed hardware PLL phase-locked loop variable configuration demodulation module, a first MCU / CPU / ADC module, a first RS232 / UART interface circuit, a first TCP / IP Ethernet chip / circuit, a first external trigger circuit, an RX1 balun balance circuit, a pre-stage low-noise amplification circuit, and an LED indication circuit. The first high-performance zero-IF architecture wireless transceiver integrated chip circuit is respectively communicatively connected to the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the first MCU / CPU / ADC module, and the RX1 balun balance circuit. The high-speed DAC module is respectively communicatively connected to the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, and the high-speed hardware PLL phase-locked loop variable configuration demodulation module. The high-speed hardware PLL phase-locked loop variable configuration demodulation module is communicatively connected to the first MCU / CPU / ADC module. The high-speed FIFO receiving module is communicatively connected to the first MCU / CPU / ADC module. The first MCU / CPU / ADC module is also respectively communicatively connected to the first RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, the first external trigger circuit, and the LED indication circuit. The RX1 balun balance circuit is also communicatively connected to the pre-stage low-noise amplification circuit.

[0015] Further, the wireless transmission link includes a second high-performance zero-IF architecture wireless transceiver integrated chip circuit, a high-speed FIFO transmission module, a second MCU / CPU / ADC module, a second RS232 / UART interface circuit, a second TCP / IP Ethernet chip / circuit, a second external trigger circuit, a TX1 balun balancing circuit, a radio frequency power amplifier module, and a second power management module. The second high-performance zero-IF architecture wireless transceiver integrated chip circuit is respectively communicatively connected to the high-speed FIFO transmission module, the second MCU / CPU / ADC module, and the TX1 balun balancing circuit. The high-speed FIFO transmission module is communicatively connected to the second MCU / CPU / ADC module. The second MCU / CPU / ADC module is also respectively communicatively connected to the second RS232 / UART interface circuit, the second TCP / IP Ethernet chip / circuit, and the second external trigger circuit. The TX1 balun balancing circuit is also communicatively connected to the radio frequency power amplifier module.

[0016] Further, the rated input voltage of the second power management module is +5V, and the output voltages include +3.3V, +2.85V, +2.5V, and +1.3V. +5V is used to supply power to the high-speed parallel accumulator circuit module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the first MCU / CPU / ADC module, the second MCU / CPU / ADC module, the pre-stage low-noise amplification circuit, and the radio frequency power amplifier module. +3.3V is used to supply power to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit, the second high-performance zero-IF architecture wireless transceiver integrated chip circuit, the high-speed DAC module, the high-speed FIFO reception module, the high-speed FIFO transmission module, the first RS232 / UART interface circuit, the second RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, and the second TCP / IP Ethernet chip / circuit. +2.85V is used to supply power to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit. +2.5V is used to supply power to the high-speed FIFO reception module and the high-speed FIFO transmission module. +1.3V is used to supply power to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit.

[0017] Further, each of the ultra-wideband radio frequency power amplifier modules is connected to one of the radio reconnaissance and countermeasure sub-nodes.

[0018] Further, the spectrum detection data received by the NAS storage server includes the RSSI signal strength values of real-time dynamic scanning, the original data of the detected radio baseband signals, the real-time or triggered baseband decoding data, and various radio reconnaissance and countermeasure trigger events.

[0019] Compared with the prior art, the ultra-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by the present utility model has at least the following beneficial effects:

[0020] Most of the related products for radio reconnaissance and countermeasure in the prior art can only meet specific or single radio reconnaissance and countermeasure application scenarios, which have great limitations and cannot meet the requirements of large-scale application and promotion. The present utility model utilizes an internal dual-networking technology (dual-networking of Ethernet and CANFD local area network), introduces key design elements of cluster-type concurrent detection and countermeasure (multiple independent radio detection & countermeasure nodes are carried in each cluster unit), greatly improves key core technical indicators such as high-speed dynamic response, high bandwidth, high sensitivity, and frequency coverage range of the system's radio detection and countermeasure. At the same time, the system also integrates and correlates high-speed software and hardware trigger countermeasure mechanisms, trigger sources, and trigger events related to radio detection and countermeasure to form a radio attack and defense closed-loop detection and countermeasure link, effectively improving the comprehensive performance of the radio detection and countermeasure system. With the help of NAS large-capacity network storage technology, the function of a radio detection spectrum recorder with large capacity and long time is further realized for users' later targeted offline analysis; the present utility model also effectively combines software-defined radio (SDR) and high-speed hardware-defined radio (HDR). While ensuring the flexibility, scalability, and compatibility characteristics of traditional software-defined radio (SDR) detection and countermeasure applications, it also has the exclusive technical characteristics of hardware-defined radio (HDR), and the entire system has high flexibility, scalability, and compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the solution of the present utility model, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 It is a schematic diagram of the overall architecture of an ultra-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0023] Figure 2 It is a schematic diagram of the central control node architecture of the core subnet cluster control system of an ultra-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0024] Figure 3 It is a circuit diagram of the LCD display screen module of the central control node of the core subnet cluster control system of an ultra-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0025] Figure 4 External PS / 2 keyboard circuit diagram of the central control node of the core subnet cluster control system of a high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0026] Figure 5 VGA interface driver chip circuit diagram of the central control node of the core subnet cluster control system of a high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0027] Figure 6 CANFD driver circuit diagram of the central control node of the core subnet cluster control system of a high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0028] Figure 7 ADC voltage division and IO detection circuit diagram of the central control node of the core subnet cluster control system of a high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0029] Figure 8 RTC clock circuit diagram of the central control node of the core subnet cluster control system of a high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0030] Figure 9 FLASH storage circuit diagram of the central control node of the core subnet cluster control system of a high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0031] Figure 10 Power supply schematic diagram of the first power management module of the central control node of the core subnet cluster control system of a high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0032] Figure 11 Wireless receiving link architecture diagram of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0033] Figure 12 Wireless transmitting link architecture diagram of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0034] Figure 13Circuit diagram of the high-speed parallel accumulator circuit module in the wireless receiving link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0035] Figure 14 Circuit diagram of the high-speed DAC module in the wireless receiving link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0036] Figure 15 Circuit diagram of the high-speed FIFO receiving module in the wireless receiving link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0037] Figure 16 Architecture diagram of the high-speed hardware PLL phase-locked loop variable configuration demodulation module in the wireless receiving link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0038] Figure 17 Circuit diagram of the first external trigger in the wireless receiving link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0039] Figure 18 Circuit diagram of the RX1 balun balance in the wireless receiving link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0040] Figure 19 Circuit diagram of the pre-stage low-noise amplification in the wireless receiving link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0041] Figure 20 Circuit diagram of the LED indication in the wireless receiving link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system provided by an embodiment of the present utility model;

[0042] Figure 21Circuit diagram of the high-speed FIFO transmission module in the wireless transmission link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present utility model;

[0043] Figure 22 Circuit diagram of the second external trigger in the wireless transmission link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present utility model;

[0044] Figure 23 Circuit diagram of the TX1 balun balance in the wireless transmission link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present utility model;

[0045] Figure 24 Circuit diagram of the radio frequency power amplifier module in the wireless transmission link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present utility model;

[0046] Figure 25 Power supply schematic diagram of the second power management module in the wireless transmission link of the radio reconnaissance and countermeasure sub-node of the core subnet cluster control system of a super-high-speed and ultra-wideband radio cluster concurrent detection analysis and countermeasure system provided by an embodiment of the present utility model. Detailed implementation manners

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs; the terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. For example, terms such as "length", "width", "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or position based on the orientation or position shown in the drawings, and are only for convenience of description and cannot be construed as a limitation to the technical solution of the present application.

[0048] In the description, claims and the above description of the drawings of the present utility model, the terms "comprising", "having" and any variations thereof are intended to cover non-exclusive inclusion; the terms "first", "second", etc. in the description, claims or the above drawings of the present utility model are used to distinguish different objects, rather than to describe a specific order. In the description, claims and the above description of the drawings of the present utility model, when an element is referred to as being "fixed to", "mounted on", "disposed on" or "connected to" another element, it may be directly or indirectly located on that other element. For example, when an element is referred to as being "connected to" another element, it may be directly or indirectly connected to that other element.

[0049] In addition, the mention of "embodiment" herein means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present utility model. The phrase appearing at various positions in the description does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0050] The present utility model provides a super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system, which is applied to the detection and countermeasure process of wireless signals. The super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system includes:

[0051] A core subnet cluster control system, which is responsible for human-machine interface interaction operations related to radio detection and countermeasures, configuration of radio underlying detection and countermeasure related parameters, internal subnet communication, sub-node control, sub-node status detection and query, system status monitoring, radar scanning, and external communication; a ultra-wideband cluster radio frequency power amplification system, which is used to amplify the power of the radio frequency signals output by each sub-node of the core subnet cluster control system to meet the requirements of long-distance radio cluster concurrent detection, countermeasures, penetration testing and analysis; a NAS storage server, which is used to receive the spectrum detection data of the central control node in the core subnet cluster control system to implement the function of a radio detection spectrum recorder.

[0052] The detection, analysis and countermeasure system provided by the present utility model has higher flexibility, expandability and compatibility than the prior art.

[0053] In order to enable those skilled in the art to better understand the solution of the present utility model, the technical solutions in the embodiments of the present utility model will be clearly and completely described below in conjunction with the drawings.

[0054] The present utility model provides a super-high-speed and ultra-wideband radio cluster concurrent detection, analysis and countermeasure system, which is applied to the detection and countermeasure process of wireless signals. In combination with Figures 1 to 25, in this embodiment, the ultra-high-speed ultra-wideband radio cluster concurrent detection analysis and countermeasure system includes:

[0055] A core subnet cluster control system, which can work independently and is mainly responsible for core functions such as man-machine interface interaction operations related to radio detection and countermeasures, parameter configuration related to radio underlying detection and countermeasures, internal subnet communication, sub-node control, sub-node status detection and query, system status monitoring, radar scanning, external communication, etc.; an ultra-wideband cluster radio frequency power amplification system, which is mainly responsible for further power amplifying the radio frequency signals output by each sub-node of the core subnet cluster control system to meet application scenarios such as long-distance radio cluster concurrent detection, countermeasures, penetration testing, analysis, etc.; a NAS storage server, which is a large-capacity storage server that receives spectrum detection data from the central control node in the core subnet cluster control system and is mainly used to implement the function of a radio detection spectrum recorder, storing relevant spectrum data of radio detection (including but not limited to the RSSI signal strength values of real-time dynamic scanning, the original data of detected radio baseband signals, real-time or triggered baseband decoding data, various radio detection and countermeasure trigger events, etc.); the core subnet cluster control system is communicatively connected to the ultra-wideband cluster radio frequency power amplification system and the NAS storage server respectively.

[0056] Furthermore, in this embodiment, the core subnet cluster control system includes a central control node and radio reconnaissance and countermeasure sub-nodes. The central control node includes a CPU / MCU module unit, an LCD display module, an external PS / 2 keyboard, a VGA interface driver chip circuit, a CANFD driver circuit, an Ethernet driver circuit, an ADC voltage division and IO detection circuit, an RTC clock circuit, a FLASH storage circuit, and a first power management module. The CPU / MCU module unit is communicatively connected to the LCD display module, the external PS / 2 keyboard, the VGA interface driver chip circuit, the CANFD driver circuit, the Ethernet driver circuit, the ADC voltage division and IO detection circuit, the RTC clock circuit, and the FLASH storage circuit respectively. The central control node is an important control node of the core subnet cluster control system. It takes the external PS2 keyboard as its command input and is mainly responsible for the relevant parameter configuration, trigger configuration, system status monitoring, spectrum recording and storage drive, and external communication of each radio reconnaissance and countermeasure sub-node. At the same time, it conducts man-machine interaction operations through the UI interface of a 10.1-inch LCD screen, displaying relevant UI interface operation menus, system information, radio dynamic scanning, and information related to detection and countermeasure parameter configuration. Secondly, it is also responsible for driving and reading the RTC clock circuit to ensure normal clock display, driving the external FLASH chip to facilitate storing necessary configuration information. Additionally, through the voltage division and IO detection circuit of the external DAC, it monitors the voltage of the external lithium battery and the power supply status of the main and backup power supplies in real time.

[0057] Specifically, the main functions of the CPU / MCU module unit include:

[0058] Drive an external PS / 2 keyboard through the standard PS / 2 interface (PS2_CLK, PS2_DAT), detect external keyboard input, and facilitate human-machine interface operations; drive a 10.1-inch LCD display through the RGB565 standard interface to display human-machine interaction operations on the UI interface, and display relevant information such as radio detection & countermeasure, related parameter configuration, and status detection; convert the content displayed on the LCD screen into a standard VGA interface output through the RGB565 standard interface for convenient display on an external monitor; drive a CANFD driver chip (CAN_H, CAN_L) through the CANFD interface to communicate with each sub-node within the subnet; drive an Ethernet driver chip through the RMII interface to communicate with each sub-node within the subnet or an external network; drive an RTC clock chip through the I2C interface (SCL, SCK) to read the real-time clock; drive a FLASH chip through the I2C interface (SCL, SCK) to store necessary configuration information; detect the voltage of the lithium battery and the status of the external main and backup power supplies through the ADC voltage division circuit and the IO detection circuit; implement the function of a radio detection spectrum recorder, drive an external NAS large-capacity network storage server, and store relevant spectrum data of radio detection (including but not limited to the RSSI signal strength value of real-time dynamic scanning, the original data of the detected radio baseband signal, real-time or triggered baseband decoding data, various radio detection & countermeasure trigger events, etc.).

[0059] Specifically, the LCD display module is driven by the CPU / MCU module unit and is used for UI interface display to facilitate human-machine interaction operations. The display content includes but is not limited to relevant UI interface operation menus, system information, radio dynamic scanning, detection and countermeasure parameter configuration, and other relevant information.

[0060] Specifically, the external PS / 2 keyboard is driven by the CPU / MCU module unit. PS2_CLK is the clock input signal of this circuit module (driven by the CPU / MCU module unit), and PS2_DAT is the bidirectional data transmission signal of this circuit module (driven or collected by the CPU / MCU module unit). The drive interface circuit is shown in the following figure. By connecting an external PS2 keyboard as its instruction input, it facilitates human-machine UI interface interaction operations.

[0061] Specifically, the VGA interface driver chip circuit is driven by the CPU / MCU module unit to convert the standard RGB565 video signal (provided by the high-performance CPU / MCU module unit circuit) into a VGA interface output for convenient synchronous display on an external monitor.

[0062] Specifically, the CANFD driver circuit is driven by the CPU / MCU module unit and communicates with each radio detection and countermeasure sub-node within the subnet. CAN_RX is the output signal of this circuit module and is output to the CANFD interface of the CPU / MCU module unit. CAN_TX is the input signal of this circuit module and is driven by the CPU / MCU module unit. CAN_SLEEP is the sleep control input signal of this circuit module and is provided by the drive of the CPU / MCU module unit. CAN_H and CAN_L are standard CANFD output signals and are led out through a 2Pin terminal block.

[0063] Specifically, the Ethernet driver circuit is driven by the CPU / MCU module unit through the RMII interface and communicates with each radio detection and countermeasure sub-node within the subnet or the external network. At the same time, it communicates with the external NAS mass network storage server to implement the spectrum recorder function, and transmits the relevant spectrum data of radio detection (including but not limited to the RSSI signal strength value of real-time dynamic scanning, the original data of the detected radio baseband signal, the real-time or triggered baseband decoding data, various radio detection & countermeasure trigger events, etc.).

[0064] Specifically, the ADC voltage division circuit uses precision resistors for voltage division to detect the lithium battery voltage. BAT_DAC is the output signal of this circuit module and is output to the CPU / MCU module unit for external lithium battery voltage acquisition. The IO detection circuit detects the external input digital quantity through an NPN-type MOS transistor and is used to detect the main and backup power states of the system. IO_INPUT is connected to the external main and backup power digital quantity, and the CHECK_IO signal is output to the CPU / MCU module unit.

[0065] Specifically, the RTC clock circuit provides accurate time and is driven by the CPU / MCU module unit through the standard I2C interface. SCL is the clock signal of the I2C interface and is output and provided by the CPU / MCU module unit. SDA is the bidirectional data transmission signal of the I2C interface.

[0066] Specifically, the FLASH storage circuit is used to save necessary configuration information and is driven by the CPU / MCU module unit through the standard I2C interface. SCL is the clock signal of the I2C interface and is output and provided by the CPU / MCU module unit. SDA is the bidirectional data transmission signal of the I2C interface.

[0067] Specifically, the first power management module is responsible for supplying power to each circuit unit module within the device. The rated input voltage is +5V / DC, and the output voltage is +3.3V.

[0068] Further, in this embodiment, the radio reconnaissance and countermeasure sub-node includes a wireless receiving link and a wireless transmitting link. The wireless receiving link includes a first high-performance zero-IF architecture wireless transceiver integrated chip circuit, a high-speed parallel accumulator circuit module, a high-speed DAC module, a high-speed FIFO receiving module, a high-speed hardware PLL phase-locked loop variable configuration demodulation module, a first MCU / CPU / ADC module, a first RS232 / UART interface circuit, a first TCP / IP Ethernet chip / circuit, a first external trigger circuit, an RX1 balun balance circuit, a pre-stage low-noise amplification circuit, and an LED indication circuit. The first high-performance zero-IF architecture wireless transceiver integrated chip circuit is respectively communicatively connected to the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the first MCU / CPU / ADC module, and the RX1 balun balance circuit. The high-speed DAC module is respectively communicatively connected to the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, and the high-speed hardware PLL phase-locked loop variable configuration demodulation module. The high-speed hardware PLL phase-locked loop variable configuration demodulation module is communicatively connected to the first MCU / CPU / ADC module. The high-speed FIFO receiving module is communicatively connected to the first MCU / CPU / ADC module. The first MCU / CPU / ADC module is also respectively communicatively connected to the first RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, the first external trigger circuit, and the LED indication circuit. The RX1 balun balance circuit is also communicatively connected to the pre-stage low-noise amplification circuit.

[0069] Specifically, the first high-performance zero-IF architecture wireless transceiver integrated chip circuit is one of the core circuit modules of the radio reconnaissance and countermeasure sub-node. It is designed based on the zero-IF architecture wireless transceiver integrated chip, adopting the concept of software-defined radio technology. Its main function is to configure various working parameters of the chip (SPI bus configuration) through the subsequent first MCU / CPU / ADC module circuit, including but not limited to parameters such as the wireless receiving channel, wireless receiving frequency, bandwidth, operating mode of the amplifier circuit, filtering characteristics, ADC sampling rate, output interface, and baseband signal output characteristics. It selects a specified wireless receiving channel to make it work in a specific wireless receiving working state, and the receiving frequency can be accurately and continuously adjusted within the range of 70 MHz to 6 GHz, so as to flexibly adapt to receiving wireless signals of different frequencies, ensuring the flexibility, scalability, and compatibility of wireless applications. It receives external specific radio signals through an external antenna. After being precisely processed by many internal unit circuits such as the internal preamplifier, local oscillator mixer, AGC / MGC amplifier circuit, filtering circuit, DAC, and ADC in this circuit module, it outputs a specific baseband IQ quadrature signal for the subsequent circuit module to use. The input signal of this circuit module is the RX balun balanced circuit (RX1) of the previous stage 1 channel, which uses a differential signal interface input, effectively suppressing common-mode noise and interference and improving the signal-to-noise ratio of the wireless received signal. The RESET signal is the internal reset signal of this circuit, which is controlled by the subsequent first MCU / CPU / ADC module circuit. The output signals VREF_CMP1 and VREF_CMP2 are the output signals of the internal DAC auxiliary unit of this circuit, providing the decision comparison reference voltage necessary for the subsequent "high-speed hardware PLL phase-locked loop variable configuration demodulation module" to demodulate the baseband signal. I[0:11] and Q[0:11] are the original baseband IQ quadrature output signals of this circuit module. Each baseband IQ quadrature signal is independently output in 12-bit parallel port, synchronously output to the subsequent high-speed parallel accumulator circuit module and high-speed FIFO receiving module, effectively improving the sampling rate and throughput of the wireless received baseband signal, ensuring the technical prerequisite for high-speed wireless communication transmission from the hardware bottom layer. DATA_CLK is the clock indication signal of the baseband IQ quadrature output signal, which can be configured in SDR or DDR working mode according to actual applications and synchronously output to the subsequent DAC module and high-speed FIFO receiving module. RX_FRAME is the baseband IQ quadrature signal transmission status indication signal, which is output to the subsequent first MCU / CPU / ADC module circuit. RESET is the reset control signal of this circuit module, which is controlled by the subsequent first MCU / CPU / ADC module circuit.

[0070] Specifically, the high-speed parallel accumulator circuit module is one of the most core implementation parts of the hardware-defined radio (HDR) technology concept. It consists of an I-signal high-speed parallel accumulator, a Q-signal high-speed parallel accumulator, and an addend initialization and configuration circuit. Its main function is to perform independent signed accumulation operations on the two original baseband IQ quadrature digital signals output by the previous-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module. The addend is initialized to 0x7ff (decimal value is 2047). The two signed positive and negative AC quadrature IQ signals (decimal value range is -2047 to +2047) output by the previous-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module are respectively converted into positive IQ signals greater than 0 (value range is 0 to +4047), which is convenient for the subsequent high-speed DAC module to process. The input signals of this circuit are the two original baseband IQ quadrature signals I[0:11] and Q[0:11] output by the previous-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module, and the output signals are the two accumulated IQ quadrature signals IADD[0:11] and QADD[0:11], which serve as the input signals for the subsequent high-speed DAC module circuit.

[0071] Specifically, the high-speed DAC module is one of the most core implementation parts of the hardware-defined radio (HDR) technology concept. It consists of an I-signal high-speed DAC and a Q-signal high-speed DAC circuit unit. Its main function is to perform high-speed DAC conversion on the two IQ quadrature signals IADD[0:11] and QADD[0:11] output by the previous-stage high-speed parallel accumulator circuit module, and convert the two IQ quadrature digital signals into IQ quadrature differential current analog signals for use by the subsequent high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit. The input signals of this module circuit are the two signals IADD[0:11] and QADD[0:11] output by the previous-stage high-speed parallel accumulator circuit module, and the DATA_CLK input signal is the DAC conversion clock drive signal, which is provided by the previous-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link). The output signals of this module circuit are the current differential signals Iia1 and Iia2 of the I quadrature signal and the current differential signals Qia1 and Qia2 of the Q quadrature signal, providing appropriate baseband demodulation input signals for the subsequent high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit.

[0072] Specifically, the high-speed FIFO receiving module is one of the most core implementation links of the high-speed software-defined radio (HDR) technology concept. It consists of an I-signal high-speed receiving FIFO, a Q-signal high-speed receiving FIFO, and a FIFO bypass control circuit unit. Its main function is to receive the IQ quadrature signal output by the previous-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module, perform high-speed FIFO caching on the IQ quadrature digital signal, relieve the operation and processing pressure of the subsequent-stage first MCU / CPU / ADC module, and effectively improve the processing ability of high-speed baseband signal demodulation. The input signals I[0:11] and Q[0:11] are the IQ quadrature signals output by the previous-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module. The input signal DATA_CLK is the reference clock signal for the IQ quadrature signal output by the previous-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module. The input signals RSTN, WEN, WRST, WCLK, REN, RRST, and RCLK are the reset signal, write FIFO control signal, and read FIFO control signal of this circuit module, which are controlled by the subsequent-stage first MCU / CPU / ADC module circuit. Iout[0:11] and Qout[0:11] are the baseband quadrature signal FIFO output signals of this circuit, which are provided for the subsequent-stage first MCU / CPU / ADC module to use, combined with radio scanning penetration applications to meet functions such as digital storage, software demodulation, operation processing, and analysis of baseband quadrature signals. The FIFO bypass control circuit controls whether the FIFO high-speed buffer is directly bypassed, and flexibly switches the internal IQ data stream reference clock indication signal. In the bypass mode, the FIFO high-speed buffer function fails, and the IQ data channels of the subsequent-stage first MCU / CPU / ADC module and the previous-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module are directly connected, facilitating real-time processing of the IQ data stream in low-speed wireless communication applications.

[0073] Specifically, the high-speed hardware PLL variable configuration demodulation module is one of the most core implementation links of the hardware-defined radio (HDR) technology concept. It is designed based on the high-speed hardware PLL variable configuration automatic tracking technology and the high-speed analog switch matrix technology. It consists of the I-signal high-speed hardware PLL variable configuration demodulation module and the Q-signal high-speed hardware PLL variable configuration demodulation module circuit units. Its main function is to perform real-time and synchronous hardware demodulation on the IQ quadrature current differential signal output by the previous high-speed DAC module. The demodulation mode supports three types simultaneously: baseband amplitude signal demodulation (AM), frequency signal demodulation (FM), and phase signal demodulation (PM). The output signal DEMOD_OUT_ASK1 of this circuit module is the digital output signal of baseband amplitude signal demodulation (AM), and the signal DEMOD_OUT_ASK2 is the auxiliary output signal of baseband amplitude signal demodulation (AM), which can provide auxiliary output for the demodulation of n-ASK standard baseband signals. The output signal DEMOD_OUT_PFSK1 is the digital output signal of baseband frequency signal demodulation (FM) and baseband phase signal demodulation (PM), and the output signal DEMOD_OUT_PFSK2 is the auxiliary output signal of baseband frequency signal demodulation (FM) and baseband phase signal demodulation (PM), which is used to indicate the current baseband signal frequency and phase locking state. All output signals are used by the subsequent first MCU / CPU / ADC module circuit module. ASK_CH_SEL_A, ASK_CH_SEL_B, and ASK_CH_SEL_C are the input control signals of this module circuit. According to the characteristics of baseband signals with different attributes, specific high-speed analog matrix switch channels for baseband amplitude signal demodulation (AM) are selected. PFSK_CH_SEL_A, PFSK_CH_SEL_B, and PFSK_CH_SEL_C are the input control signals of this module circuit. According to the characteristics of baseband signals with different attributes, specific high-speed analog matrix switch channels for baseband frequency signal demodulation (FM) and baseband phase signal demodulation (PM) are selected, effectively improving the diverse application scenarios of baseband signal demodulation and ensuring the flexibility, compatibility, and expandability of baseband signal demodulation. VREF_CMP1 and VREF_CMP2 are the DAC auxiliary output signals of the previous first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module, providing the baseband signal decision comparison reference voltage for this circuit module.

[0074] Specifically, the first MCU / CPU / ADC module is mainly responsible for controlling the circuit parameters of the front-end first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module according to the control instructions sent by the external digital interface, configuring relevant parameters to make it work in a specific wireless receiving state, and at the same time controlling and driving the high-speed FIFO receiving module and the high-speed hardware PLL phase-locked loop variable configuration demodulation module of the front-end, ensuring the efficient collaborative work of each circuit module inside the device. This circuit module also receives the digital baseband IQ quadrature signal output by the front-end first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module, and can directly perform software demodulation processing and analysis on this digital baseband signal based on software-defined radio technology to flexibly adapt to different wireless receiving application scenarios. This circuit module is also responsible for receiving and processing the hardware demodulation output signal output by the front-end high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit. Compared with software demodulation, the hardware demodulation output has higher efficiency and rate, stronger stability and anti-interference ability, effectively reducing the MCU / CPU operation processing pressure of this circuit module, and at the same time can significantly improve the hardware demodulation ability of high-speed wireless signals. DEMOD_OUT_ASK1 is the digital output signal of the baseband amplitude signal demodulation (AM) of this circuit module, and DEMOD_OUT_ASK2 is the auxiliary output signal of the baseband amplitude signal demodulation (AM) of this circuit module, both provided by the front-end high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit, which can realize the function of hardware baseband amplitude signal demodulation. Combining the output of relevant auxiliary signals, it can further realize the hardware demodulation function of n-ASK multi-mode baseband signals. DEMOD_OUT_PFSK1 is the digital input signal of the baseband frequency signal demodulation (FM) and the baseband phase signal demodulation (PM) of this circuit module, and DEMOD_OUT_PFSK2 is the auxiliary input signal of the baseband rate signal demodulation (FM) and the baseband phase signal demodulation (PM) of this circuit module, used to indicate the current baseband signal frequency and phase locking state, both provided by the front-end first high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit, which can realize the functions of hardware baseband frequency signal demodulation (FM) and baseband phase signal demodulation (PM). Combining the output of relevant auxiliary signals, it can further realize the hardware demodulation functions of n-FSK and n-PSK multi-mode baseband signals. ASK_CH_SEL_A, ASK_CH_SEL_B, and ASK_CH_SEL_C are the output control signals of this module circuit, controlling the front-end high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit to select specific baseband amplitude signal demodulation (AM) high-speed analog matrix switch configuration channels. PFSK_CH_SEL_A, PFSK_CH_SEL_B, and PFSK_CH_SEL_C are the output control signals of this module circuit,The control pre-stage high-speed hardware PLL phase-locked loop variable configuration demodulation module circuit selects specific baseband frequency signal demodulation (FM) and baseband phase signal demodulation (PM) high-speed analog matrix switch configuration channels. RSTN, WEN, WRST, WCLK, REN, RRST, and RCLK are the FIFO reset signal, write FIFO control signal, and read FIFO control signal of this circuit module, mainly responsible for controlling the pre-stage high-speed FIFO receiving module circuit to cooperate with other circuit modules. The Iout[0:11] and Qout[0:11] signals are provided by the pre-stage high-speed FIFO receiving module. The RX_FRAME is the IQ baseband signal transmission status indication signal, output by the pre-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module circuit. The SPI bus is the parameter configuration / reading bus of the pre-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module circuit. RESET is the reset control signal of the pre-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module circuit. This circuit module is also responsible for driving the first TCP / IP Ethernet chip / circuit module and the first RS232 / UART interface circuit module to achieve external wired interface communication transmission, which can meet the functional implementation of wireless base stations and wireless router gateways. At the same time, it also receives the trigger signals RX_EXT_TRG_IN1 and RX_EXT_TRG_IN2 of the first external trigger circuit module to ensure fast, accurate, and directional wireless reception capabilities. This circuit module conducts internal communication with the first MCU / CPU / ADC module circuit through the internal high-speed communication bus to ensure the real-time and high-efficiency of internal data interaction within the device. At the same time, this module circuit mainly controls the parameters of the pre-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module circuit according to the control instructions sent from the external digital interface, configures relevant parameters to make it work in a specific wireless transmission state, and simultaneously controls and drives the pre-stage high-speed FIFO transmission module to ensure the efficient cooperation of each circuit module within the device. This circuit module outputs specific original IQ quadrature baseband digital signals to the pre-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module based on different built-in baseband signal modulation algorithms and the concept of software-defined radio technology to flexibly adapt to different wireless transmission application scenarios. RSTN, WEN, WRST, WCLK, REN, RRST, and RCLK are the FIFO reset signal, write FIFO control signal, and read FIFO control output signal of this circuit module, mainly responsible for controlling the pre-stage high-speed FIFO transmission module circuit to cooperate with other circuit modules. The TX_FRAME is the IQ baseband signal transmission status indication signal, output to the pre-stage first high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module.The SPI bus is the parameter configuration / reading bus for the front-end first high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module. RESET is the reset control signal for the front-end first high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module. This circuit module is also responsible for driving the LED indication circuit, the first TCP / IP Ethernet chip / circuit module, and the first RS232 / UART interface circuit module to achieve external wired interface communication transmission, which can meet the functional implementation of wireless base stations and wireless router gateways. At the same time, it also receives the trigger signals TX_EXT_TRG_IN1 and TX_EXT_TRG_IN2 from the first external trigger circuit module to ensure fast, accurate, and directional wireless transmission capabilities. This circuit module conducts internal communication with the first MCU / CPU / ADC module circuit through the internal high-speed communication bus to ensure the real-time and high-efficiency of internal data interaction within this device.

[0075] Specifically, the first RS232 / UART interface circuit is driven by the first MCU / CPU / ADC module, with a high and adjustable communication rate, and can achieve RS232 / UART communication, support the protocol trigger function, and the trigger mode can support flexible configuration of RS232 / UART / Ethernet and is output through the terminal block.

[0076] Specifically, the first TCP / IP Ethernet chip / circuit is driven by the first MCU / CPU / ADC module based on the RMII interface, and can achieve high-speed network communication based on TCP / IP Ethernet, support the protocol trigger function, and the trigger mode can support flexible configuration of the RJ45 Ethernet communication protocol and is led out through the RJ45 interface.

[0077] Specifically, the first external trigger circuit is the key circuit part to achieve directional, high-speed, and accurate wireless reception of external trigger, comparator trigger, edge trigger, and manual trigger functions. It outputs two signals, RX_EXT_TRG_IN1 and RX_EXT_TRG_IN2, to the first MCU / CPU / ADC module circuit through the DC coupling method of resistor voltage division, and realizes the above different mode trigger functions according to the instructions sent remotely or the data configured in advance by the user, and is led out through the terminal block.

[0078] Specifically, the RX balun balance circuit consists of 1-channel independent balun balance circuits. Its main function is to achieve impedance matching between the front and rear stage circuits, convert the radio frequency front-end wireless signal from single-ended to differential and then balance output to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module of the rear stage, effectively suppressing the common-mode noise and external interference of the radio frequency front-end, improving the signal-to-noise ratio of the radio frequency front-end input signal. The RFIN signal is provided by the output of the front-end low-noise amplification circuit to further enhance the sensitivity of the received signal and meet the requirements of long-distance radio signal detection.

[0079] Specifically, the pre - stage low - noise amplification circuit is a low - noise amplification circuit for the pre - stage radio frequency (RF) received signal. Its purpose is to further enhance the sensitivity of the received signal to meet the requirements of long - distance radio signal detection. The input side is externally connected to an antenna, and the RXRF_OUT signal is the output signal of this circuit module, which is output to the next - stage RX balun balance circuit.

[0080] Specifically, the LED indication circuit is used to indicate the working status of each radio reconnaissance & counter - measure sub - node. LED_RUN, LED_SCAN, and LED_ATK respectively represent the sub - node running light, radar scanning indicator light, and radio counter - measure attack indicator light. The three control signals are all driven and provided by the first MCU / CPU / ADC module.

[0081] Specifically, the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) is designed based on the zero-IF architecture wireless transceiver integrated chip, adopting the concept of software-defined radio technology. Its main function is to configure various working parameters of the chip (SPI bus configuration) through the second MCU / CPU / ADC module circuit module at the rear stage, including but not limited to numerous parameters such as wireless transmission channels, wireless transmission frequencies, bandwidths, amplifier circuit working modes, filtering characteristics, ADC sampling rates, output interfaces, baseband signal output characteristics, etc. Select a specified wireless transmission channel to make it work in a specific wireless transmission working state. The transmission frequency can be precisely and continuously adjusted within the range of 46.875 MHz to 6 GHz, so as to flexibly adapt to the transmission of wireless signals with different frequencies, ensuring the flexibility, expandability, and compatibility of wireless applications. Drive the transmission of a specific IQ baseband quadrature signal stream through the second MCU / CPU / ADC module circuit at the rear stage, buffer and process it through the high-speed FIFO transmission module circuit, and then, after precise processing by many internal unit circuits such as the internal DAC, filtering circuit, AGC / MGC amplifier circuit, local oscillator mixing, and preamplifier in this circuit module, transmit a specific radio signal through the balun balance circuit and the external antenna. The output signal of this circuit module is the balun balance circuit (TX1) of the first-stage 1 channel, and it is output through a differential signal interface, which can effectively suppress common-mode noise and interference and improve the signal-to-noise ratio of the wireless transmission signal. Iout[0:11] and Qout[0:11] are the original baseband IQ quadrature input signals of this circuit module, provided by the high-speed FIFO transmission module at the rear stage. Each baseband quadrature signal is independently output in a 12-bit parallel port, effectively improving the sampling rate and throughput of the wireless transmission baseband signal, ensuring the technical prerequisites for high-speed wireless communication transmission from the hardware bottom layer. DATA_CLK is the clock indication signal of the baseband IQ quadrature output signal, which can be configured in the SDR or DDR working mode according to the actual application and synchronously output to the high-speed FIFO transmission module at the rear stage. TX_FRAME is the baseband IQ quadrature signal transmission status indication signal, and RESET is the reset control signal of this circuit module, both of which are controlled by the second MCU / CPU / ADC module circuit module at the rear stage.

[0082] Specifically, the high-speed FIFO transmission module is one of the most core implementation links of the high-speed software-defined radio (HDR) technology concept. It consists of an I-signal high-speed transmission FIFO, a Q-signal high-speed transmission FIFO, and a FIFO bypass control circuit unit. Its main function is to receive the IQ quadrature signals output by the subsequent second MCU / CPU / ADC module circuit, perform high-speed FIFO caching on the high-speed IQ quadrature digital signals, and then output them to the previous second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module, reducing the arithmetic processing pressure of the subsequent second MCU / CPU / ADC module and effectively improving the transmission / modulation processing ability of high-speed baseband signals. The input signals I[0:11] and Q[0:11] are the IQ quadrature output signals output by the subsequent second MCU / CPU / ADC module, the input signal DATA_CLK is the reference clock signal of the IQ quadrature input signal of the previous second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) module, and the input signals RSTN, WEN, WRST, WCLK, REN, RRST, and RCLK are the reset signal, write FIFO control signal, and read FIFO control signal of this circuit module, which are controlled by the subsequent second MCU / CPU / ADC module circuit. Iout[0:11] and Qout[0:11] are the FIFO output signals of the baseband IQ quadrature signals of this circuit, which are provided for the previous second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) to use for realizing the modulation output of software-defined radio baseband signals. The FIFO bypass control circuit controls whether the FIFO high-speed buffer is directly bypassed, and flexibly switches the internal IQ data stream reference clock indication signal. In the bypass mode, the FIFO high-speed buffer function fails, and the IQ data channels of the subsequent second MCU / CPU / ADC module and the previous second high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) module are directly connected, facilitating the real-time processing of the IQ data stream in low-speed wireless communication applications.

[0083] Specifically, the second external trigger circuit is a key circuit part for realizing the functions of directional, high-speed, and precise wireless transmission external trigger, comparator trigger, edge trigger, and manual trigger. It outputs two signals, TX_EXT_TRG_IN1 and TX_EXT_TRG_IN2, to the second MCU / CPU / ADC module circuit through a DC coupling method of resistor voltage division (or MOS transistor input acquisition), and realizes the above different mode trigger functions according to the instructions sent remotely or the data configured in advance by the user, and is led out through a terminal block.

[0084] Specifically, the TX balun balance circuit consists of a 1-channel independent balun balance circuit. Its main function is to achieve impedance matching between the front and rear stage circuits, convert the differential balanced radio frequency front-end wireless signal to single-ended and then output it to the antenna of the subsequent stage, effectively suppressing the common-mode noise and external interference of the radio frequency front-end, improving the signal-to-noise ratio of the radio frequency transmission signal. RFOUT is the output signal of this circuit module, which is provided to the input end of the first-stage radio frequency power amplifier module to further amplify the radio frequency signal.

[0085] Specifically, the radio frequency power amplifier module is a full-bandwidth radio frequency power amplification module with a high-bandwidth design, supporting the power amplification of radio frequency signals in the full frequency band. TXRF_IN is the radio frequency input signal, which is provided by the TX balun balance circuit and is output to the external antenna through the SMA interface.

[0086] Specifically, the second power management module is the internal power management module of each radio reconnaissance and countermeasure sub-node, responsible for supplying power to each circuit unit module in the device. The rated input voltage is +5V / DC, and the output voltages are: +3.3V, 2.85V, +2.5V, and +1.3V. +5V supplies power to the high-speed parallel accumulator circuit module, the PLL high-speed hardware phase-locked loop variable configuration demodulation module, the first MCU / CPU / ADC module, the second MCU / CPU / ADC module, the radio frequency power amplifier module, and the pre-stage low-noise amplification circuit. +3.3V is respectively output to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link), the high-speed DAC module, the high FIFO receiving module, the first RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link), and the high-speed FIFO sending module. +2.85V is respectively output to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link). +2.5V is respectively output to the high-speed FIFO receiving module and the high-speed FIFO sending module. +1.3V is respectively output to the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link).

[0087] In some other embodiments, the relevant FIFO modules of the first high-performance zero-IF architecture wireless transceiver integrated chip circuit (RX link) and the second high-performance zero-IF architecture wireless transceiver integrated chip circuit (TX link) can also be deleted according to the actual specific situation and directly bypassed to achieve the purpose of saving space and cost.

[0088] Furthermore, in this embodiment, the ultra-wideband cluster radio frequency power amplification system is a high-power radio transmission system, which is mainly responsible for further power amplifying the radio frequency signals output by each sub-node of the core subnet cluster control system to meet the application scenarios of long-distance radio cluster concurrent detection, countermeasure, penetration testing, analysis, etc. It adopts a cluster design internally. The system consists of 20 power amplification modules. Each module is correspondingly connected to the radio transmission output signal of a radio reconnaissance and countermeasure sub-node, meeting the requirements of high-power transmission for radio cluster concurrent countermeasures. RFIN is the radio frequency input signal, and the output signal is externally connected to a high-power antenna. A 50-ohm impedance matching circuit has been integrated and designed internally.

[0089] Furthermore, the NAS storage server is a large-capacity storage server, which uses a mature standard product on the market and communicates through network protocols. It receives the spectrum detection data from the central control node in the core subnet cluster control system and is mainly used to implement the function of a radio detection spectrum recorder, recording relevant spectrum data of radio detection (including but not limited to the RSSI signal strength value of real-time dynamic scanning, the original data of the detected radio baseband signal, real-time or triggered baseband decoding data, various radio detection & countermeasure trigger events, etc.).

[0090] Compared with the prior art, most of the related products for radio reconnaissance and countermeasure in the prior art can only meet specific or single radio reconnaissance and countermeasure application scenarios, with great limitations and unable to meet large-scale application and promotion. The utility model uses the internal dual-networking technology (dual-networking of Ethernet and CANFD local area network), introduces the key design elements of cluster-style concurrent detection and countermeasure (each cluster unit has multiple independent radio detection & countermeasure nodes), greatly improving the key core technical indicators such as the high-speed dynamic response, high bandwidth, high sensitivity, and frequency coverage range of the system's radio detection and countermeasure. At the same time, the system also integrates and correlates the high-speed software and hardware trigger countermeasure mechanisms, trigger sources, and trigger events related to radio detection and countermeasure to form a radio attack and defense closed-loop detection and countermeasure link, effectively improving the comprehensive performance of the radio detection and countermeasure system. With the help of NAS large-capacity network storage technology, the function of a large-capacity long-term radio detection spectrum recorder is further realized for users' subsequent targeted analysis; the utility model also effectively combines software-defined radio (SDR) and high-speed hardware-defined radio (HDR). While ensuring the flexibility, scalability, and compatibility characteristics of traditional software-defined radio (SDR) detection and countermeasure applications, it also has the exclusive technical characteristics of hardware-defined radio (HDR). The entire system has high flexibility, scalability, and compatibility.

[0091] Obviously, the embodiments described above are only the preferred embodiments of the present utility model, rather than all embodiments. The preferred embodiments of the present utility model are shown in the accompanying drawings, but do not limit the patent scope of the present utility model. The present utility model can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosed content of the present utility model more thorough and comprehensive. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing specific embodiments, or perform equivalent replacements on some of the technical features. Any equivalent structure made by using the content of the specification and drawings of the present utility model, directly or indirectly applied in other related technical fields, is similarly within the scope of the patent protection of the present utility model.

Claims

1. An ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system, characterized in that: include: The core subnet cluster control system includes a central control node, radio reconnaissance and countermeasure subnodes, which are responsible for the human-machine interface interaction operations related to radio detection and countermeasure, radio bottom-level detection and countermeasure related parameter configuration, internal subnet communication, subnode control, subnode status detection query, system status monitoring, radar scanning and external communication; The ultra-wideband cluster radio frequency power amplification system includes a plurality of ultra-wideband radio frequency power amplification modules, which are used to amplify the power of the radio frequency signal output by each sub-node of the core subnet cluster control system to meet the requirements of long-distance radio cluster concurrent detection, countermeasures, penetration testing and analysis; NAS storage server, used to receive spectrum detection data of the central control node in the core subnet cluster control system, and realize the function of radio detection spectrum recorder; The core subnet cluster control system is communicatively connected with the ultra-wideband cluster radio frequency power amplification system and the NAS storage server respectively.

2. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 1, characterized in that: The central control node includes a CPU / MCU module unit, an LCD display module, an external PS / 2 keyboard, a VGA interface driver chip circuit, a CANFD driver circuit, an Ethernet driver circuit, an ADC voltage divider and IO detection circuit, an RTC clock circuit, a FLASH storage circuit, and a first power management module. The CPU / MCU module unit is communicatively connected with the LCD display module, the external PS / 2 keyboard, the VGA interface driver chip circuit, the CANFD driver circuit, the Ethernet driver circuit, the ADC voltage divider and IO detection circuit, the RTC clock circuit, and the FLASH storage circuit.

3. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 2, characterized in that: The rated input voltage of the first power management module is +5V and the output voltage is +3.3V, which is used to power the CPU / MCU module unit, LCD display module, external PS / 2 keyboard, VGA interface driver chip circuit, CANFD driver circuit, Ethernet driver circuit, ADC voltage divider and IO detection circuit, RTC clock circuit, and FLASH storage circuit.

4. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 2, characterized in that: The radio reconnaissance and countermeasure sub-node includes a wireless receiving link and a wireless sending link, and the wireless receiving link includes a first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit, a high-speed parallel accumulator circuit module, a high-speed DAC module, a high-speed FIFO receiving module, a high-speed hardware PLL phase-locked loop variable configuration demodulation module, a first MCU / CPU / ADC module, a first RS232 / UART interface circuit, a first TCP / IP Ethernet chip / circuit, a first external trigger circuit, an RX1 balun balancing circuit, a front-stage low-noise amplifier circuit, and an LED indication circuit. The first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit and the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the first MCU / CPU / ADC module, the first RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, the first external trigger circuit, the RX1 balun balancing circuit, the front-stage low-noise amplifier circuit, and the LED indication circuit. The CPU / ADC module and the RX1 balun balancing circuit are respectively communicatively connected, the high-speed DAC module is respectively communicatively connected with the high-speed parallel accumulator circuit module, the high-speed FIFO receiving module, and the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module is respectively communicatively connected with the first MCU / CPU / ADC module, the high-speed FIFO receiving module is communicatively connected with the first MCU / CPU / ADC module, the first MCU / CPU / ADC module is also communicatively connected with the first RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, the first external trigger circuit, and the LED indication circuit, and the RX1 balun balancing circuit is also communicatively connected with the pre-stage low-noise amplifier circuit.

5. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 4, characterized in that: The wireless transmission link includes a second high-performance zero-IF architecture wireless transceiver integrated chip circuit, a high-speed FIFO transmission module, a second MCU / CPU / ADC module, a second RS232 / UART interface circuit, a second TCP / IP Ethernet chip / circuit, a second external trigger circuit, a TX1 balun balancing circuit, a RF power amplifier module and a second power management module. The second high-performance zero-IF architecture wireless transceiver integrated chip circuit is communicatively connected to the high-speed FIFO transmission module, the second MCU / CPU / ADC module, and the TX1 balun balancing circuit respectively. The high-speed FIFO transmission module is communicatively connected to the second MCU / CPU / ADC module. The second MCU / CPU / ADC module is also communicatively connected to the second RS232 / UART interface circuit, the second TCP / IP Ethernet chip / circuit, and the second external trigger circuit respectively. The TX1 balun balancing circuit is also communicatively connected to the RF power amplifier module.

6. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 5, characterized in that: The rated input voltage of the second power management module is +5V, and the output voltages include +3.3V, +2.85V, +2.5V and +1.3V. +5V is used to power the high-speed parallel accumulator circuit module, the high-speed hardware PLL phase-locked loop variable configuration demodulation module, the first MCU / CPU / ADC module, the second MCU / CPU / ADC module, the front-stage low-noise amplifier circuit, and the RF power amplifier module. +3.3V is used to power the first high-performance zero-IF architecture wireless transceiver integrated chip circuit, the second high-performance zero-IF architecture wireless transceiver integrated chip circuit, the high-speed DAC module, the high-speed FIFO receiving module, and the high-speed FIFO receiving module. O sending module, the first RS232 / UART interface circuit, the second RS232 / UART interface circuit, the first TCP / IP Ethernet chip / circuit, and the second TCP / IP Ethernet chip / circuit are powered, +2.85V is used to power the first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit and the second high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit, +2.5V is used to power the high-speed FIFO receiving module and the high-speed FIFO sending module, and +1.3V is used to power the first high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit and the second high-performance zero intermediate frequency architecture wireless transceiver integrated chip circuit.

7. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 1, characterized in that: Each of the ultra-wideband radio frequency power amplification modules is connected to one of the radio reconnaissance and countermeasure sub-nodes.

8. The ultra-high-speed ultra-wideband radio cluster concurrent detection, analysis and countermeasure system according to claim 1, characterized in that: The spectrum detection data received by the NAS storage server includes the RSSI signal strength value of real-time dynamic scanning, the original data of detected radio baseband signals, real-time or triggered baseband decoding data, and various radio detection and countermeasure triggering events.

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