Portable HDMI signal special detector

Abstract

The utility model discloses a portable HDMI signal special-purpose detector comprising a power supply module, the power supply module is respectively connected with an FPGA board and an ARM board, and the FPGA board is connected with the ARM board; the FPGA board comprises an FPGA chip U1, and the FPGA chip U1 is connected with a first Flash, a first DDR3 storage medium, an AD acquisition module, a first crystal oscillator, a USB module and a UART; the AD acquisition module is connected with an HDMI (High Definition Multimedia Interface) input port; the ARM board comprises an ARM processor, and the ARM processor is connected with a network port, a second Flash, a second DDR3 storage medium, a second crystal oscillator and a capacitive touch screen; the ARM processor is connected with the USB module; the UART is connected with the ARM processor; detection and analysis of HDMI interface signal waveforms are realized based on the FPGA board and the ARM board, test requirements during transmission of HDMI signals among multimedia peripherals, handheld equipment and display equipment are met, and meanwhile, the detector adopts integrated arrangement of the FPGA board and the ARM board, so that the technical problems of complicated operation and difficulty in carrying during testing of HDMI equipment in the prior art are solved.

Description

Technical Field

[0001] The utility model belongs to the fields of digital signal detection and instruments, and relates to a detector, specifically a portable special detector for HDMI signals. Background Art

[0002] With the rapid development of digital multimedia technology, HDMI has become the most widely used audio and video transmission interface at present, and its application field is also constantly expanding. Due to the differences in display devices supporting HDMI functions, when an HDMI signal source is connected to a display device, a matching failure may occur, the display device cannot work properly, and it is very difficult to determine where the problem lies, which requires the detection and analysis of HDMI interface signals. At present, the main means of analyzing and detecting such high-frequency digital signals as HDMI is to use general signal testing instruments such as logic analyzers and oscilloscopes for testing. However, these instruments have problems such as high cost and difficulty in carrying, and at the same time, they also require high professional skills of testers in digital signal testing and other aspects. In addition, at the production and equipment installation and commissioning sites, due to the specifications and parameter limitations of HDMI interfaces, the testing process is relatively cumbersome when using these instruments for testing, and it is difficult to meet the testing requirements of the commissioning site. Content of the Utility Model

[0003] Aiming at the deficiencies of the existing technology, the purpose of the utility model is to provide a portable special detector for HDMI signals to solve the technical problems of complex operation and difficulty in carrying when testing HDMI devices in the existing technology.

[0004] To solve the above technical problems, the utility model is implemented by adopting the following technical solutions:

[0005] A portable special detector for HDMI signals includes a power supply module, the power supply module is respectively connected to an FPGA board and an ARM board, and the FPGA board and the ARM board are connected to each other;

[0006] The FPGA board includes an FPGA chip U1, a first Flash, a first DDR3 storage medium, an AD acquisition module, a first crystal oscillator, a USB module and a UART are connected to the FPGA chip U1; an HDMI input port is connected to the AD acquisition module;

[0007] The ARM board includes an ARM processor, a network port, a second Flash, a second DDR3 storage medium, a second crystal oscillator and a capacitive touch screen are connected to the ARM processor; the ARM processor is connected to the USB module; the UART is connected to the ARM processor.

[0008] The utility model further includes the following technical features:

[0009] The AD acquisition module includes five digital-to-analog converters and a common-mode rejection circuit respectively connected to the FPGA chip U1, and the digital-to-analog converters and the common-mode rejection circuit are respectively connected to the HDMI input.

[0010] The common-mode rejection circuit includes an operational amplifier Q, resistors R1, R2, R3, R4, R5, and R6. Among them, the positive input terminal of the operational amplifier Q is commonly connected to one end of the resistor R1 and one end of the resistor R3, and the second end of the resistor R1 is connected to the HDMI input; the second end of the resistor R3 is commonly connected to the fourth terminal of the operational amplifier Q and one end of the resistor R5;

[0011] The negative input terminal of the operational amplifier Q is commonly connected to one end of the resistor R2 and one end of the resistor R4, and the second end of the resistor R2 is connected to the HDMI input; the second end of the resistor R4 is commonly connected to the fifth terminal of the operational amplifier Q and one end of the resistor R6; the second ends of the resistor R5 and the resistor R6 are respectively connected to the FPGA chip U1.

[0012] The USB module circuit includes a USB chip U2, an EEPROM chip U3, a USB interface U4, resistors R172, R173, R174, R176, R177, R175, R178, capacitors C28, C29, C92, C31, C93, C66, C65, and a crystal oscillator Y4; among them, one end of the capacitor C28 is connected to the pin 2 of the EEPROM chip U3 and grounded, and the second end of the capacitor C28 is commonly connected to the pin 6 of the EEPROM chip U3, the pin 12, 24, 46 of the USB chip U2, one end of the resistor R172, one end of the resistor R173, one end of the resistor R174, one end of the resistor R177, one end of the resistor R178, and the first end of the power supply module. The second end of the resistor R172 is commonly connected to the pin 5 of the EEPROM chip U3 and the pin 45 of the USB chip U2. The second end of the R173 is commonly connected to the pin 4 of the EEPROM chip U3 and the pin 44 of the USB chip U2. The second end of the R174 is commonly connected to the pin 3 of the EEPROM chip U3, one end of the resistor R175, and the pin 43 of the USB chip U2; the second end of the resistor R175 is connected to the pin 1 of the EEPROM chip U3;

[0013] One end of the capacitor C29 is grounded, and the second end of the capacitor C29 is commonly connected to the pin 40 of the USB chip U2 and the second end of the power supply module; the pin 39 of the USB chip U2 is connected to the third end of the power supply module; one end of the capacitor C92 is connected to one end of the capacitor C30 and grounded, the second end of the capacitor C92 is connected to the pin 37 of the USB chip U2, and the second end of the capacitor C30 is connected to the pin 38 of the USB chip U2;

[0014] The pins 5, 6, 7, 8, 9 of the USB interface U4 are commonly connected and grounded at one end of the capacitor C31, and the second end of the capacitor C31 is commonly connected to the pin 1 of the USB interface U4 and the fourth end of the power supply module; the pin 4 of the USB interface U4 is floating; the pins 2, 3 of the USB interface U4 are respectively connected to the pins 6, 7 of the USB chip U2;

[0015] The second end of the resistor R177 is commonly connected to one end of the capacitor C93 and the pin 34 of the USB chip U2, the second end of the capacitor C93 is grounded, one end of the resistor R176 is grounded, and the second end of the resistor R176 is connected to the pin 5 of the USB chip U2;

[0016] The pin 2 of the crystal oscillator Y4 is connected to one end of the capacitor C66 and grounded, the second end of the capacitor C66 is commonly connected to the pin 3 of the crystal oscillator Y4 and the pin 2 of the USB chip U2; the pin 1 of the crystal oscillator Y4 is commonly connected to one end of the capacitor C65 and the pin 1 of the USB chip U2, and the second end of the capacitor C65 is connected to the pin 4 of the crystal oscillator Y4 and grounded;

[0017] The pins 42, 4, 9, 41, 10, 11, 22, 23, 35, 36, 47, 48 of the USB chip U2 are grounded, and the pin 31 of the USB chip U2 is connected to the second end of the resistor R178;

[0018] The pins 13 to 20 and the pins 21 to 30 of the USB chip U2 are respectively connected to the FPGA chip U1.

[0019] Compared with the prior art, the beneficial technical effects of the present utility model are:

[0020] The present utility model realizes the detection and analysis of the HDMI interface signal waveform based on the FPGA board and the ARM board, meets the test requirements when the HDMI signal is transmitted between the multimedia peripheral, the handheld device and the display device. At the same time, due to the integrated setting of the FPGA board and the ARM board, the detector has the advantages of high integration, light weight, small volume, low cost, convenient to carry and plug-and-play, and solves the technical problems of complex operation and difficult to carry when testing HDMI devices in the prior art. Description of the Drawings

[0021] Figure 1The overall structure diagram of the detector provided by the embodiment of the present utility model;

[0022] Figure 2 The structure diagram of the AD acquisition module of the present utility model;

[0023] Figure 3 The schematic diagram of the common-mode rejection circuit of the present utility model;

[0024] Figure 4 The RTL diagram for parsing the IIC protocol using FPGA provided by the present utility model;

[0025] Figure 5 The schematic diagram of the USB module circuit provided by the present utility model;

[0026] Figure 6 The schematic diagram of the test connection of the detector provided by the embodiment;

[0027] The following further elaborates on the specific content of the present utility model in conjunction with the embodiments. Specific implementation manners

[0028] It should be noted that all the components in the present utility model, without special instructions, are components known in the art.

[0029] The following gives specific embodiments of the present utility model. It should be noted that the present utility model is not limited to the following specific embodiments, and any equivalent transformation based on the technical solution of this application falls within the protection scope of the present utility model.

[0030] The present utility model provides a portable special detector for HDMI signals, as Figure 1 shown, including a power supply module, the power supply module is respectively connected to an FPGA board and an ARM board, and the FPGA board and the ARM board are connected;

[0031] The FPGA board includes an FPGA chip U1, on which a first Flash, a first DDR3 storage medium, an AD acquisition module, a first crystal oscillator, a USB module and a UART are connected; an HDMI input port is connected to the AD acquisition module;

[0032] The ARM board includes an ARM processor, on which a network port, a second Flash, a second DDR3 storage medium, a second crystal oscillator and a capacitive touch screen are connected; the ARM processor is connected to the USB module; the UART is connected to the ARM processor.

[0033] In the above technical solution, after power-on, the first Flash and the second Flash complete the power-on initialization of the FPGA and the ARM, and the human-computer interaction is carried out through the capacitive touch screen. Under the operation of the user, the ARM processor sends control commands to the FPGA chip through the UART interface. After receiving the commands, the FPGA chip controls the AD acquisition module to complete the data acquisition of a total of 8 signals, namely the integrated circuit bus (SDA, SCL), consumer electronics control (CEC), hot plug (HPD), 5V power supply (HDMI_5V), and enhanced audio return channel (eARC+, eARC-, eARCCOM) of the HDMI signal. In the FPGA, operations such as screening, encoding, bit-width conversion, and data splicing are performed on the acquired data, and the automatic parsing process of the IIC protocol for the SDA and SCL signals is completed. The processed and parsed data is stored in the first DDR3 storage medium. The data in the first DDR3 storage medium is sent back to the ARM processor through the USB module. After receiving the data, the ARM processor uses Qt Charts to plot it as a waveform and presents the detection result on the capacitive touch screen.

[0034] In the FPGA, operations such as screening, encoding, bit-width conversion, and data splicing on the acquired data are conventional operations in the art.

[0035] Qt Charts is a well-known drawing software.

[0036] Reference Figure 4 , referring to the RTL diagram of using the FPGA for IIC protocol parsing, the SDA and SCL signals acquired by the AD9629 are parsed using the FPGA. Among them, the sda and scl signal lines are the input of the acquired SDA and SCL signals respectively. Under the action of the 40Mhz clock signal clk_40, the SCL and SDA data are registered using scl_data[1:0] and sda_data[1:0]. The register i2c_on outputs a high level during the IIC communication, and finally, when negescl is true, the bits on the bus are registered using an 8-bit register. The data is stored using an external DDR3 storage medium, and the model is H5TQ2G63GFR-RDC.

[0037] Among them, the power module is powered by DC12V, and different amplitude voltages such as 5V, 3.3V, 2.5V, and 1.8V are output through the buck chip inside the power module for use by the ARM board, the FPGA board, and the devices on them.

[0038] The ARM board and the FPGA board complete communication through the UART and USB modules. In the ARM board, the host computer application software developed using Qt controls the FPGA board to perform data acquisition through the UART, receives the acquired data and protocol data through the USB module, and solidifies the design files through the Flash on the FPGA board and the ARM board.

[0039] Among them, the model of DDR3 is H5TQ2G63GFR-RDC; the models of the FPGA chip U1 and the ARM processor are XC7S75 and AM8618 respectively; the first crystal oscillator is 50Mhz, and the second crystal oscillator is 24Mhz.

[0040] The above solution realizes the detection and analysis of the HDMI interface signal waveform based on the FPGA board and the ARM board, meets the test requirements for HDMI signal transmission between multimedia peripherals, handheld devices and display devices. At the same time, due to the integrated setting of the FPGA board and the ARM board, this detector has the advantages of high integration, light weight, small volume, low cost, convenient to carry and plug-and-play, and solves the technical problems of complex operation and difficult to carry when testing HDMI devices in the prior art.

[0041] See Figure 2 , the AD acquisition module includes five digital-to-analog converters and a common-mode rejection circuit respectively connected to the FPGA chip U1, and the digital-to-analog converters and the common-mode rejection circuit are respectively connected to the HDMI input.

[0042] In the above technical solution, the HDMI signal source is input from the HDMI input port of the FPGA board and output from the HDMI output port. During this process, the AD acquisition module completes signal acquisition.

[0043] The models of the five digital-to-analog converters are all AD9629, and are respectively connected to the pins SDA, SCL, CEC, HPD and HDMI_5V of the HDMI input; among them, the common-mode rejection circuit differentially outputs and balances the voltages of the two pins eARC+ and eARC- of the HDMI interface, and then the FPGA directly completes the acquisition. The digital-to-analog converters are controlled by the FPGA to realize signal acquisition of the five pins SDA, SCL, CEC, HPD and HDMI_5V.

[0044] See Figure 3, the common-mode rejection circuit includes an operational amplifier Q, resistors R1, R2, R3, R4, R5, and R6. Among them, the non-inverting input terminal of the operational amplifier Q is commonly connected to one end of the resistor R1 and one end of the resistor R3. The second end of the resistor R1 is connected to the HDMI input; the second end of the resistor R3 is commonly connected to the fourth terminal of the operational amplifier Q and one end of the resistor R5; the inverting input terminal of the operational amplifier Q is commonly connected to one end of the resistor R2 and one end of the resistor R4. The second end of the resistor R2 is connected to the HDMI input; the second end of the resistor R4 is commonly connected to the fifth terminal of the operational amplifier Q and one end of the resistor R6; the second ends of the resistor R5 and the resistor R6 are respectively connected to the FPGA chip U1.

[0045] In the above technical solution, the differential-mode signals eARC+ and eARC- of the HDMI are input to the operational amplifier Q. The voltage gain is set by the external resistors R1 and R3 to complete the suppression of noise and interference and balance the differential output voltage for output to the FPGA (U1) to complete the acquisition of two differential signals.

[0046] The model of the operational amplifier Q is AD8138; the resistance values of the resistors R1, R2, R3, R4, R5, and R6 are 499Ω, 499Ω, 2.49KΩ, 2.49KΩ, 49.9Ω, and 49.9Ω;

[0047] See Figure 5 , the USB module circuit includes a USB chip U2, an EEPROM chip U3, a USB interface U4, resistors R172, R173, R174, R176, R177, R175, R178, capacitors C28, C29, C92, C31, C93, C66, C65, and a crystal oscillator Y4; among them, one end of the capacitor C28 is connected to the pin 2 of the EEPROM chip U3 and grounded. The second end of the capacitor C28 is commonly connected to the pin 6 of the EEPROM chip U3, the pin 12, 24, 46 of the USB chip U2, one end of the resistor R172, one end of the resistor R173, one end of the resistor R174, one end of the resistor R177, one end of the resistor R178, and the first end of the power supply module. The second end of the resistor R172 is commonly connected to the pin 5 of the EEPROM chip U3 and the pin 45 of the USB chip U2. The second end of the R173 is commonly connected to the pin 4 of the EEPROM chip U3 and the pin 44 of the USB chip U2. The second end of the R174 is commonly connected to the pin 3 of the EEPROM chip U3, one end of the resistor R175, and the pin 43 of the USB chip U2; the second end of the resistor R175 is connected to the pin 1 of the EEPROM chip U3;

[0048] One end of the capacitor C29 is grounded, and the second end of the capacitor C29 is commonly connected to the pin 40 of the USB chip U2 and the second end of the power supply module; the pin 39 of the USB chip U2 is connected to the third end of the power supply module; one end of the capacitor C92 is connected to one end of the capacitor C30 and grounded, the second end of the capacitor C92 is connected to the pin 37 of the USB chip U2, and the second end of the capacitor C30 is connected to the pin 38 of the USB chip U2;

[0049] The pins 5, 6, 7, 8, 9 of the USB interface U4 are commonly connected and grounded with one end of the capacitor C31, and the second end of the capacitor C31 is commonly connected to the pin 1 of the USB interface U4 and the fourth end of the power supply module; the pin 4 of the USB interface U4 is floating; the pins 2, 3 of the USB interface U4 are respectively connected to the pins 6, 7 of the USB chip U2;

[0050] The second end of the resistor R177 is commonly connected to one end of the capacitor C93 and the pin 34 of the USB chip U2, the second end of the capacitor C93 is grounded, one end of the resistor R176 is grounded, and the second end of the resistor R176 is connected to the pin 5 of the USB chip U2;

[0051] The pin 2 of the crystal oscillator Y4 is connected to one end of the capacitor C66 and grounded, the second end of the capacitor C66 is commonly connected to the pin 3 of the crystal oscillator Y4 and the pin 2 of the USB chip U2; the pin 1 of the crystal oscillator Y4 is commonly connected to one end of the capacitor C65 and the pin 1 of the USB chip U2, and the second end of the capacitor C65 is connected to the pin 4 of the crystal oscillator Y4 and grounded;

[0052] The pins 42, 4, 9, 41, 10, 11, 22, 23, 35, 36, 47, 48 of the USB chip U2 are grounded, and the pin 31 of the USB chip U2 is connected to the second end of the resistor R178;

[0053] The pins 13 to 20 and the pins 21 to 30 of the USB chip U2 are respectively connected to the FPGA chip U1.

[0054] In the above technical solution, the USB module circuit is used to complete the data exchange between the FPGA board and the ARM board, that is, the FPGA sends data to the ARM through the USB module, and the ARM completes the waveform drawing after receiving the data.

[0055] Among them, the EEPROM chip is used to store the configuration information of the USB chip U2 to make it work in the synchronous FIFO mode; U4 is a USB interface used to realize the data transmission between the USB module and the ARM processor; the crystal oscillator Y4 is used to provide the 12Mhz crystal oscillator required for the operation of the USB chip U2 to generate a clock; the bit width of the EEPROM chip must be 16 bits, and its power supply voltage is the same as the power supply voltages of the pins 12, 24, 46 of the USB chip, and it is used to store configuration information to make the USB chip U2 work in the synchronous FIFO mode.

[0056] The capacitor C29 is a voltage stabilizing capacitor, ensuring that the operating voltage of pin 40 of the USB chip is stably +5V; the USB interface U4 is directly connected to the ARM and completes data transmission through pins 2 and 3; the capacitor C31 is a voltage stabilizing capacitor, ensuring the stability of the input voltage of pin 1 of the USB interface U4 and enabling normal data driving; the resistor R177 and the capacitor C93 are connected to the reset pin 34 of the USB chip to stabilize the input 3.3V voltage and ensure that the USB chip can complete the reset normally; the capacitors C65 and C66 are matching capacitors between pin 1, pin 2 and the ground respectively, making the output 12Mhz clock reach the standard.

[0057] Among them, the models of the USB chip U2 and the EEPROM chip U3 are FT232HL and 93LC56BT-I / OT respectively; the USB interface U4 is a USB_SLAVE;

[0058] The resistance values of the resistors R172, R173, R174, R176, R177, R175 and R178 are 10KΩ, 10KΩ, 10KΩ, 12.1KΩ, 100KΩ, 2KΩ and 39KΩ respectively;

[0059] The capacitance values of the capacitors C28, C29, C31, C92, C31, C93, C66 and C65 are 100nF, 100nF, 100nF, 100nF, 10uF, 100nF, 27pF and 27pF.

[0060] Actual measurement example:

[0061] See Figure 6 , including any HDMI signal source device 1 that can generate HDMI signals, HDMI display device 2, HDMI cable 3, and the portable HDMI signal special detector 4 of the present utility model;

[0062] The test process is as follows: The HDMI signal source device 1 uses the HDMI cable 3 to insert into the HDMI input port of the portable HDMI signal special detector 4, and the HDMI display device 2 is connected to the HDMI output port of the portable HDMI signal special detector 4 through the HDMI cable 3, and the corresponding function is selected on the liquid crystal screen to complete the signal detection.

Claims

1. A portable HDMI signal detector, comprising a power module, characterized in that: The power module is respectively connected with an FPGA board and an ARM board, and the FPGA board and the ARM board are connected; The FPGA board includes an FPGA chip U1, and the FPGA chip U1 is connected to a first Flash, a first DDR3 storage medium, an AD acquisition module, a first crystal oscillator, a USB module and a UART; the AD acquisition module is connected to an HDMI input port; The ARM board comprises an ARM processor, to which a network port, a second Flash, a second DDR3 storage medium, a second crystal oscillator and a capacitive touch screen are connected; the ARM processor is connected to the USB module; and the UART is connected to the ARM processor.

2. The portable HDMI signal detector as claimed in claim 1, characterized in that: The AD acquisition module includes five digital-to-analog converters and a common-mode suppression circuit respectively connected to the FPGA chip U1 , and the digital-to-analog converter and the common-mode suppression circuit are respectively connected to the HDMI input.

3. The portable HDMI signal detector as claimed in claim 2, characterized in that: The common mode suppression circuit comprises an operational amplifier Q, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6, wherein the positive input terminal of the operational amplifier Q is commonly connected to one end of the resistor R1 and one end of the resistor R3, the second end of the resistor R1 is connected to the HDMI input; the second end of the resistor R3 is commonly connected to the fourth end of the operational amplifier Q and one end of the resistor R5; The reverse input terminal of the operational amplifier Q is commonly connected to one end of the resistor R2 and one end of the resistor R4, and the second end of the resistor R2 is connected to the HDMI input; the second end of the resistor R4 is commonly connected to the fifth end of the operational amplifier Q and one end of the resistor R6; the second end of the resistor R5 and the second end of the resistor R6 are respectively connected to the FPGA chip U1.

4. The portable HDMI signal detector as claimed in claim 1, characterized in that: The USB module circuit includes a USB chip U2, an EEPROM chip U3, a USB interface U4, a resistor R172, a resistor R173, a resistor R174, a resistor R176, a resistor R177, a resistor R175, a resistor R178, a capacitor C28, a capacitor C29, a capacitor C92, a capacitor C31, a capacitor C93, a capacitor C66, a capacitor C65 and a crystal oscillator Y4; wherein one end of the capacitor C28 is connected to the pin 2 of the EEPROM chip U3 and is grounded, and the second end of the capacitor C28 is connected to the pin 6 of the EEPROM chip U3, the pins 12, 24, 46 of the USB chip U2, the resistor R One end of resistor R172, one end of resistor R173, one end of resistor R174, one end of resistor R177, one end of resistor R178 and a first end of the power module are connected together, a second end of resistor R172 is connected together with pin 5 of EEPROM chip U3 and pin 45 of USB chip U2, a second end of R173 is connected together with pin 4 of EEPROM chip U3 and pin 44 of USB chip U2, a second end of R174 is connected together with pin 3 of EEPROM chip U3, one end of resistor R175 and pin 43 of USB chip U2; a second end of resistor R175 is connected to pin 1 of EEPROM chip U3; One end of the capacitor C29 is grounded, and the second end of the capacitor C29 is connected to the pin 40 of the USB chip U2 and the second end of the power module; the pin 39 of the USB chip U2 is connected to the third end of the power module; one end of the capacitor C92 is connected to one end of the capacitor C30 and grounded, the second end of the capacitor C92 is connected to the pin 37 of the USB chip U2, and the second end of the capacitor C30 is connected to the pin 38 of the USB chip U2; Pins 5, 6, 7, 8, and 9 of the USB interface U4 are connected to one end of the capacitor C31 and are grounded. The second end of the capacitor C31 is connected to pin 1 of the USB interface U4 and the fourth end of the power module. Pin 4 of the USB interface U4 is left floating. Pins 2 and 3 of the USB interface U4 are connected to pins 6 and 7 of the USB chip U2, respectively. The second end of the resistor R177 is connected to one end of the capacitor C93 and the pin 34 of the USB chip U2. The second end of the capacitor C93 is grounded. One end of the resistor R176 is grounded. The second end of the resistor R176 is connected to the pin 5 of the USB chip U2. Pin 2 of crystal oscillator Y4 is connected to one end of capacitor C66 and grounded, and the second end of capacitor C66 is connected to pin 3 of crystal oscillator Y4 and pin 2 of USB chip U2; Pin 1 of crystal oscillator Y4 is connected to one end of capacitor C65 and pin 1 of USB chip U2, and the second end of capacitor C65 is connected to pin 4 of crystal oscillator Y4 and grounded; Pins 42, 4, 9, 41, 10, 11, 22, 23, 35, 36, 47, and 48 of USB chip U2 are grounded, and pin 31 of USB chip U2 is connected to the second end of resistor R178; Pins 13 to 20 and pins 21 to 30 of the USB chip U2 are respectively connected to the FPGA chip U1.

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