Lora gateway

By designing a Lora gateway with a built-in TCP/IP, it uses microcontroller module, RS485 module, PHY circuit, RJ45 connector and power module to realize multiple TCP links, solving the problem that the existing Lora gateway can only establish one connection, and meeting the complex large-capacity networking needs.

CN223007651UActive Publication Date: 2025-06-20MAYAIR TECH (CHINA) CO LTD +1
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Patent Information

Application Number
CN202421953738.5
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-08-13
Publication Date
2025-06-20
Estimated Expiration
2034-08-13

AI Technical Summary

Technical Problem

The existing Lora gateways are integrated into one chip, and are not very autonomous, and can only establish one connection, which cannot meet the complex large-capacity networking needs.

Method used

A Lora gateway is designed, using a microcontroller module, RS485 module, PHY circuit, RJ45 connector and power module, and built-in TCP/IP ISO seven-layer model, and multiple TCP links are realized through the RS485 module and PHY circuit.

Benefits of technology

Through the built-in TCP/IP ISO seven-layer model, multiple TCP links are completed at the network layer and the transport layer, solving the problem of only one link being established, and achieving the concurrent processing capability of multi-frequency points and multiple channels.

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Abstract

The utility model discloses a Lora gateway comprising a single-chip microcomputer module, an RS485 module, a PHY circuit, an RJ45 connector and a power supply module. The single chip microcomputer module is electrically connected with the RS485 module and the PHY circuit, and is used for receiving and sending the serial port signal of the TTL level and transmitting and receiving parallel data through the RS485 module; an ISO seven-layer model of TCP / IP (Transmission Control Protocol / Internet Protocol) for multi-path TCP link is built in the single chip microcomputer module; the PHY circuit is used for receiving the parallel data sent by the single chip microcomputer, sequentially converting the parallel data into serial flow data, coded data and analog signals and then transmitting the serial flow data, the coded data and the analog signals to the RJ45 connector; the PHY circuit receives data sent by the RJ45 connector, converts the data into digital signals, decoding data and parallel data in sequence, and then sends the digital signals, the decoding data and the parallel data to the single-chip microcomputer module. The method has the advantages that through the ISO seven-layer model with the built-in TCP / IP, the link of multiple paths of TCP is completed in the network layer and the transmission layer.
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Description

Technical Field

[0001] The utility model relates to a LoRa gateway, belonging to the field of network technology. Background Art

[0002] The LoRa gateway, also known as the LoRa base station, is a gateway device that uses LoRa wireless modulation technology to achieve long-distance data transmission. The product is designed with an industrial-grade 32-bit dedicated network processor and a high-speed 4G wireless communication module, supports APN / VPDN wireless private networks, supports the LoRaWAN communication specification, supports GPS high-precision clock synchronization, has the concurrent processing ability of multiple frequency points and multiple channels, can meet the complex large-capacity networking requirements of industrial sites, and is mainly applied to multiple fields such as intelligent street lights, smart buildings, smart communities, and intelligent fire protection.

[0003] At present, for LoRa gateways on the market, the MAC and PHY are integrated in one chip. This solution is simple, but it has weak autonomy. Affected by the chip, only one connection can be established. Summary of the Invention

[0004] The technical problem to be solved by the utility model is to overcome the defects of the prior art and provide a LoRa gateway.

[0005] To solve the above technical problem, the utility model is implemented by the following technical solutions.

[0006] On the one hand, a LoRa gateway includes: a single-chip microcomputer module, an RS485 module, a PHY circuit, an RJ45 connector, and a power module;

[0007] The single-chip microcomputer module is electrically connected to the RS485 module and the PHY circuit respectively, and is used to receive and send serial port signals of TTL level through the RS485 module and transmit and receive parallel data; the single-chip microcomputer module internally has the ISO seven-layer model of TCP / IP for multiple TCP connections;

[0008] The PHY circuit is used to receive the parallel data sent by the single-chip microcomputer, and then convert the parallel data into serial stream data, coded data, and analog signals in sequence and transmit them to the RJ45 connector; the PHY circuit receives the data sent by the RJ45 connector, and converts it into digital signals, decoded data, and parallel data in sequence and then sends them to the single-chip microcomputer module.

[0009] Further, the parallel data is RMII data.

[0010] Further, it also includes: a 50MHz crystal oscillator, and the 50MHz crystal oscillator is electrically connected to the PHY circuit and is used to provide a unified operating frequency.

[0011] Furthermore, it also includes: a network transformer, wherein the network transformer is electrically connected between the PHY circuit and the RJ45 connector.

[0012] Furthermore, it also includes: an ESD protection module, wherein the ESD protection module is electrically connected between the network transformer and the RJ45 connector.

[0013] Furthermore, it also includes: a power supply module, which supplies power to the single-chip computer module, the RS485 module, the PHY circuit, the 50MHz crystal oscillator and the RJ45 connector.

[0014] Beneficial effects achieved by the utility model:

[0015] The utility model completes multi-channel TCP links at the network layer and the transport layer through the built-in ISO seven-layer model of TCP / IP, and can solve the problem that only one link can be established. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of a circuit module of the utility model;

[0017] Figure 2 This is a schematic diagram of the circuit structure adopted by the single chip microcomputer of the utility model;

[0018] Figure 3 It is a schematic diagram of the circuit structure of the PHY circuit of the utility model;

[0019] Figure 4 The utility model is a schematic diagram of the network transformer, ESD protection module and RJ45 circuit structure. DETAILED DESCRIPTION

[0020] The utility model is further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the utility model, and cannot be used to limit the protection scope of the utility model.

[0021] Embodiment 1, as Figure 1 As shown, this embodiment discloses a Lora gateway, including: a single-chip microcomputer module, an RS485 module, a PHY circuit, a 50MHz crystal oscillator and an RJ45;

[0022] The single-chip microcomputer module is electrically connected to the RS485 module and the PHY circuit, and is used to receive and send TTL-level serial port signals and transmit and receive RMII data through the RS485 module. Figure 2As shown in the figure, the single-chip microcomputer module in this embodiment specifically uses the STM32F407VET6 chip and its peripheral circuits; the single-chip microcomputer module is responsible for MAC, that is, Media Access Control, which is the media access control sub-layer protocol. This protocol is located in the lower half of the data link layer in the OSI seven-layer protocol and is mainly responsible for controlling and connecting to the physical medium of the physical layer, following the IEEE-802.3 Ethernet standard definition.

[0023] The PHY circuit is used to receive the RMII data sent by the single-chip microcomputer, then convert the parallel data into serial stream data, encode the data according to the encoding rules of the physical layer, and then convert the encoded data into an analog signal, which is transmitted to the RJ45 connector after passing through the network transformer; the PHY circuit receives the data sent by the RJ45, and after passing through the network transformer, it successively performs analog-to-digital conversion, decoding, and conversion of RMII data and then sends it to the single-chip microcomputer module, as Figure 3 As shown in the figure, in this embodiment, the PHY circuit uses the DP83848KSQ-10 / 100 chip and its peripheral circuits; the PHY is a physical interface transceiver that implements the physical layer. It is connected to the single-chip microcomputer through the RMII interface. RMII stands for "Reduced Media Independent Interface" and is an implementation in the IEEE-802.3u standard. When the PHY sends data, it receives the data from the MAC, then converts the parallel data into serial stream data, encodes the data according to the encoding rules of the physical layer, and then converts it into an analog signal to send the data out. The process is reversed when receiving data.

[0024] The 50MHz crystal oscillator is electrically connected to the PHY circuit and is used to provide a unified operating frequency;

[0025] The power supply module supplies power to the single-chip microcomputer module, RS485 module, PHY circuit, 50MHz crystal oscillator, and RJ45.

[0026] Embodiment 2: On the basis of Embodiment 1, a network transformer and an ESD protection module are successively arranged between the PHY circuit and the RJ45 connector; the PHY circuit is used to receive the RMII data sent by the single-chip microcomputer, then convert the parallel data into serial stream data, encode the data according to the encoding rules of the physical layer, and then convert the encoded data into an analog signal, which is transmitted to the RJ45 connector after passing through the network transformer; the PHY circuit receives the data sent by the RJ45, and after passing through the network transformer, it successively performs analog-to-digital conversion, decoding, and conversion of RMII data and then sends it to the single-chip microcomputer module, as Figure 3As shown, in this embodiment, the PHY circuit uses the DP83848KSQ-10 / 100 chip and its peripheral circuits; the PHY is a physical interface transceiver that implements the physical layer. It is connected to the single-chip microcomputer through the RMII interface. RMII stands for "Reduced Media Independent Interface" and is an implementation in the IEEE-802.3u standard. When the PHY sends data, it receives the data from the MAC, then converts the parallel data into a serial stream of data, encodes the data according to the encoding rules of the physical layer, and then sends the data out as an analog signal. The process is reversed when receiving data.

[0027] The network transformer consists of a differential-mode coil, a transformer, and a center tap: 1. Couples differential signals to make the anti-interference ability stronger; 2. The transformer isolates different levels of different devices at the network cable end and isolates DC signals.

[0028] The ESD protection module is electrically connected between the network transformer and the RJ45 for electrostatic protection, such as Figure 4 As shown, in this embodiment, the network transformer and the ESD protection module use the HX1198FNL chip and the TPD4E1U06DCK and their peripheral circuits respectively.

[0029] The power supply module supplies power to the single-chip microcomputer module, the RS485 module, the PHY circuit, the network transformer, the ESD protection module, the 50 MHz crystal oscillator, and the RJ45.

[0030] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and deformations can be made, and these improvements and deformations should also be regarded as the protection scope of the present invention.

Claims

1. A Lora gateway, characterized in that: include: MCU module, RS485 module, PHY circuit and RJ45 connector; The single-chip microcomputer module is electrically connected to the RS485 module and the PHY circuit, respectively, and is used to receive and send TTL-level serial port signals and transmit and receive parallel data through the RS485 module; the single-chip microcomputer module has a built-in ISO seven-layer model of TCP / IP for multi-channel TCP links; The PHY circuit is used to receive parallel data sent by the single-chip microcomputer, and then convert the parallel data into serial stream data, encoded data and analog signals in sequence before transmitting them to the RJ45 connector; the PHY circuit receives data sent by the RJ45 connector, converts them into digital signals, decoded data, parallel data in sequence before sending them to the single-chip microcomputer module.

2. The Lora gateway according to claim 1, characterized in that: The parallel data is RMII data.

3. The Lora gateway according to claim 1, characterized in that: Also includes: A 50 MHz crystal oscillator is electrically connected to the PHY circuit to provide a uniform operating frequency.

4. The Lora gateway according to claim 1, characterized in that: Also includes: A network transformer is electrically connected between the PHY circuit and the RJ45 connector.

5. The Lora gateway according to claim 4, characterized in that: Also includes: An ESD protection module is electrically connected between the network transformer and the RJ45 connector.

6. The Lora gateway according to claim 5, characterized in that: Also includes: A power supply module, wherein the power supply module supplies power to the single-chip microcomputer module, the RS485 module, the PHY circuit, the 50MHz crystal oscillator and the RJ45 connector.