Switch multiplexing semiconductor test equipment and test system
By introducing digital control loops and logic multiplexing switch modules into semiconductor testing equipment, multiplexing of test channels is achieved, solving the problem of limited test channels in the prior art, and meeting the testing needs of more scenarios.
Patent Information
- Application Number
- CN202421584900.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-04
- Publication Date
- 2025-06-24
- Estimated Expiration
- 2034-07-04
AI Technical Summary
The testing channels of existing semiconductor testing equipment are limited and cannot meet the testing needs of more scenarios.
A switch-multiplexed semiconductor test equipment is designed, using a digital control loop and a logic multiplexing switch module to realize multiplexing of test channels by controlling the access and switching of service boards.
Through the use of the logic multiplexing switch module, the multiplexing of test channels is achieved, the problem of limited number of test channels is solved, and the testing needs of more scenarios is met.
Smart Images
Figure CN223022312U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing, and particularly to a semiconductor testing device and a testing system with switch multiplexing. Background Art
[0002] Chip testing refers to using a semiconductor testing device to output test signals to detect various parameter indicators of a device under test, and eliminating defective products to control the ex-factory quality of semiconductor devices.
[0003] In the prior art, due to limited test channels in the semiconductor testing device, each test channel corresponds to a service board, so it is impossible to meet the test requirements of more scenarios. Summary of the Utility Model
[0004] Based on this, it is necessary to provide a semiconductor testing device and a testing system with switch multiplexing for the above technical problems.
[0005] In a first aspect, an embodiment of this application proposes a semiconductor testing device with switch multiplexing. The device includes a digital control loop, multiple service boards, and a logic multiplexing switch module. Each service board includes a service function module and a switching switch module connected to the service function module. Each service function module is connected to the digital control loop, each switching switch module is connected to the logic multiplexing switch module, and the logic multiplexing switch module is connected to the device under test; wherein,
[0006] The digital control loop outputs control signals to the logic multiplexing switch module and each switching switch module to control at least one of the multiple service boards to access, and form at least one test loop with the digital control loop and the device under test.
[0007] In some embodiments, the device further includes an internal calibration board, and the internal calibration board is connected to the logic multiplexing switch module;
[0008] The digital control loop outputs control signals to the logic multiplexing switch module and each switching switch module to control at least one of the multiple service boards to access and control the access of the internal calibration board, and form at least one calibration loop with the digital control loop.
[0009] In some embodiments, the logic multiplexing switch module includes a first multiplexing switch unit and a second multiplexing switch unit. A first switching end of the first multiplexing switch unit is connected to the internal calibration board, a second switching end is connected to the device under test, a common end is connected to one end of the second multiplexing switch unit, and the other end of the second multiplexing switch unit is connected to multiple switching switch modules.
[0010] In some embodiments, the device further includes an interface module, and the interface module is connected to the logic multiplexing switch module and the device under test.
[0011] In some embodiments, the first multiplexing switch unit includes a plurality of first multiplexing switches, the second multiplexing switch unit includes a plurality of second multiplexing switches, the first switching ends of the plurality of first multiplexing switches are respectively connected to the input ends of the internal calibration board, the second switching ends are respectively connected to the interfaces of the interface module, the common ends are respectively connected to one ends of the plurality of second multiplexing switches, and the other ends of the plurality of second multiplexing switches are respectively connected to a plurality of the switching switch modules.
[0012] In some embodiments, the internal calibration board and the logic multiplexing switch module are provided on the same backplane.
[0013] In some embodiments, the service boards in the plurality of test loops for parallel testing are provided on the same daughter board.
[0014] In some embodiments, the backplane is provided with plug-in connectors, and each daughter board is detachably connected to the backplane through the plug-in connectors.
[0015] In some embodiments, the plurality of service boards include multiple ones of a time parameter measurement board, an arbitrary waveform generator board, a high pulse current source board, a floating differential measurement board, and a signal parameter measurement board.
[0016] In some embodiments, the time parameter measurement board includes a time parameter measurement module and a first switching switch module connected to the time parameter measurement module, and the time parameter measurement module includes a first comparator and a gear switching circuit;
[0017] The digital control loop, the first comparator, the gear switching circuit, the first switching switch module, the logic multiplexing switch module, and the device under test are connected to form a time parameter measurement circuit.
[0018] In some embodiments, the arbitrary waveform generator board includes an arbitrary waveform generation module and a second switching switch module connected to the arbitrary waveform generation module, and the arbitrary waveform generation module includes a first differential amplifier and a second differential amplifier;
[0019] The digital control loop, the first differential amplifier, the second switching switch module, the logic multiplexing switch module, the device under test, and the second differential amplifier are connected to form a first negative feedback loop.
[0020] In some embodiments, the high pulse current source board includes a high pulse current source module and a third switching switch module connected to the high pulse current source module. The high pulse current source module includes a first error comparator, a first integrator, a first operational amplifier, and a third differential amplifier;
[0021] The digital control loop, the first error comparator, the first integrator, the first operational amplifier, and the third differential amplifier are connected to form a second negative feedback loop.
[0022] In some embodiments, the floating differential measurement board includes a floating differential measurement module and a fourth switching switch module connected to the floating differential measurement module. The floating differential measurement module includes a fourth differential amplifier;
[0023] The digital control loop, the first error comparator, the first integrator, the first operational amplifier, the third switching switch module, the logic multiplexing switch module, the device under test, the fourth switching switch module, and the fourth differential amplifier are connected to form a third negative feedback loop.
[0024] The digital control loop, the fourth differential amplifier, the fourth switching switch module, the logic multiplexing switch module, and the device under test are connected to form a floating differential measurement loop.
[0025] In some embodiments, the signal parameter measurement board includes a signal parameter measurement module and a fifth switching switch module connected to the signal parameter measurement module. The signal parameter measurement module includes a second error comparator, a second integrator, a second operational amplifier, a sampling resistor, a fifth differential amplifier, and a sixth differential amplifier;
[0026] The digital control loop, the second error comparator, the second integrator, the second operational amplifier, the sampling resistor, and the fifth differential amplifier are connected to form a fourth feedback loop;
[0027] The digital control loop, the second error comparator, the second integrator, the second operational amplifier, the sampling resistor, the fifth switching switch module, the logic multiplexing switch module, the device under test, and the sixth differential amplifier are connected to form a fifth feedback loop.
[0028] In a second aspect, an embodiment of the present application provides a test system, which includes a host computer and a switch-multiplexed semiconductor test device as described in the first aspect and communicatively connected to the host computer.
[0029] Compared with the prior art, in this technical solution, a control signal is output from a digital control loop to a logic multiplexing switch module and each switching switch module to control the access of at least one of multiple service boards, and at least one test loop is formed with the digital control loop and the device under test. The multiplexing of test channels can be realized by using the logic multiplexing switch module to solve the technical problem that the test requirements of more scenarios cannot be met due to the limitation of the number of test channels. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is a schematic structural diagram of a semiconductor test device with switch multiplexing in an embodiment of the present application;
[0031] Figure 2 It is a schematic overall structural diagram of a semiconductor test device with switch multiplexing in an embodiment of the present application;
[0032] Figure 3 It is a schematic specific structural diagram of a semiconductor test device with switch multiplexing in an exemplary embodiment of the present application;
[0033] Figure 4 It is a schematic structural diagram of a semiconductor test device with switch multiplexing in an exemplary embodiment of the present application.
[0034] Among them, 10, digital control loop; 20, service board; 30, logic multiplexing switch module; 40, device under test; 50, internal calibration board; 60, interface module; 210, service function module, 220, switching switch module. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0035] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application and are not used to limit the present application.
[0036] Obviously, the drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacturing or production changes based on the technical content disclosed in the present application are only conventional technical means and should not be understood that the content disclosed in the present application is insufficient.
[0037] References to "embodiments" in this application mean that specific features, structures, or characteristics described in connection with the embodiments can be included in multiple embodiments of this application. The phrase appears in various places in the specification and is not necessarily referring to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive of other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.
[0038] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the ordinary meaning understood by those of ordinary skill in the technical field to which this application pertains. The words "a", "one", "kind", "the", and similar words involved in this application do not denote a limitation of quantity and can represent singular or plural. The terms "include", "comprise", "have", and any variations thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may further include steps or units not listed, or may further include other steps or units inherent to these processes, methods, products, or devices. The words "connect", "be connected", "couple", and similar words involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.
[0039] As Figure 1 shown, an embodiment of this application further provides a semiconductor test device with switch multiplexing. The semiconductor test device with switch multiplexing includes a digital control loop 10, a plurality of service boards 20, and a logic multiplexing switch module 30. Each service board 20 includes a service function module 210 and a switching switch module 220 connected to the service function module 210. Each service function module 210 is connected to the digital control loop 10, each switching switch module 220 is connected to the logic multiplexing switch module 30, and the logic multiplexing switch module 30 is connected to the device under test 40; wherein, the digital control loop 10 outputs a control signal to the logic multiplexing switch module 30 and each switching switch module 220 to control at least one of the plurality of service boards 20 to access and form at least one test loop with the digital control loop 10 and the device under test 40.
[0040] The digital control loop 10 has an FPGA as the core device, and the peripheral devices include the FPGA power supply, clock, memory, I / O drive circuits for relays / analog switches, I / O expansion circuits, ADC SPI interfaces, DAC SPI interfaces, etc. The FPGA logic is implemented through logic code, and the development of service interfaces is achieved through interaction with the service board 20.
[0041] The multiple service boards 20 include, but are not limited to, multiple ones among a time parameter measurement board, an arbitrary waveform generator board, a high pulse current source board, a floating differential measurement board, and a signal parameter measurement board.
[0042] In this embodiment, a control signal is output from the digital control loop 10 to the logic multiplexing switch module 30 and each switching switch module 220 to control the access of at least one of the multiple service boards 20, and at least one test loop is formed with the digital control loop 10 and the device under test 40. The multiplexing of test channels can be realized by using the logic multiplexing switch module 30 to solve the technical problem that the test requirements of more scenarios cannot be met due to the limitation of the number of test channels.
[0043] In some embodiments, as Figure 2 shown, the semiconductor test equipment with switch multiplexing further includes an internal calibration board 50, and the internal calibration board 50 is connected to the logic multiplexing switch module 30; the digital control loop 10 outputs a control signal to the logic multiplexing switch module 30 and each switching switch module 220 to control the access of at least one of the multiple service boards 20 and the access of the internal calibration board 50, and at least one calibration loop is formed with the digital control loop 10.
[0044] In this embodiment, the multiplexing of calibration channels can be realized by using the logic multiplexing switch module 30 to solve the technical problem that the calibration requirements of more scenarios cannot be met due to the limitation of the number of calibration channels.
[0045] Parallel test loops can be generated between some of the service boards 20 through the logic multiplexing switch module 30. For example: the signal parameter measurement board and the time parameter measurement board / floating differential measurement board can work simultaneously; the high pulse current source board and the time parameter measurement board / floating differential measurement board can work simultaneously; the time parameter measurement board and the floating differential measurement board can work simultaneously.
[0046] The switching switch modules 220 of some service boards 20 can be made mutually exclusive to prevent incorrect operations. For example, the signal parameter measurement board and the high pulse current source board cannot work simultaneously, and their respective switching switch modules 220 are made mutually exclusive. Specifically, it can be the mutual exclusion design of the switching switch module 220 itself, or the control signal is output through the digital control loop 10 to control the switching switch module 220 of the corresponding service board 20, so as to make the respective switching switch modules 220 mutually exclusive and prevent incorrect operations. In some embodiments, as Figure 3 shown, the semiconductor test equipment with switch multiplexing further includes an interface module 60, and the interface module 60 is connected to the logic multiplexing switch module 30 and the device under test 40.
[0047] In some embodiments, the internal calibration board 50 and the logic multiplexing switch module 30 are arranged on the same backplane. The service boards 20 in multiple test loops for parallel testing are arranged on the same daughter board.
[0048] Exemplarily, the time parameter measurement board and the arbitrary waveform generator board are arranged on the same daughter board; the high pulse current source board and the floating differential measurement board are arranged on the same daughter board; the signal parameter measurement board is independently arranged on a daughter board.
[0049] Based on the above architecture, arranging the internal calibration board 50 and the logic multiplexing switch module 30 on the same backplane and arranging the service boards 20 in multiple test loops for parallel testing on the same daughter board can reduce the volume of the semiconductor test equipment. Further, the backplane is provided with plug-in connectors, and each daughter board is detachably connected to the backplane through the plug-in connectors.
[0050] Since the daughter board and the backplane are detachably connected, it is convenient to replace the daughter board to meet the test requirements of more scenarios.
[0051] Figure 4 FIG. is a schematic structural diagram of a semiconductor test equipment with switch multiplexing in an exemplary embodiment. The following will be described in detail with reference to Figure 4 this equipment.
[0052] In this exemplary embodiment, the semiconductor test equipment with switch multiplexing includes a time parameter measurement board, an arbitrary waveform generator board, a high pulse current source board, a floating differential measurement board, and a signal parameter measurement board.
[0053] The time parameter measurement board includes a time parameter measurement module and a first switching switch module connected to the time parameter measurement module. The time parameter measurement module includes a first comparator U1 and a gear switching circuit. The digital control loop 10, the first comparator U1, the gear switching circuit, the first switching switch module, the logic multiplexing switch module 30, and the device under test 40 are connected to form a time parameter measurement loop.
[0054] Specifically, the first comparator U1 includes high-speed comparators with their positive input terminals connected, and the negative input terminals of the corresponding high-speed comparators are connected to the high threshold voltage VOH and the low threshold voltage VOL respectively. The gear switching circuit includes a high-impedance input amplifier AP, a first resistor RS, switches K1 connected to the high-impedance input amplifier AP and the first resistor RS respectively, and a switch K2 connected to the positive input terminal and the output terminal of the high-impedance input amplifier AP, constituting a three-gear circuit switching. The first switching switch module includes switching switches TMU_HS and TMU_LS.
[0055] Specifically, as Figure 4 shown, one end of the first resistor RS is grounded, and the other end is connected to the moving contact of the switch K1. The static contact of the switch K1 is connected to the switching switch TMU_HS. The negative input terminal of the high-impedance input amplifier AP is grounded, the positive input terminal of the high-impedance input amplifier AP is connected to the switching switch TMU_HS, and the switch K2 is arranged between the output terminal of the high-impedance input amplifier AP and the switching switch TMU_HS, constituting a three-gear impedance input. Then, according to different signals to be measured input by the device under test 40 to the gear switching circuit, the output signal is input to the first comparator U1. After comparing with the high threshold voltage VOH and the low threshold voltage VOL, the first comparator U1 outputs a level signal, which is output to the digital control loop 10 to realize the measurement of the time parameters of the measured signal.
[0056] The arbitrary waveform generator board includes an arbitrary waveform generation module and a second switching switch module connected to the arbitrary waveform generation module. The arbitrary waveform generation module includes a first differential amplifier U2 and a second differential amplifier U3. The digital control loop 10, the first differential amplifier U2, the second switching switch module, the logic multiplexing switch module 30, the device under test 40, and the second differential amplifier U3 are connected to form a first negative feedback loop.
[0057] The second switching switch module includes switching switches HAWG_HF, HAWG_HS, and HAWG_LS.
[0058] The high-pulse current source board includes a high-pulse current source module and a third switching switch module connected to the high-pulse current source module. The high-pulse current source module includes a first error comparator U4, a first integrator U5, a first operational amplifier U6, and a third differential amplifier U7. The digital control loop 10, the first error comparator U4, the first integrator U5, the first operational amplifier U6, and the third differential amplifier U7 are connected to form a second negative feedback loop.
[0059] The third switching switch module includes switching switches HCU_HF and HCU_LF.
[0060] The floating differential measurement board card includes a floating differential measurement module and a fourth switching switch module connected to the floating differential measurement module. The floating differential measurement module includes a fourth differential amplifier U8. The digital control loop 10, the first error comparator U4, the first integrator U5, the first operational amplifier U6, the third switching switch module, the logic multiplexing switch module 30, the device under test 40, the fourth switching switch module, and the fourth differential amplifier U8 are connected to form a third negative feedback loop. The digital control loop 10, the fourth differential amplifier U8, the fourth switching switch module, the logic multiplexing switch module 30, and the device under test 40 are connected to form a floating differential measurement loop.
[0061] The fourth switching switch module includes switching switches FDMM_HS and FDMM_LS.
[0062] The signal parameter measurement board card includes a signal parameter measurement module and a fifth switching switch module connected to the signal parameter measurement module. The signal parameter measurement module includes a second error comparator U9, a second integrator U10, a second operational amplifier U11, a sampling resistor RL, a fifth differential amplifier U12, and a sixth differential amplifier U13. The digital control loop 10, the second error comparator U9, the second integrator U10, the second operational amplifier U11, the sampling resistor RL, and the fifth differential amplifier U12 are connected to form a fourth feedback loop. The digital control loop 10, the second error comparator U9, the second integrator U10, the second operational amplifier U11, the sampling resistor RL, the fifth switching switch module, the logic multiplexing switch module 30, the device under test 40, and the sixth differential amplifier U13 are connected to form a fifth feedback loop.
[0063] The fifth switching switch module includes switching switches PMU_HF, PMU_HS, and PMU_LS.
[0064] The internal calibration board card includes a seventh differential amplifier U14. The digital control loop 10, the seventh differential amplifier U14, the logic multiplexing switch module 30, and at least one service board card are connected to form an internal calibration loop.
[0065] It should be noted that the above-mentioned logic multiplexing switch module 30 is connected to the device under test 40 through an interface module.
[0066] DAC modules are provided at the input ends of the arbitrary waveform generator board card, the high pulse current source board card, the floating differential measurement board card, and the signal parameter measurement board card, and ACD modules are provided at the output ends.
[0067] The logic multiplexing switch module 30 includes a first multiplexing switch unit and a second multiplexing switch unit. The first switching end of the first multiplexing switch unit is connected to the internal calibration board 50, the second switching end is connected to the device under test 40 (connected through the interface module), and the common end is connected to one end of the second multiplexing switch unit. The other end of the second multiplexing switch unit is connected to multiple switching switch modules 220.
[0068] Specifically, the first multiplexing switch unit includes first multiplexing switches HF_K, HS_K, and LS_K, and the second multiplexing switch unit includes second multiplexing switches BHF_K, BHS_K, and BLS_K. The first switching ends of the first multiplexing switches HF_K, HS_K, and LS_K are respectively connected to three input ends (DCC_HF, DCC_SP, DCC_SM) of the internal calibration board 50, the second switching ends are respectively connected to three interfaces (HF, HS, LS) of the interface module 60, and the common ends are respectively connected to one ends of the second multiplexing switches BHF_K, BHS_K, and BLS_K, as well as the switching switches PMU_HF, PMU_HS, and PMU_LS in the signal parameter measurement board. The other end of the second multiplexing switch BHF_K is connected to the switching switch HAWG_HF in the arbitrary waveform generator board and the switching switch HCU_HF in the high pulse current source board. The other end of the second multiplexing switch BHS_K is connected to the switching switch TMU_HS in the time parameter measurement board, the switching switch HAWG_HS in the arbitrary waveform generator board, and the switching switch FDMM_HS in the high pulse current source board. The other end of the second multiplexing switch BLS_K is connected to the switching switch TMU_LS in the time parameter measurement board, the switching switch HAWG_LS in the arbitrary waveform generator board, and the switching switch FDMM_LS in the high pulse current source board.
[0069] When it is necessary to access the time parameter measurement board, it is necessary to close the switching switches TMU_HS, TMU_LS, and the second multiplexing switches BHS_K, BLS_K, and at the same time control the first multiplexing switches HS_K, LS_K to switch to the interface module 60. The time parameter measurement board detects the voltage waveforms of the interfaces HS, LS from the interface module 60, compares them with the threshold voltages (VOH, VLH) set by the first comparator, converts them into digital levels and sends them to the digital control loop 10 for processing to measure the time parameters of the signal waveforms, such as the cycle time, etc.
[0070] When it is necessary to connect to an arbitrary waveform generator board, the switching switches HAWG_HF, HAWG_HS, HAWG_LS, the second multiplexing switches BHF_K, BHS_K, BLS_K need to be closed. At the same time, control the first multiplexing switches HF_K, HS_K, LS_K to switch to the interface module 60. The arbitrary waveform generator board can output a voltage waveform. The voltage excitation is output to the interface HF of the interface module 60 through the switching switch HAWG_HF. The pressure difference between the interfaces HS and LS is collected through the switching switches HAWG_HS and HAWG_LS to construct a first negative feedback loop to adjust the output voltage so that the load is the output set value.
[0071] When it is necessary to connect to a high pulse current source board, the switching switches HCU_HF, HCU_LF, FDMM_HS, FDMM_LS, the second multiplexing switches BHF_K, BHS_K, BLS_K need to be closed. At the same time, control the first multiplexing switches HF_K, HS_K, LS_K to switch to the interface module 60. The high pulse current source board can output voltage or current pulses. The voltage or current excitation is output to the HF of the DUT through the switching switch HCU_HF. The switching switch HCU_LF serves as a return path. The pressure difference between the interfaces HS and LS is collected through the switching switches FDMM_HS and FDMM_LS to construct a negative feedback loop to adjust the output voltage so that the load is the output set value. When used as a voltage output, the high pulse current source board selects a partial circuit of the floating differential measurement board as the voltage loop, that is, the second negative feedback loop; when used as a current output, the high pulse current source board selects the cascaded circuit of the sampling resistor and the differential amplifier as the current loop, that is, the third negative feedback loop.
[0072] When it is necessary to connect to a floating differential measurement board, the switching switches FDMM_HS, FDMM_LS, the second multiplexing switches BHS_K, BLS_K need to be closed. At the same time, control the first multiplexing switches HS_K, LS_K to switch to the interface module 60. The floating differential measurement board detects the voltages from the interfaces HS and LS through the switching switches FDMM_HS and FDMM_LS to construct a floating differential measurement loop to measure the external input voltage.
[0073] When it is necessary to connect to a signal parameter measurement board, the switching switches PMU_HF, PMU_HS, PMU_LS need to be closed. At the same time, control the first multiplexing switches HF_K, HS_K, LS_K to switch to the interface module 60. The signal parameter measurement board has functions such as voltage application, voltage measurement, current application, and current measurement. The voltage or current excitation is output to the interface HF through the switching switch PMU_HF. The pressure difference between the interfaces HS and LS is collected through the switching switches PMU_HS and PMU_LS to construct a fourth feedback loop or a fifth feedback loop to adjust the output voltage so that the load is the output set value.
[0074] When it is necessary to access the internal calibration board 50, in addition to enabling the switching switch module 220 of a certain service board 20, it is also necessary to connect the first multiplexing switches HF_K, HS_K, and LS_K to the three input terminals DCC_HF, DCC_SP, and DCC_SM of the internal calibration board 50. The internal calibration board 50 provides functions of reference voltage, resistance load, and voltage acquisition. The input terminals DCC_HF, DCC_SP, and DCC_SM are connected to the first multiplexing switches HF_K, HS_K, and LS_K through the DCC bus to construct an internal calibration loop to selectively access a certain function of the channel to be calibrated.
[0075] Taking the voltage calibration verification of the signal parameter measurement board as an example, using an external multimeter, first calibrate the DC accuracy of the internal calibration board 50, including the reference voltage, resistance value, and voltage acquisition accuracy. Then, use the accuracy of the internal calibration board 50 as the measured value for the accuracy transfer of other service functions. Finally, close the switching switches PMU_HF, PMU_HS, and PMU_LS to output a voltage signal. The internal calibration board 50 measures the pressure difference between the input terminals DCC_SP and DCC_SM as the measured value to correct the deviation of the voltage output of the signal parameter measurement board.
[0076] In one embodiment, the embodiment of the present application proposes a test system, which includes a host computer and a semiconductor test device as described in the above embodiment that is communicatively connected to the host computer.
[0077] Since the test system includes the semiconductor test device with switch multiplexing in the above embodiment, it can solve the same technical problems and achieve the same technical effects, which will not be elaborated here.
[0078] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0079] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A switch multiplexing semiconductor test device, characterized in that: The device includes a digital control loop, a plurality of service boards and a logic multiplexing switch module, each of the service boards includes a service function module and a switching switch module connected to the service function module, each of the service function modules is connected to the digital control loop, each of the switching switch modules is connected to the logic multiplexing switch module, and the logic multiplexing switch module is connected to the device under test; wherein, The digital control loop outputs a control signal to the logic multiplexing switch module and each of the switching switch modules to control the access of at least one of the multiple service boards, and forms at least one test loop with the digital control loop and the device under test.
2. The switch multiplexing semiconductor test equipment according to claim 1, characterized in that: The device further comprises an internal calibration board, wherein the internal calibration board is connected to the logic multiplexing switch module; The digital control loop outputs a control signal to the logic multiplexing switch module and each of the switching switch modules to control the access of at least one of the multiple service boards and the access of the internal calibration board, forming at least one calibration loop with the digital control loop.
3. The switch multiplexing semiconductor test equipment according to claim 2, characterized in that: The logic multiplexing switch module includes a first multiplexing switch unit and a second multiplexing switch unit, the first switching end of the first multiplexing switch unit is connected to the internal calibration board, the second switching end is connected to the device under test, the common end is connected to one end of the second multiplexing switch unit, and the other end of the second multiplexing switch unit is connected to multiple switching switch modules.
4. The switch multiplexing semiconductor test equipment according to claim 3, characterized in that: The device further comprises an interface module, wherein the interface module is connected to the logic multiplexing switch module and the device under test.
5. The switch multiplexing semiconductor test equipment according to claim 4, characterized in that: The first multiplexing switch unit includes multiple first multiplexing switches, and the second multiplexing switch unit includes multiple second multiplexing switches. The first switching ends of the multiple first multiplexing switches are respectively connected to the input end of the internal calibration board, the second switching ends are respectively connected to the interface of the interface module, the common ends are respectively connected to one end of the multiple second multiplexing switches, and the other ends of the multiple second multiplexing switches are respectively connected to the multiple switching switch modules.
6. The switch multiplexing semiconductor test equipment according to claim 2, characterized in that: The internal calibration board and the logic multiplexing switch module are arranged on the same backplane.
7. The switch multiplexing semiconductor test equipment according to claim 6, characterized in that: The service boards in the multiple test loops tested in parallel are arranged on the same sub-board.
8. The switch multiplexing semiconductor test equipment according to claim 7, characterized in that: The backplane is provided with a plug-in connector, and each of the sub-boards is detachably connected to the backplane via the plug-in connector.
9. The switch multiplexing semiconductor test equipment according to claim 1, characterized in that: The multiple service boards include multiple boards selected from the group consisting of a time parameter measurement board, an arbitrary waveform generator board, a high pulse current source board, a floating differential measurement board, and a signal parameter measurement board.
10. The semiconductor testing device according to claim 9, characterized in that The time parameter measurement board includes a time parameter measurement module and a first switch module connected to the time parameter measurement module, and the time parameter measurement module includes a first comparator and a gear switching circuit; The digital control loop, the first comparator, the gear switching circuit, the first switching switch module, the logic multiplexing switch module, and the device under test are connected to form a time parameter measurement loop.
11. The semiconductor testing device according to claim 9, characterized in that The arbitrary waveform generator board includes an arbitrary waveform generating module and a second switching switch module connected to the arbitrary waveform generating module, and the arbitrary waveform generating module includes a first differential amplifier and a second differential amplifier; The digital control loop, the first differential amplifier, the second switching switch module, the logic multiplexing switch module, the device under test, and the second differential amplifier are connected to form a first negative feedback loop.
12. The semiconductor testing device according to claim 9, characterized in that The high pulse current source board includes a high pulse current source module and a third switch module connected to the high pulse current source module, and the high pulse current source module includes a first error comparator, a first integrator, a first operational amplifier, and a third differential amplifier; The digital control loop, the first error comparator, the first integrator, the first operational amplifier, and the third differential amplifier are connected to form a second negative feedback loop.
13. The semiconductor testing device according to claim 12, characterized in that The floating differential measurement board includes a floating differential measurement module and a fourth switch module connected to the floating differential measurement module, and the floating differential measurement module includes a fourth differential amplifier; The digital control loop, the first error comparator, the first integrator, the first operational amplifier, the third switching switch module, the logic multiplexing switch module, the device under test, the fourth switching switch module, and the fourth differential amplifier are connected to form a third negative feedback loop; The digital control loop, the fourth differential amplifier, the fourth switching switch module, the logic multiplexing switch module, and the device under test are connected to form a floating differential measurement loop.
14. The semiconductor testing device according to claim 9, characterized in that The signal parameter measurement board includes a signal parameter measurement module and a fifth switching switch module connected to the signal parameter measurement module; the signal parameter measurement module includes a second error comparator, a second integrator, a second operational amplifier, a sampling resistor, a fifth differential amplifier, and a sixth differential amplifier; The digital control loop, the second error comparator, the second integrator, the second operational amplifier, the sampling resistor, and the fifth differential amplifier are connected to form a fourth feedback loop; The digital control loop, the second error comparator, the second integrator, the second operational amplifier, the sampling resistor, the fifth switching switch module, the logic multiplexing switch module, the device under test, and the sixth differential amplifier are connected to form a fifth feedback loop.
15. A testing system, characterized in that: The system includes a host computer and a switch multiplexing semiconductor testing device as described in any one of claims 1 to 14, which is communicatively connected to the host computer.