Mainboard and electronic equipment

Abstract

Disclosed are a mainboard and an electronic device wherein the mainboard comprises: a target electronic unit comprising a first power receiving unit and a second power receiving unit; the first type management unit is arranged on one side of a first point on the edge of the target electronic unit, and the distance between the power supply terminal of the first power receiving unit and the first point is smaller than or equal to the distance between the power supply terminal of the first power receiving unit and any point on the edge of the target electronic unit except the first point; the first point and a power supply terminal of the first power receiving unit are arranged along a first direction, and the first type of management units are arranged along the first direction; and / or the second type management unit is arranged on one side of a second point on the edge of the target electronic unit, and the distance between the power supply terminal of the second power receiving unit and the second point is smaller than or equal to the distance between the power supply terminal of the second power receiving unit and any point on the edge of the target electronic unit except the second point. The second point and the power supply terminal of the second power receiving unit are arranged along a second direction, and the second type management unit is arranged along the second direction.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic information technology, and particularly to a main board and an electronic device. Background Art

[0002] The miniaturization and thinning design of the main board of an electronic device (such as a computer, a mobile phone, etc.) can not only meet the signal quality of high-speed signals, improve performance such as overclocking, but also reduce the occupied area of the main board, leaving more space for other functional components such as fans and batteries, thereby enhancing the product competitiveness. Currently, there is still room for improvement in the main board. Summary of the Utility Model

[0003] Embodiments of the present disclosure provide a main board, including:

[0004] A target electronic unit, including a first power receiving unit and a second power receiving unit;

[0005] A plurality of power management units, including one or more first type management units electrically connected to the first power receiving unit, and / or one or more second type management units electrically connected to the second power receiving unit;

[0006] Wherein, the first type management unit is disposed on one side of a first point on the edge of the target electronic unit, the distance between the power terminal of the first power receiving unit and the first point is less than or equal to the distance between the power terminal of the first power receiving unit and any point on the edge of the target electronic unit other than the first point, the first point and the power terminal of the first power receiving unit are arranged along a first direction, and the first type management unit is arranged along the first direction; and / or

[0007] The second type management unit is disposed on one side of a second point on the edge of the target electronic unit, the distance between the power terminal of the second power receiving unit and the second point is less than or equal to the distance between the power terminal of the second power receiving unit and any point on the edge of the target electronic unit other than the second point, the second point and the power terminal of the second power receiving unit are arranged along a second direction, and the second type management unit is arranged along the second direction.

[0008] In some embodiments, the number of power terminals of the first power receiving unit is multiple, and the sum of the distances between the multiple power terminals of the first power receiving unit and the first point is less than or equal to the distance between the multiple power terminals of the first power receiving unit and any point on the edge of the target electronic unit other than the first point; and / or

[0009] The number of power terminals of the second power receiving unit is multiple, and the sum of the distances between the multiple power terminals of the second power receiving unit and the second point is less than or equal to the sum of the distances between the multiple power terminals of the second power receiving unit and any point on the edge of the target electronic unit other than the second point.

[0010] In some embodiments, any edge of the target electronic unit is a curve and / or a straight line.

[0011] In some embodiments,

[0012] The first power receiving unit is a memory unit, and the second power receiving unit is a processor.

[0013] In some embodiments,

[0014] The power terminals of the first power receiving unit include a first terminal located in a first area and a second terminal located in a second area; the first type of management unit includes a first management unit and a second management unit; the first point includes a first sub-point and a second sub-point;

[0015] The first management unit, the first sub-point, and the first area are arranged along the first direction, and the distance between the first terminal and the first sub-point is less than or equal to the distance between the first terminal and any point on the edge of the target electronic unit other than the first sub-point. The first management unit is configured to provide a first interface voltage for the memory unit through the first terminal;

[0016] The second management unit, the second sub-point, and the second area are arranged along the first direction, and the distance between the second terminal and the second sub-point is less than or equal to the distance between the second terminal and any point on the edge of the target electronic unit other than the second sub-point. The second management unit is configured to provide a first core voltage for the memory unit through the second terminal.

[0017] In some embodiments,

[0018] The power terminals of the second power receiving unit include a third terminal located in a third area and a fourth terminal located in a fourth area; the second type of management unit includes a third management unit and a fourth management unit; the second point includes a third sub-point and a fourth sub-point;

[0019] The third management unit, the third sub-point, and the third area are arranged along the second direction, and the distance between the third terminal and the third sub-point is less than or equal to the distance between the third terminal and any point on the edge of the target electronic unit other than the third sub-point. The third management unit is configured to provide a second core voltage for the processor through the third terminal;

[0020] The fourth management unit, the fourth sub - point, and the fourth area are arranged along the second direction. The distance between the fourth terminal and the fourth sub - point is less than or equal to the distance between the fourth terminal and any point on the edge of the target electronic unit other than the fourth sub - point. The fourth management unit is configured to provide a second interface voltage to the processor through the fourth terminal.

[0021] In some embodiments, the power supply terminal of the second power - receiving unit further includes a fifth terminal located in a fifth area; the main board further includes: at least one oscillator disposed on at least one side of the target electronic unit;

[0022] The oscillator is disposed on one side of a third point on the edge of the target electronic unit. The third point and the fifth area are arranged along a third direction. The oscillators are arranged along the third direction, and the distance between the fifth terminal and the third point is less than or equal to the distance between the fifth terminal and any point on the edge of the target electronic unit other than the third point. The oscillator is configured to provide a clock signal to the processor through the fifth terminal.

[0023] In some embodiments, the main board further includes: a plurality of first capacitors and a plurality of first inductors. The plurality of first capacitors and the plurality of first inductors are disposed on at least one side of the target electronic unit and are distributed between the target electronic unit and the power management unit.

[0024] In some embodiments, the target electronic unit and the plurality of power management units are located in a target area of the main board. The plurality of power management units are distributed on both sides of the target electronic unit in the first direction. The length of the target area extending along the first direction ranges from 65 mm to 70 mm, and the length extending in a direction perpendicular to the first direction ranges from 38 mm to 40 mm.

[0025] The present disclosure further provides an electronic device, the electronic device includes a main board, and the main board includes:

[0026] A target electronic unit, including a first power - receiving unit and a second power - receiving unit;

[0027] A plurality of power management units, including one or more first - type management units electrically connected to the first power - receiving unit, and / or one or more second - type management units electrically connected to the second power - receiving unit;

[0028] Among them, the first type of management unit is disposed on one side of a first point on the edge of the target electronic unit, the distance between the power terminal of the first power receiving unit and the first point is less than or equal to the distance between the power terminal of the first power receiving unit and any point on the edge of the target electronic unit other than the first point, the first point and the power terminal of the first power receiving unit are arranged along a first direction, and the first type of management unit is arranged along the first direction; and / or,

[0029] The second type of management unit is disposed on one side of a second point on the edge of the target electronic unit, the distance between the power terminal of the second power receiving unit and the second point is less than or equal to the distance between the power terminal of the second power receiving unit and any point on the edge of the target electronic unit other than the second point, the second point and the power terminal of the second power receiving unit are arranged along a second direction, and the second type of management unit is arranged along the second direction. Description of the Drawings

[0030] Figure 1 Schematic structural diagram of a main board provided by an embodiment of the present disclosure;

[0031] Figure 2 Schematic structural diagram of a main board provided by another embodiment of the present disclosure;

[0032] Figure 3 Schematic structural diagram of a main board provided by still another embodiment of the present disclosure;

[0033] Figure 4 Different examples of the shape of the target electronic unit provided by an embodiment of the present disclosure;

[0034] Figures 5a to 5b Schematic structural diagram of a main board provided by yet another embodiment of the present disclosure;

[0035] Figure 6 Schematic block diagram of a main board provided by an embodiment of the present disclosure;

[0036] Figure 7 Schematic block diagram of an electronic device provided by an embodiment of the present disclosure. Detailed Description of the Embodiments

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will further describe the specific technical solutions of the invention in detail with reference to the accompanying drawings in the embodiments of the present disclosure. The following embodiments are used to illustrate the present disclosure but are not intended to limit the scope of the present disclosure.

[0038] The miniaturization and thinning design of the main board of electronic devices (such as computers, mobile phones, etc.) can not only meet the signal quality of high-speed signals, improve performance such as overclocking, but also reduce the occupied area of the main board, leaving more space for functional components such as fans or batteries, thereby improving battery performance and the overall thermal performance of the machine, reducing the cost of the main board, and enhancing the competitiveness of the product. Currently, there is still room for improvement in the main board design.

[0039] Based on this, the following technical solutions of the embodiments of the present disclosure are proposed: The present disclosure provides a main board, including: a target electronic unit, including a first power receiving unit and a second power receiving unit; a plurality of power management units, including one or more first type management units electrically connected to the first power receiving unit, and / or one or more second type management units electrically connected to the second power receiving unit; wherein, the first type management units are arranged on one side of a first point on the edge of the target electronic unit, the distance between the power terminal of the first power receiving unit and the first point is less than or equal to the distance between the power terminal of the first power receiving unit and any point other than the first point on the edge of the target electronic unit, the first point and the power terminal of the first power receiving unit are arranged along a first direction, and the first type management units are arranged along the first direction; and / or, the second type management units are arranged on one side of a second point on the edge of the target electronic unit, the distance between the power terminal of the second power receiving unit and the second point is less than or equal to the distance between the power terminal of the second power receiving unit and any point other than the second point on the edge of the target electronic unit, the second point and the power terminal of the second power receiving unit are arranged along a second direction, and the second type management units are arranged along the second direction.

[0040] In this way, the distance between the first type management units and the power terminals of the first power receiving unit is minimized, and / or the distance between the second type management units and the power terminals of the second power receiving unit is minimized, thereby reducing the complexity and length of the wiring between the first type management units and the power terminals of the first power receiving unit, and / or the complexity and length of the wiring between the second type management units and the power terminals of the second power receiving unit, thereby reducing the area and cost of the main board and improving the performance of the whole machine. Moreover, since the first type management units and / or the second type management units are respectively close to the power terminals of the first power receiving unit and / or the second power receiving unit, the power transmission path can be reduced, thereby reducing resistance and inductance, improving power transmission efficiency, reducing energy loss, and also helping to reduce electromagnetic interference to other electronic components and improve the stability of the system. Also, the power management units being close to the power receiving units they manage helps to concentrate heat, facilitating heat dissipation design and improving the thermal management of the entire system.

[0041] Next, Figures 1 to 7 a further detailed description will be given of the main board provided by the embodiments of the present disclosure. Among them, Figure 5a the Figure 5b memory unit and the processor in

[0042] are omitted.Figure 1 As shown, the present disclosure provides a main board 1, including: a target electronic unit 10, including a first power receiving unit 21 and a second power receiving unit 22; a plurality of power management units 15, including one or more first type management units 151 electrically connected to the first power receiving unit 21, and / or one or more second type management units 152 electrically connected to the second power receiving unit 22; wherein, the first type management unit 151 is disposed on one side of a first point O1 on the edge of the target electronic unit 10, the distance between the power terminal 13 of the first power receiving unit 21 and the first point O1 is less than or equal to the distance between the power terminal 13 of the first power receiving unit 21 and any point on the edge of the target electronic unit 10 other than the first point O1, the first point O1 and the power terminal 13 of the first power receiving unit 21 are arranged along a first direction, and the first type management unit 151 is arranged along the first direction; and / or, the second type management unit 152 is disposed on one side of a second point O2 on the edge of the target electronic unit 10, the distance between the power terminal 14 of the second power receiving unit 22 and the second point O2 is less than or equal to the distance between the power terminal 14 of the second power receiving unit 22 and any point on the edge of the target electronic unit 10 other than the second point O2, the second point O2 and the power terminal 14 of the second power receiving unit 22 are arranged along a second direction, and the second type management unit 152 is arranged along the second direction.

[0043] Here, the main board 1 can be understood as the main board of an electronic device. For example, the main board of a mobile phone, the main board of a computer (such as a tablet computer, a laptop computer, etc.), the main board of a smart speaker, etc., which are not specifically limited in the present disclosure.

[0044] The target electronic unit 10 can be understood as an electronic unit with a specific function in an electronic device. The target electronic unit 10 may include one or more electronic units, and the multiple electronic units can cooperate to achieve the function of the target electronic unit 10. In some embodiments, the target electronic unit 10 may include a system on chip (SOC), which means integrating a system on a single chip, and the first power receiving unit 21 and the second power receiving unit 22 are integrated on a single chip. However, it is not limited thereto. The target electronic unit 10 may also include a network on chip (NOC), a multi-processor system on chip (MPSOC), a multi-chip module (MCM), a system in package (SiP), etc.

[0045] The first power receiving unit 21 and the second power receiving unit 22 can be two identical or different power demand units in the target electronic unit 10, and the first power receiving unit 21 and the second power receiving unit 22 can have the same or different voltage or current requirements. In some embodiments, the first power receiving unit 21 can include a memory, a processor, an analog circuit, a digital circuit, a communication module, etc., and the second power receiving unit 22 can also include a memory, a processor, an analog circuit, a digital circuit, a communication module, etc.; the memory can include a read-only memory (ROM) and a random access memory (RAM), and the random access memory can include a dynamic random access memory (DRAM) and a static random access memory (SRAM); the processor can include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), etc., and the processor can be a single-core processor or a multi-core processor; the digital circuit can include, such as a logic circuit, a digital signal processor, etc.; the analog circuit can include, such as an amplifier, a sensor interface, etc.; the communication module can include a Wi-Fi module, a Bluetooth module, etc.; this is not limited herein.

[0046] The power management unit 15 can be a chip that plays a role in power conversion, distribution, detection, and other power management in an electronic device. The first type of power management unit 151 is electrically connected to the first power receiving unit 21 for supplying power to the first power receiving unit 21, and the second type of power management unit 152 is electrically connected to the second power receiving unit 22 for supplying power to the second power receiving unit 22.

[0047] The target electronic unit 10 can be connected to the main board 1 through various terminals, such as pads, pins, etc. Each module on the target electronic unit 10 has corresponding terminals connected to the main board 1. For example, both the first power receiving unit 21 and the second power receiving unit 22 have power terminals, which are respectively connected to the main board 1 and are connected to the corresponding power management unit 15 through the traces on the main board 1.

[0048] In some embodiments, the power supply terminal 13 of the first power receiving unit 21 and the power supply terminal 14 of the second power receiving unit 22 may be disposed on the side of the target electronic unit 10 close to the main board 1. The first type of management unit 151 is electrically connected to the power supply terminal 13 of the first power receiving unit 21 to supply power to the first power receiving unit 21, and the second type of management unit 152 is electrically connected to the power supply terminal 14 of the second power receiving unit 22 to supply power to the second power receiving unit 22.

[0049] In the embodiments of the present disclosure, the setting position of the first type of power management unit 151 may be related to the setting position of the power supply terminal 13 of the first power receiving unit 21, and the setting position of the second type of power management unit 152 may be related to the setting position of the power supply terminal 22 of the second power receiving unit 22.

[0050] As Figure 1 shown, in some embodiments, there may be a first point O1 on the edge of the target electronic unit 10. The distance between the power supply terminal 13 of the first power receiving unit 21 and the first point O1 is less than the distance between the power supply terminal 13 of the first power receiving unit 21 and any other point on the edge of the target electronic unit 10 except the first point O1. In this case, the distance between the power supply terminal 13 of the first power receiving unit 21 and the first point O1 is the shortest. The first type of management unit 151 may be disposed on one side of the first point O1, and the first type of management unit 151, the first point O1, and the power supply terminal 13 of the first power receiving unit 21 are arranged along the first direction.

[0051] As Figure 2 shown, in some embodiments, the number of the first points O1 may be multiple. The distances between the power supply terminal 13 of the first power receiving unit 21 and the multiple first points O1 are equal, and the distance between the power supply terminal 13 of the first power receiving unit 21 and any one of the first points O1 is less than the distance between the power supply terminal 13 of the first power receiving unit 21 and any other point on the edge of the target electronic unit 10 except the multiple first points O1. In this case, the first type of management unit 151 may be disposed on one side of any one of the first points O1. Here, the multiple first points O1 may be located on the same side or different sides of the edge of the target electronic unit 10.

[0052] However, it is not limited thereto. In some other embodiments, the distance between the power supply terminal 13 of the first power receiving unit 21 and the first point O1 may also be equal to the distance between the power supply terminal 13 of the first power receiving unit 21 and any other point on the edge of the target electronic unit 10 except the first point O1. For example, when the shape of the target electronic unit 10 is circular and the power supply terminal 13 of the first power receiving unit 21 is located at the center position of the target electronic unit 10, the distances between the power supply terminal 13 of the first power receiving unit 21 and any point on the edge of the target electronic unit 10 are equal. In this case, the first type of management unit 151 may be disposed on one side of any point on the edge of the target electronic unit 10.

[0053] As shown Figure 1 In some embodiments, as shown, a second point O2 may exist on the edge of the target electronic unit 10. The distance between the power supply terminal 14 of the second power receiving unit 22 and the second point O2 is less than the distance between the power supply terminal 14 of the second power receiving unit 22 and any point other than the second point O2 on the edge of the target electronic unit 10. In this case, the distance between the power supply terminal 14 of the second power receiving unit 22 and the second point O2 is the shortest. The second type of management unit 152 may be disposed on one side of the second point O2, and the second type of management unit 152, the second point O2, and the power supply terminal 14 of the second power receiving unit 22 are arranged along the second direction.

[0054] As shown Figure 2 In some embodiments, as shown, the number of the second points O2 may be multiple. The distances between the power supply terminal 14 of the second power receiving unit 22 and the multiple second points O2 are equal, and the distance between the power supply terminal 14 of the second power receiving unit 22 and any one of the second points O2 is less than the distance between the power supply terminal 13 of the second power receiving unit 22 and any point other than the multiple second points O2 on the edge of the target electronic unit 10. In this case, the first type of management unit 151 may be disposed on one side of any one of the second points O2. Here, the multiple second points O2 may be located on the same side or different sides of the target electronic edge 10.

[0055] However, it is not limited thereto. In some other embodiments, the distance between the power supply terminal 14 of the second power receiving unit 22 and the second point O2 may also be equal to the distance between the power supply terminal 14 of the second power receiving unit 22 and any point other than the second point O2 on the edge of the target electronic unit 10. For example, when the shape of the target electronic unit 10 is circular and the power supply terminal 14 of the second power receiving unit 22 is located at the center position of the target electronic unit 10, the distances between the power supply terminal 14 of the second power receiving unit 22 and any point on the edge of the target electronic unit 10 are equal. In this case, the first type of management unit 151 may be disposed on one side of any point on the edge of the target electronic unit 10.

[0056] Here, both the first direction and the second direction may be directions parallel to the plane of the main board 1, and the first direction and the second direction may be perpendicular, obliquely intersecting, the same, or opposite.

[0057] As shown Figure 3As shown, in some embodiments, the number of power terminals 13 of the first power receiving unit 21 may be multiple, and the sum of the distances between the multiple power terminals 13 of the first power receiving unit 21 and the first point O1 is less than or equal to the sum of the distances between the multiple power terminals 13 of the first power receiving unit 21 and any point on the edge of the target electronic unit 10 other than the first point O1; and / or, the number of power terminals 14 of the second power receiving unit 22 may be multiple, and the sum of the distances between the multiple power terminals 14 of the second power receiving unit 22 and the second point O2 is less than or equal to the sum of the distances between the multiple power terminals 14 of the second power receiving unit 22 and any point on the edge of the target electronic unit 10 other than the second point O2.

[0058] The edge of the target electronic unit 10 refers to the contour line of the target electronic unit 10, which is used here to facilitate the description of the positional relationship between the target electronic unit 10 and the power management unit 15, etc. The target electronic unit 100 may include one or more edges, and the one or more edges are connected end to end to form the edge contour of the target electronic unit 10; among them, the edge of the target electronic unit 10 can be regarded as a figure formed by a set of countless points, and any point on the edge of the target electronic unit 10 refers to any one of the countless points, and any point on the edge of the target electronic unit 10 other than the first point O1 refers to any one of the other points among the countless points other than the first point O1, and any point on the edge of the target electronic unit 10 other than the second point O2 refers to any one of the other points among the countless points other than the second point O2.

[0059] In some embodiments, any edge of the target electronic unit 10 may be a curve and / or a straight line. For example, the edge of the target electronic unit 10 may be composed of one or more curves, or may be composed of multiple straight lines, or may be composed of at least one straight line and at least one curve.

[0060] Figure 1 The shape of the target electronic unit 10 shown in is a rectangle, and the edge of the target electronic unit 10 may be composed of 4 straight lines. It should be understood that Figure 1 is not used to limit the shape of the target electronic unit 10, such as Figure 4 shown, in other embodiments, the shape of the target electronic unit 10 may also be various shapes such as a circle, an ellipse, a triangle, a polygon, and an irregular shape that can be formed by multiple points.

[0061] In the embodiments of the present disclosure, the first type of management unit 151 is used to supply power to the first power receiving unit 21, and the second type of management unit 152 is used to supply power to the second power receiving unit 22. In this way, compared with using a single power management unit to supply power to the first power receiving unit 21 and the second power receiving unit 22 simultaneously, a flexible layout of the power management unit 15 can be achieved. At the same time, in the embodiments of the present disclosure, the first type of management unit 151 is arranged on one side of the first point O1 along the first direction, and the power terminals 13 of the first type of management unit 151, the first point O1, and the first power receiving unit 21 are arranged along the first direction, so as to minimize the distance between the first type of management unit 151 and the power terminal 13 of the first power receiving unit 21, and / or the second type of management unit 152 is arranged on one side of the second point O2 along the second direction, and the power terminals 14 of the second type of management unit 152, the second point O2, and the second power receiving unit 22 are arranged along the second direction, so as to minimize the distance between the second type of management unit 152 and the power terminal 14 of the second power receiving unit 22, thereby reducing the complexity and length of the wiring between the first type of management unit 151 and the power terminal 13 of the first power receiving unit 21, and / or the complexity and length of the wiring between the second type of management unit 152 and the power terminal 14 of the second power receiving unit 22, thereby reducing the area and cost of the main board 1 and improving the performance of the whole machine.

[0062] At the same time, since the first type of management unit 151 and / or the second type of management unit 152 are respectively close to the power terminals of the first power receiving unit 21 and / or the second power receiving unit 22, the power transmission path can be reduced, thereby reducing the resistance and inductance, improving the power transmission efficiency, reducing the energy loss, and also helping to reduce the electromagnetic interference to other electronic components and improve the stability of the system. In addition, the power management unit 15 is close to the power receiving unit it manages, which also helps to concentrate the heat, facilitate the heat dissipation design, and improve the thermal management of the whole system.

[0063] Figures 1 to 3The number of the first type of management units 151 and the number of the second type of management units 152 shown are both 1. However, this is not limited thereto. The number of the first type of management units 151 can also be multiple, such as 2, 3, 4, 5, etc. Multiple first type of management units 151 are used to supply power to the first power receiving unit 21 simultaneously. Any first type of management unit 151, the corresponding first point O1, and the power supply terminal 13 of the first power receiving unit 21 electrically connected thereto are arranged along the first direction, and for different first type of management units 151, the first direction can be the same or different; the number of the second type of management units 152 can also be multiple, such as 2, 3, 4, 5, etc. Multiple second type of management units 152 are used to supply power to the second power receiving unit 22 simultaneously. Any second type of management unit 152, the corresponding second point O2, and the power supply terminal 14 of the second power receiving unit 22 electrically connected thereto are arranged along the second direction, and for different second type of management units 152, the second direction can be the same or different.

[0064] The following describes the cases where the number of the first type of management units 151 is multiple and / or the number of the second type of management units 152 is multiple in combination with specific embodiments.

[0065] As Figure 5a and Figure 5b shown, in some embodiments, the first power receiving unit 21 can be a memory unit 11, and the second power receiving unit 22 can be a processor 12. Among them, the processor 12 can be the core component for data processing and control of the electronic device, and the memory unit 11 can be used to temporarily store the operation data in the processor 12 and the data exchanged with external memories such as hard disks. The memory unit 11 can include double data rate synchronous dynamic random access memory (DDR) or low power memory (LPDDR), such as one or more of DDR2, DDR3, DDR4, LPDDR5, etc.; the processor 12 can be a central processing unit (CPU), and the central processing unit can be a single-core processor or a multi-core processor.

[0066] As Figure 5a shown, in some embodiments, the power supply terminal 13 of the first power receiving unit 21 can include a first terminal P1 located in the first area 101 and a second terminal P2 located in the second area 102; the first type of management unit 151 can include a first management unit 161 and a second management unit 162; the first point O1 can include a first sub-point O11 and a second sub-point O12.

[0067] In some embodiments, the first management unit 161, the first sub - point O11, and the first area 101 are arranged along the first direction. The distance between the first terminal P1 and the first sub - point O11 is less than or equal to the distance between the first terminal P1 and any point on the edge of the target electronic unit 10 other than the first sub - point O11. The first management unit 161 can be used to provide a first interface voltage for the memory unit 11 through the first terminal P1; the second management unit 162, the second sub - point O12, and the second area 102 are arranged along the first direction. The distance between the second terminal P2 and the second sub - point O12 is less than or equal to the distance between the second terminal P2 and any point on the edge of the target electronic unit 10 other than the second sub - point O12. The second management unit 162 can be used to provide a first core voltage for the memory unit 11 through the second terminal P2.

[0068] Here, the first core voltage can be the power supply voltage of the memory unit 11, such as VDD, VSS, GND, etc. The second management unit 162 is electrically connected to the second terminal P2 to provide the first core voltage for the memory unit 11; the first interface voltage can be any other different power supply voltage of the memory unit 11 other than the first core voltage, such as VDD2H, VDD2L, VSSL, etc. The first management unit 161 is electrically connected to the first terminal P1 to provide the first interface voltage for the memory unit 11.

[0069] In some embodiments, the number of the first terminals P1 can be multiple. The sum of the distances between the multiple first terminals P1 and the first sub - point O11 is less than or equal to the sum of the distances between the multiple first terminals P1 and any point on the edge of the target electronic unit 10 other than the first sub - point O11. In some embodiments, the number of the second terminals P2 can be multiple. The sum of the distances between the multiple second terminals P2 and the second sub - point O12 is less than or equal to the sum of the distances between the multiple second terminals P2 and any point on the edge of the target electronic unit 10 other than the second sub - point O12.

[0070] As Figure 5a shown, in some embodiments, the first sub - point O11 and the second sub - point O12 can be located on the same side of the target electronic unit 10. The first management unit 161 and the second management unit 162 can be located on the same side of the target electronic unit 10, and the arrangement direction of the first management unit 161, the first sub - point O11, and the first area 101 can be the same as the arrangement direction of the second management unit 162, the second sub - point O12, and the second area 102.

[0071] However, not limited thereto, the first sub-point O11 and the second sub-point O12 may also be located on different sides of the target electronic unit 10, the first management unit 161 and the second management unit 162 may also be located on different sides of the target electronic unit 10, and the arrangement directions of the first management unit 161, the first sub-point O11, and the first area 101 may be opposite to, perpendicular to, or obliquely intersect with the arrangement directions of the second management unit 162, the second sub-point O12, and the second area 102.

[0072] In the present disclosure, the first management unit 161 is used to provide a first interface voltage for the memory unit 11, and the second management unit 162 is used to provide a first core voltage for the memory unit 11. Compared with using a first type of management unit 15 to provide both the first core voltage and the first interface voltage for the memory unit 11 at the same time, a flexible layout of the first type of power management unit 151 can be achieved. In the present disclosure, the first management unit 161 is disposed on one side of the first sub-point O11, and the first management unit 161, the first sub-point O11, and the first area 101 are arranged in the same direction, so that the distance between the first management unit 161 and the first terminal P1 is the shortest. The second management unit 162 is disposed on one side of the second sub-point O12, and the second management unit 162, the second sub-point O12, and the second terminal P2 are arranged in the same direction, so that the distance between the second management unit 162 and the second terminal P2 is the shortest. Thereby, the complexity and length of the trace between the first management unit 161 and the first terminal P1, and the complexity and length of the trace between the second management unit 162 and the second terminal P2 are reduced, thereby reducing the area and cost of the main board 1 and improving the performance of the whole machine.

[0073] Such as Figure 5a As shown, in some embodiments, the power terminals 14 of the second power receiving unit 22 may include a third terminal P3 located in the third area 103 and a fourth terminal P4 located in the fourth area 104; the second type of management unit 152 may include a third management unit 163 and a fourth management unit 164; the second point O2 may include a third sub-point O13 and a fourth sub-point O14.

[0074] In some embodiments, the third management unit 163, the third sub - point O13, and the third area 103 are arranged along the second direction. The distance between the third terminal P3 and the third sub - point O13 is less than or equal to the distance between the third terminal P3 and any point on the edge of the target electronic unit 10 other than the third sub - point O13. The third management unit 163 can be used to provide the second core voltage for the processor 12 through the third terminal P3; the fourth management unit 164, the fourth sub - point O14, and the fourth area 104 are arranged along the second direction. The distance between the fourth terminal P4 and the fourth sub - point O14 is less than or equal to the distance between the fourth terminal P4 and any point on the edge of the target electronic unit 10 other than the fourth sub - point O14. The fourth management unit 164 can be used to provide the second interface voltage for the processor 12 through the fourth terminal P4.

[0075] Here, the second core voltage can be the voltage required for the normal operation of the core of the processor 12, and can include the voltage provided for the transistor array inside the processor 12. The third management unit 163 is electrically connected to the third terminal P3 to provide the second core voltage for the processor 12; the second interface voltage can be any other different power supply voltage of the processor 12 other than the second core voltage, and can include the voltage provided for a mouse, a keyboard, etc. The fourth management unit 164 is electrically connected to the fourth terminal P4 to provide the second interface voltage for the processor 12.

[0076] In some embodiments, the number of the third terminals P3 can be multiple. The sum of the distances between the multiple third terminals P3 and the third sub - point O13 is less than or equal to the sum of the distances between the multiple third terminals P3 and any point on the edge of the target electronic unit 10 other than the third sub - point O13. In some embodiments, the number of the fourth terminals P4 can be multiple. The sum of the distances between the multiple fourth terminals P4 and the fourth sub - point O14 is less than or equal to the sum of the distances between the multiple fourth terminals P4 and any point on the edge of the target electronic unit 10 other than the fourth sub - point O14.

[0077] As Figure 5a shown, in some embodiments, the third sub - point O13 and the fourth sub - point O14 can be respectively located on two opposite sides of the target electronic unit 10. The third management unit 163 and the fourth management unit 164 can be respectively arranged on two opposite sides of the target electronic unit 10. The arrangement direction of the third management unit 163, the third sub - point O13, and the third area 103 can be opposite to the arrangement direction of the fourth management unit 164, the fourth sub - point O14, and the fourth area 104.

[0078] However, not limited thereto, the third sub-point O13 and the fourth sub-point O14 may also be located on the same side of the target electronic unit 10 or on two non-opposite sides of the target electronic unit 10. The third management unit 163 and the fourth management unit 164 may also be located on the same side of the target electronic unit 10. The arrangement directions of the third management unit 163, the third sub-point O13, and the third area 103 may also be the same as, perpendicular to, or obliquely intersect with the arrangement directions of the fourth management unit 164, the fourth sub-point O14, and the fourth area 104.

[0079] In the present disclosure, the third management unit 163 is used to provide the second core voltage for the processor 12, and the fourth management unit 164 is used to provide the second interface voltage for the processor 12. Compared with using a second type of management unit 16 to provide both the second interface voltage and the second core voltage for the processor 12 simultaneously, it is possible to achieve a flexible layout of the second type of management unit 16. The present disclosure arranges the third management unit 163 on one side of the third sub-point O13, and the third management unit 163, the third sub-point O13, and the first area 101 are arranged in the same direction, so as to minimize the distance between the third management unit 163 and the third terminal P3. The fourth management unit 164 is arranged on one side of the fourth sub-point O14, and the fourth management unit 164, the fourth sub-point O14, and the fourth terminal P4 are arranged in the same direction, so as to minimize the distance between the fourth management unit 164 and the fourth terminal P4. Thereby, the complexity and length of the wiring between the third management unit 163 and the third terminal P3, and the complexity and length of the wiring between the fourth management unit 164 and the fourth terminal P4 are reduced, thereby reducing the area and cost of the main board 1 and improving the performance of the whole machine.

[0080] Such as Figure 5a As shown in the figure, in some embodiments, the first area 101, the second area 102, and the third area 103 may be arranged in the fourth direction. The first management unit 161, the second management unit 162, and the third management unit 163 may be located on the same side of the target electronic unit 10 and arranged in sequence in the fourth direction. The third area 103 and the fourth area 104 may be arranged in the first direction. The fourth management unit 164 and the third management unit 163 may be located on opposite sides of the target electronic unit 10. Among them, the fourth direction may be parallel to the plane of the main board 1 and perpendicular to the first direction.

[0081] Such as Figure 5bAs shown, in some embodiments, the memory unit 11 may be arranged with the processor 12 in a first direction. The memory unit 11 may include a first memory 111 and a second memory 112 arranged in a fourth direction. The first memory 111 and the second memory 112 may be the same or different. The first memory 111 and the second memory 112 may be double data rate synchronous dynamic random access memory (DDR) or low power memory (LPDDR), such as one or more of DDR2, DDR3, DDR4, LPDDR5, etc.

[0082] It should be noted that the number of the first type of management units 151 may be even more. A plurality of first points O1 corresponding to the plurality of first type of management units 151 one by one may be distributed on the same side or different sides of the target electronic unit 10; the number of the second type of management units 152 may be even more. A plurality of second points O2 corresponding to the plurality of second type of management units 152 one by one may be distributed on the same side or different sides of the target electronic unit 10.

[0083] As Figures 5a to 5b As shown, in some embodiments, the power terminal 14 of the second power receiving unit 22 may further include a fifth terminal P5 located in the fifth area 105; the main board 1 may further include: at least one oscillator 19 provided on at least one side of the target electronic unit 10; the oscillator 19 may be provided on one side of a third point O3 on the edge of the target electronic unit 10. The third point O3 and the fifth area 105 are arranged in a third direction. The oscillator 19 is arranged in the third direction, and the distance between the fifth terminal P5 and the third point O3 is less than or equal to the distance between the fifth terminal P5 and any point on the edge of the target electronic unit 10 other than the third point O3. The oscillator 19 may be used to provide a clock signal to the processor 12 through the fifth terminal P5. In this way, the distance between the oscillator 19 and the fifth terminal P5 is the closest, reducing the complexity and length of the wiring between the oscillator 19 and the fifth terminal P5, thereby reducing the area of the main board 1.

[0084] Here, the third direction may be a direction parallel to the plane of the main board 1, and the third direction may be the same as or different from the first direction or the second direction.

[0085] In some embodiments, the number of the fifth terminals P5 may be multiple. The sum of the distances between the multiple fifth terminals P5 and the third point O3 is less than or equal to the sum of the distances between the multiple fifth terminals P5 and any point on the edge of the target electronic unit 10 other than the third point O3.

[0086] In some embodiments, the number of crystal oscillators 19 may be multiple. The multiple crystal oscillators 19 may include a first crystal oscillator 191 and a second crystal oscillator 192. The third point O3 may include a fifth sub-point O15 and a sixth sub-point O16. The number of the fifth terminals P5 may be multiple. The multiple fifth terminals P5 at least include one or more fifth terminals P5 electrically connected to the first crystal oscillator 191 and one or more fifth terminals P5 electrically connected to the second crystal oscillator 192. Wherein, the distance between the fifth terminal P5 electrically connected to the first crystal oscillator 191 and the fifth sub-point O15 is less than or equal to the distance between the fifth terminal P5 electrically connected to the first crystal oscillator 191 and any point on the edge of the target electronic unit 10 other than the fifth sub-point O15. The distance between the fifth terminal P5 electrically connected to the second crystal oscillator 192 and the sixth sub-point O16 is less than or equal to the distance between the fifth terminal P5 electrically connected to the second crystal oscillator 192 and any point on the edge of the target electronic unit 10 other than the sixth sub-point O16. In this way, the distance between the first crystal oscillator 191 and the fifth terminal P5 is the shortest, and the distance between the second crystal oscillator 192 and the fifth terminal P5 is the shortest, thereby reducing the complexity and length of the trace between the first crystal oscillator 191 and the fifth terminal P5, and the complexity and length of the trace between the second crystal oscillator 192 and the fifth terminal P5, thereby further reducing the area and cost of the main board 1 and improving the performance of the whole machine.

[0087] In some embodiments, the fifth sub-point O15 and the sixth sub-point O16 may be located on the same side or different sides of the target electronic unit 10. The arrangement directions of the first crystal oscillator 191, the fifth sub-point O15, and the fifth area 105 may be the same as or different from the arrangement directions of the second crystal oscillator 192, the sixth sub-point O16, and the fifth area 105.

[0088] In some embodiments, the number of the fifth terminals P5 electrically connected to the first crystal oscillator 191 may be multiple, and the number of the fifth terminals P5 electrically connected to the second crystal oscillator 192 may be multiple. The sum of the distances between the multiple fifth terminals P5 electrically connected to the first crystal oscillator 191 and the fifth sub-point O15 is less than or equal to the sum of the distances between the multiple fifth terminals P5 electrically connected to the first crystal oscillator 191 and any point on the edge of the target electronic unit 10 other than the fifth sub-point O15. The sum of the distances between the multiple fifth terminals P5 electrically connected to the second crystal oscillator 192 and the sixth sub-point O16 is less than or equal to the sum of the distances between the multiple fifth terminals P5 electrically connected to the second crystal oscillator 192 and any point on the edge of the target electronic unit 10 other than the sixth sub-point O16.

[0089] The number of crystal oscillators 19 can also be greater, such as 3, 4, 5, or 6, etc. A plurality of third points O3 corresponding one-to-one to the plurality of crystal oscillators 19 can be located on the same side or different sides of the target electronic unit 10, and for different crystal oscillators 19, the third direction can be the same or different.

[0090] For example Figures 5a to 5b , in some embodiments, the fifth region 105 and the fourth region 104 can be arranged along the fourth direction, the fifth region 105 and the first crystal oscillator 191 can be arranged along the first direction, and the second crystal oscillator 192 and the fifth region 105 can be arranged along the fourth direction.

[0091] In some embodiments, after the main power supply of the electronic device (such as a computer) is turned on, the crystal oscillator 19 can first provide a clock signal for the processor 12, then the fourth management unit 164 can provide a second interface voltage for the processor 12, then the second management unit 162 can provide a first core voltage for the memory unit 11, then the first management unit 161 can provide a first interface voltage for the memory unit 11, and then the third management unit 163 can provide a core voltage for the processor 12.

[0092] For example Figures 5a to 5b As shown, in some embodiments, the main board 1 can further include: a plurality of first capacitors 181 and a plurality of first inductors 171. The plurality of first capacitors 181 and the plurality of first inductors 171 can be arranged on at least one side of the target electronic unit 10 and can be distributed between the target electronic unit 10 and the power management unit 15. The first capacitor 181 and the first inductor 171 can be used to stabilize and filter the voltage provided by the power management unit 15.

[0093] In some embodiments, the main board 1 can further include a plurality of second capacitors 182 and a plurality of second inductors 172 located on at least one side of the target electronic unit 10. The plurality of second capacitors 182 and the plurality of second inductors 172 can be arranged on one side of at least one point on the edge of the target electronic unit 10 other than the first point O1 and the second point O2.

[0094] For example Figures 5a to 5b As shown, in some embodiments, the plurality of second capacitors 182 and the plurality of second inductors 172 can be distributed along the fourth direction on both sides of the target electronic unit 10.

[0095] For example Figure 6 As shown, in some embodiments, the main board 1 can include a target area 2. The target electronic unit 10 and a plurality of power management units 15 can be located in the target area 2 of the main board 1, and the plurality of power management units 15 can be distributed on both sides of the target electronic unit 10 in the first direction.

[0096] The target area 2 of the present disclosure may include the target electronic unit 10 and the area where multiple power management units 15 that supply power to the target electronic component 10 are located. Multiple electronic components located within the target area 2 cooperate to achieve the functions of the target electronic unit 10. The shape of the target area 2 may be a regular or irregular figure, such as a rectangle, polygon, circle, ellipse, etc.

[0097] The present disclosure realizes the close arrangement of multiple power management units 15 and the target electronic unit 10 by disposing the first type of management unit 151 on one side of the first point O1 and / or disposing the second type of management unit 152 on one side of the second point O2, reducing the size of the target area 2. In some embodiments, the range of the length of the target area 2 extending in the first direction may be between 65 mm and 70 mm (including the end point values), such as 65 mm, 68 mm, 70 mm, etc., and the range of the length of the target area 2 extending in the direction (the fourth direction) perpendicular to the first direction may be between 38 mm and 40 mm (including the end point values), such as 38 mm, 39 mm, 40 mm, etc.

[0098] The target area 2 provided by the present disclosure can be applied to Intel's LNL (Lunar Lake) project, including Proof Of Concept (POC) projects, such as Warrior, West lake, and Mass Production (MP) projects, such as Qixia, S9, Aladdin, and Alloy, etc.

[0099] In some embodiments, the crystal oscillator 19, multiple first capacitors 181 and multiple first inductors 171, multiple second capacitors 182 and multiple second inductors 172 may also be disposed in the target area 2 of the main board 1 to increase the layout rate of the target area 2, and thus contribute to increasing the layout rate of the main board 1.

[0100] As Figure 7As shown in the figure, the present disclosure also provides an electronic device 100, which includes a main board 1. The main board 1 includes: a target electronic unit, including a first power receiving unit and a second power receiving unit; a plurality of power management units, including one or more first type management units electrically connected to the first power receiving unit, and / or one or more second type management units electrically connected to the second power receiving unit; wherein, the first type management unit is disposed on one side of a first point on the edge of the target electronic unit, the distance between the power terminal of the first power receiving unit and the first point is less than or equal to the distance between the power terminal of the first power receiving unit and any point other than the first point on the edge of the target electronic unit, the first point and the power terminal of the first power receiving unit are arranged along a first direction, and the first type management units are arranged along the first direction; and / or, the second type management unit is disposed on one side of a second point on the edge of the target electronic unit, the distance between the power terminal of the second power receiving unit and the second point is less than or equal to the distance between the power terminal of the second power receiving unit and any point other than the second point on the edge of the target electronic unit, the second point and the power terminal of the second power receiving unit are arranged along a second direction, and the second type management units are arranged along the second direction.

[0101] In the electronic device provided by the present disclosure, by arranging the first type management unit along the first direction on one side of the first point, and / or arranging the second type management unit along the second direction on one side of the second point, the shortest distance between the first type management unit and the power terminal of the first power receiving unit is achieved, and / or the shortest distance between the second type management unit and the power terminal of the second power receiving unit is achieved, thereby reducing the complexity and length of the wiring between the first type management unit and the power terminal of the first power receiving unit, and / or the complexity and length of the wiring between the second type management unit and the power terminal of the second power receiving unit, thereby reducing the area and cost of the main board in the electronic device and improving the performance of the electronic device. Moreover, since the first type management unit and / or the second type management unit are respectively close to the power terminals of the first power receiving unit and / or the second power receiving unit, the power transmission path can be reduced, thereby reducing the resistance and inductance, improving the power transmission efficiency, reducing the energy loss, and also helping to reduce the electromagnetic interference to other electronic components and improve the stability of the system. In addition, the power management unit being close to the power receiving unit it manages also helps to concentrate the heat, facilitate the heat dissipation design, and improve the thermal management of the entire system.

[0102] It should be noted that the various embodiments of the main board provided by the present disclosure belong to the same concept; among the technical features in the technical solutions recorded in the various embodiments, they can be arbitrarily combined without conflict.

[0103] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A motherboard, characterized in that: The main board comprises: a target electronic unit, comprising a first power receiving unit and a second power receiving unit; a plurality of power management units, including one or more first-type management units electrically connected to the first power receiving unit, and / or one or more second-type management units electrically connected to the second power receiving unit; Wherein, the first type of management unit is arranged on one side of a first point on the edge of the target electronic unit, the distance between the power terminal of the first power receiving unit and the first point is less than or equal to the distance between the power terminal of the first power receiving unit and any point on the edge of the target electronic unit except the first point, the first point and the power terminal of the first power receiving unit are arranged along a first direction, and the first type of management units are arranged along the first direction; and / or, The second type of management unit is arranged on one side of a second point on the edge of the target electronic unit, the distance between the power terminal of the second power receiving unit and the second point is less than or equal to the distance between the power terminal of the second power receiving unit and any point on the edge of the target electronic unit except the second point, the second point and the power terminal of the second power receiving unit are arranged along a second direction, and the second type of management units are arranged along the second direction.

2. The mainboard according to claim 1, characterized in that: The first power receiving unit has a plurality of power terminals, and the sum of distances between the plurality of power terminals of the first power receiving unit and the first point is less than or equal to the distance between the plurality of power terminals of the first power receiving unit and any point on the edge of the target electronic unit except the first point; and / or The second power receiving unit has multiple power terminals, and the sum of distances between the multiple power terminals of the second power receiving unit and the second point is less than or equal to the sum of distances between the multiple power terminals of the second power receiving unit and any point on the edge of the target electronic unit except the second point.

3. The mainboard according to claim 1, characterized in that: Any edge of the target electronic unit is a curve and / or a straight line.

4. The mainboard according to claim 1, characterized in that: The first power receiving unit is a memory unit, and the second power receiving unit is a processor.

5. The mainboard according to claim 4, characterized in that: The power terminal of the first power receiving unit includes a first terminal located in the first area and a second terminal located in the second area; the first type management unit includes a first management unit and a second management unit; the first point includes a first sub-point and a second sub-point; The first management unit, the first sub-point, and the first area are arranged along the first direction, the distance between the first terminal and the first sub-point is less than or equal to the distance between the first terminal and any point on the edge of the target electronic unit except the first sub-point, and the first management unit is used to provide a first interface voltage to the memory unit through the first terminal; The second management unit, the second sub-point and the second area are arranged along the first direction, the distance between the second terminal and the second sub-point is less than or equal to the distance between the second terminal and any point on the edge of the target electronic unit except the second sub-point, and the second management unit is used to provide a first core voltage to the memory unit through the second terminal.

6. The mainboard according to claim 4, characterized in that: The power supply terminal of the second power receiving unit includes a third terminal located in the third area and a fourth terminal located in the fourth area; the second type management unit includes a third management unit and a fourth management unit; the second point includes a third sub-point and a fourth sub-point; The third management unit, the third sub-point and the third area are arranged along the second direction, the distance between the third terminal and the third sub-point is less than or equal to the distance between the third terminal and any point on the edge of the target electronic unit except the third sub-point, and the third management unit is used to provide a second core voltage for the processor through the third terminal; The fourth management unit, the fourth sub-point and the fourth area are arranged along the second direction, the distance between the fourth terminal and the fourth sub-point is less than or equal to the distance between the fourth terminal and any point on the edge of the target electronic unit except the fourth sub-point, and the fourth management unit is used to provide a second interface voltage to the processor through the fourth terminal.

7. The mainboard according to claim 4, characterized in that: The power terminal of the second power receiving unit further includes a fifth terminal located in the fifth area; the main board further includes: at least one crystal oscillator disposed on at least one side of the target electronic unit; The crystal oscillator is arranged on one side of a third point on the edge of the target electronic unit, the third point and the fifth area are arranged along a third direction, the crystal oscillator is arranged along the third direction, and the distance between the fifth terminal and the third point is less than or equal to the distance between the fifth terminal and any point on the edge of the target electronic unit except the third point, and the crystal oscillator is used to provide a clock signal to the processor through the fifth terminal.

8. The mainboard according to claim 1, characterized in that: The mainboard further includes: a plurality of first capacitors and a plurality of first inductors, wherein the plurality of first capacitors and the plurality of first inductors are disposed on at least one side of the target electronic unit and distributed between the target electronic unit and the power management unit.

9. The mainboard according to any one of claims 1 to 8, characterized in that: The target electronic unit and the multiple power management units are located in the target area of ​​the main board. The multiple power management units are distributed on both sides of the target electronic unit in the first direction. The length of the target area extending along the first direction ranges from 65 mm to 70 mm, and the length extending in a direction perpendicular to the first direction ranges from 38 mm to 40 mm.

10. An electronic device, characterized in that: The electronic device comprises a main board, and the main board comprises: a target electronic unit, comprising a first power receiving unit and a second power receiving unit; a plurality of power management units, including one or more first-type management units electrically connected to the first power receiving unit, and / or one or more second-type management units electrically connected to the second power receiving unit; Wherein, the first type of management unit is arranged on one side of a first point on the edge of the target electronic unit, the distance between the power terminal of the first power receiving unit and the first point is less than or equal to the distance between the power terminal of the first power receiving unit and any point on the edge of the target electronic unit except the first point, the first point and the power terminal of the first power receiving unit are arranged along a first direction, and the first type of management units are arranged along the first direction; and / or, The second type of management unit is arranged on one side of a second point on the edge of the target electronic unit, the distance between the power terminal of the second power receiving unit and the second point is less than or equal to the distance between the power terminal of the second power receiving unit and any point on the edge of the target electronic unit except the second point, the second point and the power terminal of the second power receiving unit are arranged along a second direction, and the second type of management units are arranged along the second direction.

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