Watchdog circuit

Abstract

The utility model provides a watchdog circuit. The watchdog circuit provided by the utility model comprises a time delay unit and a watchdog chip, the time delay unit is connected with a first end of the watchdog chip, and a second end and a third end of the watchdog chip are connected with a monitored system. The watchdog circuit can continuously input voltage to the watchdog chip within the preset time after the monitored system is started, so that the watchdog chip cannot send a reset signal to the monitored system under the condition that the watchdog chip does not receive a dog feeding signal, and the stability and the reliability of the watchdog circuit are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of system operation monitoring, in particular to a watchdog circuit. Background Art

[0002] A watchdog circuit is a common electronic circuit and an indispensable part of an embedded system. It is mainly used to monitor and protect the normal operation of a microprocessor or microcontroller system. When the processor works normally, it outputs a signal to the watchdog feeding terminal at regular intervals to clear the WDT (Watchdog Timer). If the program of the processor enters an infinite loop and the watchdog feeding terminal of the watchdog chip does not receive a signal, when the accumulated time of the WDT exceeds the preset time (usually 1.6 seconds), the watchdog circuit triggers the reset circuit to restart the system.

[0003] With the increasing scale of software in the embedded system, the startup time of the software is getting longer. If the startup time of the system software exceeds the preset time, it will be reset by the watchdog circuit at the last moment of the preset time and restart continuously, resulting in the program being unable to run normally. The same problem also exists in the process of program burning. If the duration of program burning exceeds the preset time, the watchdog circuit will also restart, resulting in the program being unable to complete normal burning. These situations make the stability and reliability of the watchdog circuit in the prior art insufficient. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a watchdog circuit to solve the technical problem of insufficient stability and reliability of the watchdog circuit in the prior art.

[0005] The technical solution of the utility model is as follows: A watchdog circuit is provided, which includes a delay unit and a watchdog chip. The delay unit is connected to the first end of the watchdog chip, and the second end and the third end of the watchdog chip are connected to the monitored system;

[0006] The delay unit is used to continuously input voltage to the watchdog chip within a preset time after the monitored system starts, so that the watchdog chip cannot send a reset signal to the monitored system.

[0007] Preferably, the delay unit is connected to the MR pin of the watchdog chip, and the RESET pin and the WDI pin of the watchdog chip are connected to the monitored system.

[0008] Preferably, the delay unit includes a delay voltage sub-unit, a reference voltage sub-unit, a comparator U1A, and a PMOS transistor Q1. The delay voltage sub-unit is connected to the non-inverting input terminal of the comparator U1A. The reference voltage sub-unit is connected to the inverting input terminal of the comparator U1A. The first power supply interface of the comparator U1A is connected to a power supply. The second power supply interface of the comparator U1A is grounded. The output terminal of the comparator U1A is connected to the gate of the PMOS transistor Q1. The source of the PMOS transistor Q1 is connected to the power supply. The drain of the PMOS transistor Q1 is connected to the MR pin of the watchdog chip.

[0009] Preferably, the delay voltage sub-unit includes a resistor Rset and a capacitor Cset. The first end of the resistor Rset is connected to the power supply. The second end of the resistor Rset is connected to the non-inverting input terminal of the comparator U1A. The second end of the resistor Rset is also connected to the first end of the capacitor Cset. The second end of the capacitor Cset is grounded.

[0010] Preferably, the capacitor Cset is an electrolytic capacitor.

[0011] Preferably, the reference voltage sub-unit includes a resistor Ru and a resistor Rd. The first end of the resistor Ru is connected to the power supply. The second end of the resistor Ru is connected to the inverting input terminal of the comparator U1A. The second end of the resistor Ru is also connected to the first end of the resistor Rd. The second end of the resistor Rd is grounded.

[0012] Preferably, the watchdog circuit further includes a reset switch SW. The first end of the reset switch SW is grounded. The second end of the reset switch SW is connected to the MR pin of the watchdog chip.

[0013] Preferably, the Vcc pin of the watchdog chip is connected to the power supply.

[0014] Preferably, the GND pin of the watchdog chip is grounded.

[0015] Preferably, the watchdog chip is a MAX706 chip or an SP706 chip.

[0016] The beneficial effects of the present utility model are as follows: The delay unit continuously inputs a voltage to the watchdog chip within a preset time after the monitored system is started, so that the watchdog chip will not send a reset signal to the monitored system even when no dog-feeding signal is received, improving the stability and reliability of the watchdog circuit. Description of the Drawings

[0017] Figure 1 It is a structural block diagram of the watchdog circuit according to an embodiment of the present utility model.

[0018] Figure 2 This is the circuit diagram of the watchdog circuit according to the embodiment of the present utility model.

[0019] Reference numerals: Delay unit - 10; Watchdog chip - 20; Monitored system - 30. Specific embodiments

[0020] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0021] Referring to "embodiments" herein means that the specific features, structures or characteristics described in conjunction with the embodiments can be included in at least one embodiment of the present utility model. The phrase appears at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0022] Figure 1 This is the circuit diagram of the watchdog circuit according to the embodiment of the present utility model. It should be noted that if there are substantially the same results, the present utility model is not limited to Figure 1 the structure shown. As Figure 1 shown, the watchdog circuit includes a delay unit 10 and a watchdog chip 20. The delay unit 10 is connected to the first end of the watchdog chip 20, and the second end and the third end of the watchdog chip 20 are connected to the monitored system 30;

[0023] The delay unit 10 is configured to continuously input a voltage to the watchdog chip 20 within a preset time after the monitored system 30 starts, so that the watchdog chip 20 cannot send a reset signal to the monitored system 30.

[0024] In this embodiment, the delay unit 10 continuously inputs a voltage to the watchdog chip 20 within a preset time after the monitored system 30 starts, so that the watchdog chip 20 will not send a reset signal to the monitored system 30 even when no dog-feeding signal is received, improving the stability and reliability of the watchdog circuit.

[0025] In a specific embodiment, the preset time can be the time required from the start to the completion of the initial start of the monitored system 30, or the time required for the monitored system 30 to perform program burning. The monitored system 30 can be a Linux embedded operating system.

[0026] In some embodiments, Figure 2 is the circuit diagram of the watchdog circuit of the embodiment of the present utility model. As Figure 2 shown, the delay unit 10 is connected to the MR pin of the watchdog chip 20, and the RESET pin and the WDI pin of the watchdog chip 20 are connected to the monitored system 30.

[0027] In this embodiment, the delay unit 10 continuously inputs a voltage to the MR pin of the watchdog chip 20, so that the RESET pin of the watchdog chip 20 maintains a high level state, so that the watchdog chip 20 will not send a reset signal to the monitored system 30 without receiving a dog-feeding signal.

[0028] In some embodiments, as Figure 2 shown, the delay unit 10 includes a delay voltage sub-unit, a reference voltage sub-unit, a comparator U1A, and a PMOS transistor Q1. The delay voltage sub-unit is connected to the non-inverting input terminal of the comparator U1A, the reference voltage sub-unit is connected to the inverting input terminal of the comparator U1A, the first power supply interface of the comparator U1A is connected to the power supply, the second power supply interface of the comparator U1A is grounded, the output terminal of the comparator U1A is connected to the gate of the PMOS transistor Q1, the source of the PMOS transistor Q1 is connected to the power supply, and the drain of the PMOS transistor Q1 is connected to the MR pin of the watchdog chip 20.

[0029] In this embodiment, the power supply connected to each component outputs a continuous and stable voltage Vcc, and the power supply and the monitored system 30 are started at the same time; the delay voltage sub-unit inputs a voltage Vch with an initial value of 0 and gradually increasing with time to the non-inverting input terminal of the comparator U1A; the reference voltage sub-unit inputs a continuous and stable voltage Vref to the inverting input terminal of the comparator U1A; when the watchdog circuit of this embodiment is just powered on, Vch = 0, the output voltage Von of the output terminal of the comparator U1A is 0, the PMOS transistor Q1 is turned on, and the MR pin of the watchdog chip 20 receives the voltage Vcc of the power supply through the PMOS transistor Q1, so that the RESET pin of the watchdog chip 20 maintains a high level state, so that the watchdog chip 20 will not send a reset signal to the monitored system 30 without receiving a dog-feeding signal. When the watchdog circuit of this embodiment is powered on for more than the preset time, Vch > Vref, at this time Von = Vcc, the PMOS transistor Q1 is turned off, the MR pin of the watchdog chip 20 no longer receives an external voltage, and the watchdog chip 20 starts to work normally.

[0030] In some embodiments, as Figure 2As shown, the delay voltage sub-unit includes a resistor Rset and a capacitor Cset. The first end of the resistor Rset is connected to the power supply, the second end of the resistor Rset is connected to the non-inverting input terminal of the comparator U1A, the second end of the resistor Rset is also connected to the first end of the capacitor Cset, and the second end of the capacitor Cset is grounded.

[0031] In this embodiment, the resistor Rset and the capacitor Cset together form the delay voltage sub-unit. As the power supply Vcc charges the capacitor Cset through the resistor Rset, the voltage input by the delay voltage sub-unit to the non-inverting input terminal of the comparator U1A also changes with time. The formula for the voltage Vch input to the non-inverting input terminal of the comparator U1A changing with time t is: Vch is the voltage input by the delay voltage sub-unit to the non-inverting input terminal of the comparator U1A; Vcc is the voltage provided by the power supply; e is the base of the natural logarithm; t is time.

[0032] In some embodiments, the capacitor Cset is an electrolytic capacitor.

[0033] In this embodiment, the capacitor Cset is an electrolytic capacitor. The electrolytic capacitor has polarity and usually has a large capacitance, which is suitable for application scenarios that require long delays.

[0034] In some embodiments, as Figure 2 shown, the reference voltage sub-unit includes a resistor Ru and a resistor Rd. The first end of the resistor Ru is connected to the power supply, the second end of the resistor Ru is connected to the inverting input terminal of the comparator U1A, the second end of the resistor Ru is also connected to the first end of the resistor Rd, and the second end of the resistor Rd is grounded.

[0035] In this embodiment, the resistor Ru and the resistor Rd form the reference voltage sub-unit. The voltage input by the reference voltage sub-unit to the inverting input terminal of the comparator U1A depends on the voltage provided by the power supply and the resistance values of the resistor Ru and the resistor Rd. The calculation formula for the voltage Vref input to the inverting input terminal of the comparator U1A is: Vref is the voltage input by the reference voltage sub-unit to the inverting input terminal of the comparator U1A, and Vcc is the voltage provided by the power supply.

[0036] In a specific embodiment, let the time t when Vch = Vref be t1, and the calculation formula for t1 is: When the time t is less than t1, Vch < Vref, Von = 0, the PMOS transistor Q1 is turned on, and the MR pin of the watchdog chip 20 receives the voltage Vcc of the power supply through the PMOS transistor Q1, so that the RESET pin of the watchdog chip 20 maintains a high level state, and the watchdog chip 20 will not send a reset signal to the monitored system 30 without receiving a dog-feed signal. When the time t is greater than t1, Vch > Vref, at this time Von = Vcc, the PMOS transistor Q1 is turned off, the MR pin of the watchdog chip 20 no longer receives an external voltage, and the watchdog chip 20 starts to work normally.

[0037] In practical applications, the value of t1 can be adjusted by adjusting the values of Rset, Cset, Rd, and Ru, so as to adjust the time when the watchdog chip 20 starts to work normally to adapt to the startup time of the monitored system 30.

[0038] In some embodiments, as Figure 2 shown, the watchdog circuit further includes a reset switch SW, the first end of the reset switch SW is grounded, and the second end of the reset switch SW is connected to the MR pin of the watchdog chip 20.

[0039] In this embodiment, after pressing the reset switch SW, a low-level signal can be applied to the MR pin of the watchdog chip 20, so that the watchdog chip 20 sends a reset signal to the monitored system 30 through the RESET pin to complete a forced reset.

[0040] In some embodiments, as Figure 2 shown, the Vcc pin of the watchdog chip 20 is connected to the power supply.

[0041] In this embodiment, the Vcc pin of the watchdog chip 20 is connected to the power supply to provide the power required for the normal operation of the chip.

[0042] In some embodiments, as Figure 2 shown, the GND pin of the watchdog chip 20 is grounded.

[0043] In this embodiment, the GND pin of the watchdog chip 20 is grounded to serve as the reference ground for all signals to ensure the normal operation of the circuit.

[0044] In some embodiments, the watchdog chip 20 is a MAX706 chip or an SP706 chip.

[0045] In this embodiment, the watchdog chip 20 is a MAX706 chip or an SP706 chip. In practical applications, the watchdog chip 20 can also be other mainstream 706-type chips, such as an IMP706 chip.

[0046] The above are only the embodiments of the present utility model. It should be noted here that for those of ordinary skill in the art, improvements can be made without departing from the creative concept of the present utility model, but these all fall within the protection scope of the present utility model.

Claims

1. A watchdog circuit, characterized in that: It includes a delay unit and a watchdog chip, wherein the delay unit is connected to a first end of the watchdog chip, and a second end and a third end of the watchdog chip are connected to a monitored system; The delay unit is used to continuously input voltage to the watchdog chip within a preset time after the monitored system is started, so that the watchdog chip cannot send a reset signal to the monitored system.

2. The watchdog circuit according to claim 1, characterized in that: The delay unit is connected to the MR pin of the watchdog chip, and the RESET pin and WDI pin of the watchdog chip are connected to the monitored system.

3. The watchdog circuit according to claim 2, characterized in that: The delay unit includes a delay voltage subunit, a reference voltage subunit, a comparator U1A and a PMOS tube Q1. The delay voltage subunit is connected to the same-direction input terminal of the comparator U1A, the reference voltage subunit is connected to the reverse input terminal of the comparator U1A, the first power interface of the comparator U1A is connected to the power supply, the second power interface of the comparator U1A is grounded, the output terminal of the comparator U1A is connected to the gate of the PMOS tube Q1, the source of the PMOS tube Q1 is connected to the power supply, and the drain of the PMOS tube Q1 is connected to the MR pin of the watchdog chip.

4. The watchdog circuit according to claim 3, characterized in that: The delay voltage subunit includes a resistor Rset and a capacitor Cset, the first end of the resistor Rset is connected to the power supply, the second end of the resistor Rset is connected to the same-direction input end of the comparator U1A, the second end of the resistor Rset is also connected to the first end of the capacitor Cset, and the second end of the capacitor Cset is grounded.

5. The watchdog circuit according to claim 4, characterized in that: The capacitor Cset is an electrolytic capacitor.

6. The watchdog circuit according to claim 3, characterized in that: The reference voltage subunit includes a resistor Ru and a resistor Rd, wherein the first end of the resistor Ru is connected to a power supply, the second end of the resistor Ru is connected to the inverting input end of the comparator U1A, the second end of the resistor Ru is also connected to the first end of the resistor Rd, and the second end of the resistor Rd is grounded.

7. The watchdog circuit according to claim 1, characterized in that: The watchdog circuit further includes a reset switch SW, a first end of the reset switch SW is grounded, and a second end of the reset switch SW is connected to an MR pin of the watchdog chip.

8. The watchdog circuit according to claim 1, characterized in that: The Vcc pin of the watchdog chip is connected to a power supply.

9. The watchdog circuit according to claim 1, characterized in that: The GND pin of the watchdog chip is grounded.

10. The watchdog circuit according to claim 1, characterized in that: The watchdog chip is a MAX706 chip or an SP706 chip.

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