Capacitance-free driver circuit of display device

Abstract

The utility model discloses a non-capacitive driver circuit of a display device. The non-capacitive driver circuit includes an anti-noise control circuit and a plurality of output circuits. The control end and the first end of a first control transistor of the anti-noise control circuit respectively receive a first driving signal and a first scanning signal. The second end of the first control transistor is connected with the first end of the third control transistor. The control end of the third control transistor is connected with the first control ends of the first transistors of the plurality of output circuits. The control end of the third control transistor and the second control end of the first transistor are coupled to a first voltage level. In each output circuit, the control end and the second end of the third transistor are respectively connected with the first end of the first transistor and the output end of each output circuit. The first end of the third transistor receives a second frequency signal. Therefore, the non-capacitive driver circuit provided by the utility model can have a smaller frame, and ensures that the output circuit is not opened by mistake in a closed state.

Description

Technical Field

[0001] The utility model relates to a driver circuit of a display device, in particular to a capacitorless driver circuit. Background Art

[0002] There is a need for narrow bezels / frameless displays, and the non-display boundaries require smaller bezels. The capacitors in the existing GOA (gatedriver on array) circuits occupy a large space, which limits the reduction of the boundaries. During the operation of the display, the output circuit is mostly in the off state. If the capacitors are omitted, the circuit operation is easily affected by noise crosstalk caused by voltage sources, frequency signals or parasitic capacitance coupling, resulting in accidental turn-on of the output terminal, and then generating a flickering or incorrect display screen.

[0003] Therefore, how to prevent the malfunction of the transistors at the output terminal through the improvement of the anti-noise circuit design has become one of the important issues to be solved in this field. Summary of the Invention

[0004] The technical problem to be solved by the utility model is to provide a capacitorless driver circuit for a display device in view of the deficiencies of the prior art. The capacitorless driver circuit includes at least one anti-noise control circuit and a plurality of output circuits. The technical features that the output circuits share the anti-noise control circuit and omit capacitors can reduce the number of transistors used and achieve a smaller bezel. The anti-noise control circuit and each output circuit are respectively coupled to a lower voltage level, which can ensure that the output circuit will not be accidentally turned on in the off state.

[0005] To solve the above technical problems, one of the technical solutions adopted by the present utility model is to provide a capacitorless driver circuit for a display device, which includes a noise-resistant control circuit and a plurality of output circuits. The noise-resistant control circuit includes a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, and a signal generation circuit. The control terminal of the first control transistor receives a first driving signal. The first terminal of the first control transistor receives a first scanning signal. The control terminal of the second control transistor receives a second driving signal. The first terminal of the second control transistor is connected to a voltage source. The second terminal of the second control transistor is connected to the second terminal of the first control transistor. The first terminal of the third control transistor is connected to the second terminal of the first control transistor. The second terminal of the third control transistor is coupled to a first voltage level. The control terminal of the fourth control transistor is connected to the second terminal of the first control transistor. The first terminal of the fourth control transistor is connected to the control terminal of the third control transistor. The second terminal of the fourth control transistor is coupled to the first voltage level. The signal generation circuit is configured to generate a first control signal to the control terminal of the third control transistor according to a first frequency signal. Each output circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first control terminal of the first transistor is connected to the control terminal of the third control transistor. The second terminal of the first transistor is coupled to a second voltage level. The second control terminal of the first transistor is coupled to the first voltage level. The first terminal of the second transistor receives the first scanning signal. The second terminal of the second transistor is connected to the first terminal of the first transistor. The control terminal of the second transistor receives the first driving signal. The first terminal of the third transistor receives a second frequency signal. The second terminal of the third transistor is connected to the output terminal of the output circuit. The control terminal of the third transistor is connected to the first terminal of the first transistor. The first terminal of the fourth transistor is connected to the output terminal. The control terminal of the fourth transistor is connected to the control terminal of the third control transistor. The second terminal of the fourth transistor is coupled to the second voltage level.

[0006] Further, the noise-resistant control circuit further includes: a fifth control transistor, the control terminal of the fifth control transistor receives a third driving signal, the first terminal of the fifth control transistor is connected to the second terminal of the first control transistor, and the second terminal of the fifth control transistor is connected to a second scanning signal; a sixth control transistor, the control terminal of the sixth control transistor receives a fourth driving signal, the first terminal of the sixth control transistor is connected to the voltage source, and the second terminal of the sixth control transistor is connected to the second terminal of the first control transistor; a seventh control transistor, the control terminal of the seventh control transistor receives a fifth driving signal, the first terminal of the seventh control transistor is connected to the voltage source, and the second terminal of the seventh control transistor is connected to the second terminal of the first control transistor.

[0007] Further, a first end of the signal generation circuit receives the first frequency signal, a second end and a third end of the signal generation circuit are respectively connected to a control end of the third control transistor and a second end of the first control transistor, and a fourth end of the signal generation circuit is coupled to the first voltage level; the first control signal is output from the second end of the signal generation circuit.

[0008] Further, the anti-noise control circuit further includes: a complementary signal generation circuit, a first end of the complementary signal generation circuit receives a third frequency signal, a second end of the complementary signal generation circuit outputs a second control signal, a third end of the complementary signal generation circuit is connected to the second end of the first control transistor, and a fourth end of the complementary signal generation circuit is coupled to the first voltage level. The complementary signal generation circuit generates the second control signal according to the third frequency signal.

[0009] Further, the anti-noise control circuit further includes: an eighth control transistor, a control end of the eighth control transistor is connected to the second end of the complementary signal generation circuit, a first end of the eighth control transistor is connected to the second end of the first control transistor, and a second end of the eighth control transistor is coupled to the first voltage level.

[0010] Further, the anti-noise control circuit further includes: a ninth control transistor, a control end of the ninth control transistor is connected to the second end of the first control transistor, a first end of the ninth control transistor is connected to the second end of the complementary signal generation circuit, and a second end of the ninth control transistor is coupled to the first voltage level.

[0011] Further, each of the output circuits further includes: a fifth transistor, a first control end of the fifth transistor is connected to the second end of the complementary signal generation circuit, a second control end of the fifth transistor is coupled to the first voltage level, a first end of the fifth transistor is connected to the first end of the first transistor, and a second end of the fifth transistor is coupled to the second voltage level.

[0012] Further, each of the output circuits further includes: a sixth transistor, a first control end of the sixth transistor receives the fifth driving signal, a second control end of the sixth transistor is coupled to the first voltage level, a first end of the sixth transistor is connected to the first end of the first transistor, and a second end of the sixth transistor receives the second scan signal.

[0013] Further, each of the output circuits further includes: a seventh transistor, a control end of the seventh transistor is connected to the second end of the complementary signal generation circuit, a first end of the seventh transistor is connected to the output end, and a second end of the seventh transistor is coupled to the second voltage level.

[0014] Furthermore, each of the output circuits further includes: an eighth transistor, a first control terminal of the eighth transistor receives a reset signal, a second control terminal of the eighth transistor is coupled to the first voltage level, a first terminal of the eighth transistor is connected to a first terminal of the first transistor, and a second terminal of the eighth transistor is coupled to the second voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit layout diagram of a capacitorless driver circuit of a display device according to an embodiment of the present invention.

[0016] Figure 2 It is a circuit layout diagram of an anti-noise control circuit according to an embodiment of the present invention.

[0017] Figure 3A It is a circuit layout diagram of an Nth-stage output circuit according to an embodiment of the present invention.

[0018] Figure 3B It is a circuit layout diagram of an (N + 1)th-stage output circuit according to an embodiment of the present invention.

[0019] Figure 3C It is a circuit layout diagram of an (N + 2)th-stage output circuit according to an embodiment of the present invention.

[0020] Figure 3D It is a circuit layout diagram of an (N + 3)th-stage output circuit according to an embodiment of the present invention.

[0021] Figure 4 It is an operation timing diagram of a capacitorless driver circuit according to an embodiment of the present invention.

[0022] Figure 5 It is a schematic diagram of a capacitorless driver circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The following are specific examples to illustrate the embodiments of the present invention regarding the "capacitorless driver circuit of a display device". Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Additionally, the drawings of the present invention are only for simple schematic illustration and are not drawn according to actual dimensions, hereby stating in advance. The following embodiments will further detail the related technical content of the present invention, but the disclosed content is not used to limit the protection scope of the present invention.

[0024] It should be understood that although terms such as "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another, or one signal from another. In addition, the term "or" used herein should, depending on the actual situation, possibly include any one or a combination of more of the associated listed items.

[0025] Figure 1 This is a circuit layout diagram of a capacitorless driver circuit for a display device according to an embodiment of the present invention. Refer to Figure 1 As shown, an embodiment of the present invention provides a capacitorless driver circuit CLD which may include an anti-noise control circuit ANC and a plurality of output circuits OUT. In an embodiment of the present invention, the capacitorless driver circuit CLD can provide a first control signal SQN from an anti-noise control circuit ANC to 4 output circuits OUT. The 4 output circuits are the Nth-stage output circuit OUT(N), the (N + 1)th-stage output circuit OUT(N + 1), the (N + 2)th-stage output circuit OUT(N + 2), and the (N + 3)th-stage output circuit OUT(N + 3).

[0026] The following describes the gate output circuit of the capacitorless driver circuit applied in a display. The gate output circuit of the display sequentially provides a high voltage to the scan lines of the panel display area from top to bottom or from bottom to top, so that the transistors connected to this scan line in the display panel are turned on, so that the current provided by the source chip of this transistor flows through this transistor to the pixel voltage connected to this scan line, so as to sequentially turn on each column of pixels of the liquid crystal display panel. That is to say, the source driver cooperates with the turn-on timing of the column pixels to provide a data voltage to drive the pixels. However, the present invention is not limited to the gate driving circuit. Therefore, the Nth-stage output circuit OUT(N) provides a driving signal to the Nth scan line, the (N + 1)th-stage output circuit OUT(N + 1) provides a driving signal to the (N + 1)th scan line, and so on.

[0027] The anti-noise control circuit ANC includes a first control transistor CT1, a second control transistor CT2, a third control transistor CT3, a fourth control transistor CT4, and a signal generation circuit GCS. Further illustrate the connection relationship of each component in the anti-noise control circuit ANC in Figure 1 The control terminal of the first control transistor CT1 is coupled to the first driving signal G(N - 4), that is, coupled to the G(N - 4)th-stage driving signal. As described above, it is known that the Nth-stage output circuit OUT(N) provides a driving signal to the Nth scan line, and in an embodiment of the present invention, an anti-noise control circuit ANC provides an anti-noise control signal to 4 gate output circuits. Figure 5 This is a schematic diagram of the Nth-stage to (N + 7)th-stage capacitorless driver circuit according to an embodiment of the present invention. AsFigure 5 As shown, the first anti-noise control circuit ANC provides anti-noise control signals SQN and SQNX to output circuits OUT(N) to OUT(N + 3). The second anti-noise control circuit ANC provides anti-noise control signals (not shown in the figure) to output circuits OUT(N + 4) to OUT(N + 7). Although Figure 5 not marked in the figure, it can be known that the previous anti-noise control circuit ANC before the first anti-noise control circuit ANC provides anti-noise control signals to output circuits OUT(N - 4) to OUT(N - 1). Therefore, when the first output circuit of the previous anti-noise control circuit ANC, that is, the (N - 4)-th stage output circuit, outputs a high voltage to the G(N - 4)-th stage driving signal, the first control transistor CT1 of the first anti-noise control circuit ANC is also turned on.

[0028] The first end of the first control transistor CT1 is coupled to the first scan signal U2D, that is, the forward scan signal U2D. The second end of the first control transistor CT1 is connected to the second end of the second control transistor CT2. For the convenience of explaining the signal change at the second end of the first control transistor CT1, it is called the control node X. When the first control transistor CT1 is turned on / conducted according to the high voltage level provided by the G(N - 4)-th stage driving signal, the current supplied from the forward scan signal U2D can flow through the turned-on / conducted first control transistor CT1 to charge the control node X.

[0029] The control end of the second control transistor CT2 is coupled to the second driving signal G(N + 2), that is, coupled to the G(N + 2)-th stage driving signal. That is, when the third output circuit of the first anti-noise control circuit ANC, that is, the (N + 2)-th stage output circuit, outputs a high voltage, the second control transistor CT2 is also turned on. The first end of the second control transistor CT2 is coupled to the voltage source VDD, and the second end of the second control transistor CT2 is connected to the control node X. When the second control transistor CT2 is turned on / conducted according to the high voltage level provided by the G(N + 2)-th stage driving signal, the current supplied from the voltage source VDD can flow through the turned-on / conducted second control transistor CT2 to input a high voltage level to the control node X.

[0030] The control terminal of the third control transistor CT3 is connected to the signal generation circuit GCS. For the convenience of explaining the signal change at the control terminal of the third control transistor CT3, it is called the signal node Q. The first terminal of the third control transistor CT3 is connected to the second terminal of the first control transistor CT1, that is, the first terminal of the third control transistor CT3 is connected to the control node X. The second terminal of the third control transistor CT3 is coupled to the first voltage level VSS2. In this embodiment, the first voltage level VSS2 is -18 volts, but it is not limited to this range. When the third control transistor CT3 is turned on / conducted according to the high voltage level provided by the signal generation circuit GCS, the current supplied from the second terminal of the first control transistor CT1 can flow through the turned-on / conducted third control transistor CT3, pulling down the control node X to the first voltage level VSS2, that is, the potential of the control node X is pulled down to -18 volts.

[0031] The control terminal of the fourth control transistor CT4 is connected to the second terminal of the first control transistor CT1, that is, the control terminal of the fourth control transistor CT4 is connected to the control node X. The first terminal of the fourth control transistor CT4 is connected to the control terminal of the third control transistor CT3, that is, the first terminal of the fourth control transistor CT4 is connected to the signal node Q. The second terminal of the fourth control transistor CT4 is coupled to the first voltage level VSS2, that is, -18 volts. When the fourth control transistor CT4 is turned on / conducted according to the high voltage level provided by the second terminal of the first control transistor CT1, the current supplied from the signal generation circuit GCS can flow through the turned-on / conducted fourth control transistor CT4, pulling down the signal node Q to the first voltage level VSS2, that is, the potential of the signal node Q is pulled down to -18 volts.

[0032] The first terminal of the signal generation circuit GCS is coupled to the first frequency signal ECK. The second terminal of the signal generation circuit GCS is connected to the control terminal of the third control transistor CT3, that is, the second terminal of the signal generation circuit GCS is connected to the signal node Q. The third terminal of the signal generation circuit GCS is connected to the second terminal of the first control transistor CT1. The fourth terminal of the signal generation circuit GCS is coupled to the first voltage level VSS2, that is, -18 volts. The signal generation circuit GCS can be composed of multiple transistors and generates the first control signal SQN according to the high voltage level signal provided by the first frequency signal ECK.

[0033] Next, each anti-noise control circuit ANC in the capacitorless driver circuit provides the first control signal SQN to the N output circuits. As Figure 1As shown, an anti-noise control circuit ANC provides a first control signal SQN to four output circuits. However, in the present invention, the anti-noise control circuit ANC and the output circuit OUT are not limited to a 1-to-4 relationship. Further elaborating on the connection relationship of each component in one of the output circuits OUT, the Nth-level output circuit OUT(N) includes a first transistor M11, a second transistor M12, a third transistor M13, and a fourth transistor M14. The (N + 1)th-level output circuit OUT(N + 1) includes a first transistor M21, a second transistor M22, a third transistor M23, and a fourth transistor M24. The (N + 2)th-level output circuit OUT(N + 2) includes a first transistor M31, a second transistor M32, a third transistor M33, and a fourth transistor M34. The (N + 3)th-level output circuit OUT(N + 3) includes a first transistor M41, a second transistor M42, a third transistor M43, and a fourth transistor M44.

[0034] The first control terminal of the first transistor M11 is connected to the control terminal of the third control transistor CT3, that is, the first control terminal of the first transistor M11 is connected to the second terminal of the signal generation circuit GCS. The second control terminal of the first transistor M11 is connected to the first voltage level VSS2, that is, -18 volts. The first terminal of the first transistor M11 is connected to the bias node A(N) in the output circuit OUT(N), and the voltage change of the bias node A(N) affects the output signal of the output circuit OUT(N). The second terminal of the first transistor M11 is coupled to the second voltage level VSS. In this embodiment, the second voltage level VSS is -12 volts, but it is not limited to this range. When the first transistor M11 is turned on / conducted according to the high voltage level provided by the second terminal of the signal generation circuit GCS, the current supplied from the bias node A(N) can flow through the turned-on / conducted first transistor M11, pulling down the bias node A(N) to the first voltage level VSS2, that is, the electric potential of the bias node A(N) is pulled down to -18 volts. The turning on of the first transistor M11 can provide a path for pulling down the electric potential of the control terminal of the output transistor of the output circuit OUT(N). When the Nth-level output terminal G(N) outputs a low voltage, the first transistor M11 is turned on / conducted according to the high voltage provided by the first control signal SQN. The current supplied from the control terminal of the third transistor M13 flows through the turned-on first transistor M11 to the second voltage level VSS, causing the third transistor M13 that controls the Nth-level output terminal G(N) to be in a closed state, ensuring that there is no noise crosstalk at the Nth-level output terminal G(N). The operating principles of the first transistors M21, M31, and M41 of the (N + 1)th-level output circuit OUT(N + 1) to the (N + 3)th-level output circuit OUT(N + 3) are the same and will not be elaborated here.

[0035] The control terminal of the second transistor M12 is coupled to the first driving signal G(N-4). That is to say, when the first output circuit of the previous anti-noise control circuit ANC, i.e., the (N-4)th stage output circuit, outputs a high voltage to the G(N-4)th stage driving signal, the second transistor M12 is also turned on. The first terminal of the second transistor M12 is coupled to the first scanning signal U2D, i.e., the forward scanning signal U2D. The second terminal of the second transistor M12 is connected to the first terminal of the first transistor M11, i.e., the second terminal of the second transistor M12 is connected to the bias node A(N). When the second transistor M12 is turned on / conducted according to the high voltage level provided by the first driving signal G(N-4), the current supplied from the forward scanning signal U2D can flow through the turned-on / conducted second transistor M12 to charge the bias node A(N). The operating principles of the second transistors M22, M32, and M42 of the (N+1)th stage output circuit OUT(N+1) to the (N+3)th stage output circuit OUT(N+3) are the same and will not be elaborated here.

[0036] The control terminal of the third transistor M13 is connected to the first terminal of the first transistor M11, i.e., the control terminal of the third transistor M13 is coupled to the bias node A(N). The first terminal of the third transistor M13 is coupled to the second frequency signal CLK1, and the second terminal of the third transistor M13 is connected to the (N)th stage output terminal G(N). When the third transistor M13 is turned on / conducted according to the high voltage level provided by the bias node A(N), the current supplied from the second frequency signal CLK1 can flow through the turned-on / conducted third transistor M13 to output a high voltage level to the output terminal G(N). The operating principles of the third transistors M23, M33, and M43 of the (N+1)th stage output circuit OUT(N+1) to the (N+3)th stage output circuit OUT(N+3) are the same and will not be elaborated here.

[0037] The control terminal of the fourth transistor M14 is connected to the control terminal of the third control transistor CT3, i.e., the control terminal of the fourth transistor M14 is connected to the second terminal of the signal generation circuit GCS. The first terminal of the fourth transistor M14 is connected to the output terminal of the (N)th stage output circuit, and the second terminal of the fourth transistor M14 is coupled to the second voltage level VSS, i.e., -12 volts. When the fourth transistor M14 is turned on / conducted according to the high voltage level provided by the second terminal of the signal generation circuit GCS, the output terminal G(N) is pulled down to the second voltage level VSS, ensuring that the (N)th stage output terminal G(N) is not affected by the noise crosstalk from the second frequency signal CLK1. The operating principles of the fourth transistors M24, M34, and M44 of the (N+1)th stage output circuit OUT(N+1) to the (N+3)th stage output circuit OUT(N+3) are the same and will not be elaborated here.

[0038] Figure 2 It is the circuit layout diagram of the anti-noise control circuit of this embodiment. As Figure 2As shown, the anti-noise control circuit ANC further includes a fifth control transistor CT5, a sixth control transistor CT6, a seventh control transistor CT7, a complementary signal generation circuit GCSX, an eighth control transistor CT8, and a ninth control transistor CT9.

[0039] The control terminal of the fifth control transistor CT5 is coupled to the third driving signal, that is, coupled to the G(N + 7)th stage driving signal. When the fourth output circuit of the next anti-noise control circuit ANC, that is, the (N + 7)th stage output circuit, outputs a high voltage to the G(N + 7)th stage driving signal, the fifth control transistor CT5 of the first anti-noise control circuit ANC is also turned on. The first terminal of the fifth control transistor CT5 is connected to the second terminal of the first control transistor CT1, that is, connected to the control node X. The second terminal of the fifth control transistor CT5 is coupled to the second scanning signal, that is, the reverse scan signal D2U. When the fifth control transistor CT5 is turned on / conducted according to the high voltage level provided by the G(N + 7)th stage driving signal, the current supplied from the control node X can flow through the turned-on / conducted fifth control transistor CT5, pulling down the control node X to a low voltage level.

[0040] The control terminal of the sixth control transistor CT6 is coupled to the fourth driving signal, that is, coupled to the G(N - 1)th stage driving signal. When the fourth output circuit of the previous anti-noise control circuit ANC, that is, the (N - 1)th stage output circuit, outputs a high voltage to the G(N - 1)th stage driving signal, the sixth control transistor CT6 of the first anti-noise control circuit ANC is also turned on. The first terminal of the sixth control transistor CT6 is coupled to the voltage source VDD. The second terminal of the sixth control transistor CT6 is connected to the second terminal of the first control transistor CT1, that is, connected to the control node X. When the sixth control transistor CT6 is turned on / conducted according to the high voltage level provided by the G(N - 1)th stage driving signal, the current supplied from the voltage source VDD can flow through the turned-on / conducted sixth control transistor CT6 to output a high voltage level to the control node X.

[0041] The control terminal of the seventh control transistor CT7 is coupled to the fifth driving signal G(N + 4), that is, coupled to the G(N + 4)th stage driving signal. The first terminal of the seventh control transistor CT7 is coupled to the voltage source VDD. The second terminal of the seventh control transistor CT7 is connected to the second terminal of the first control transistor CT1, that is, connected to the control node X. When the seventh control transistor CT7 is turned on / conducted according to the high voltage level provided by the G(N + 4)th stage driving signal, the current supplied from the voltage source VDD can flow through the turned-on / conducted seventh control transistor CT7 to output a high voltage level to the control node X.

[0042] The first terminal of the complementary signal generation circuit GCSX receives a third frequency signal EXCK, the second terminal of the complementary signal generation circuit GCSX outputs a second control signal SQNX, the third terminal of the complementary signal generation circuit GCSX is connected to the second terminal of the first control transistor CT1, and the fourth terminal of the complementary signal generation circuit GCSX is coupled to a first voltage level VSS2. The complementary signal generation circuit GCSX can be composed of multiple transistors and generates the second control signal SQNX based on the third frequency signal EXCK.

[0043] The control terminal of the eighth control transistor CT8 is connected to the second terminal of the complementary signal generation circuit GCSX. When the first terminal of the eighth control transistor CT8 is connected to the second terminal of the first control transistor CT1, that is, connected to the control node X. The second terminal of the eighth control transistor CT8 is coupled to the first voltage level VSS2. The complementary signal generation circuit GCSX generates the second control signal SQNX based on the third frequency signal EXCK, and the second terminal of the complementary signal generation circuit GCSX outputs the second control signal SQNX. When the eighth control transistor CT8 is turned on / conducted according to the high voltage level provided by the second control signal SQNX, the current supplied from the control node X can flow through the turned-on / conducted eighth control transistor CT8, pulling down the control node X to the first voltage level VSS2.

[0044] The control terminal of the ninth control transistor CT9 is connected to the second terminal of the first control transistor CT1, that is, connected to the control node X. The first terminal of the ninth control transistor CT9 is coupled to the second terminal of the complementary signal generation circuit GCSX. The second terminal of the ninth control transistor CT9 is coupled to the first voltage level VSS2. The complementary signal generation circuit GCSX generates the second control signal SQNX based on the third frequency signal EXCK, and the second terminal of the complementary signal generation circuit GCSX outputs the second control signal SQNX. When the ninth control transistor CT9 is turned on / conducted according to the high voltage level provided by the control node X, the current supplied from the second control signal SQNX can flow through the turned-on / conducted ninth control transistor CT9, pulling down the signal node Q to the first voltage level VSS2.

[0045] Figures 3A to 3D It is the circuit layout diagram of the Nth-stage output circuit to the (N + 3)th-stage output circuit of this embodiment. As Figures 3A to 3D shown, the Nth-stage output circuit further includes a fifth transistor M15, a sixth transistor M16, a seventh transistor M17, and an eighth transistor M18.

[0046] The first control terminal of the fifth transistor M15 is connected to the second terminal of the complementary signal generation circuit GCSX. The second control terminal of the fifth transistor M15 is coupled to the first voltage level VSS2. The first terminal of the fifth transistor M15 is connected to the first terminal of the first transistor M11, that is, coupled to the bias node A(N). The second terminal of the fifth transistor M15 is coupled to the second voltage level VSS. The complementary signal generation circuit GCSX generates a second control signal SQNX according to the third frequency signal EXCK, and the second terminal of the complementary signal generation circuit GCSX outputs the second control signal SQNX. When the fifth transistor M15 is turned on / conducted according to the high voltage level provided by the second control signal SQNX, the current supplied from the bias node A(N) can flow through the turned-on / conducted fifth transistor M15, pulling down the bias node A(N) to the second voltage level VSS.

[0047] The first control terminal of the sixth transistor M16 is coupled to the fifth drive signal G(N + 4), that is, coupled to the G(N + 4)-th stage drive signal. The second control terminal of the sixth transistor M16 is coupled to the first voltage level VSS2. The first terminal of the sixth transistor M16 is connected to the first terminal of the first transistor M11, that is, connected to the bias node A(N). The second terminal of the sixth transistor M16 is coupled to the second scan signal D2U, that is, the reverse scan signal D2U. When the sixth transistor M16 is turned on / conducted according to the high voltage level provided by the G(N + 4)-th stage drive signal, the current supplied from the bias node A(N) can flow through the turned-on / conducted sixth transistor M16, pulling down the bias node A(N) to the second voltage level VSS.

[0048] The control terminal of the seventh transistor M17 is connected to the second terminal of the complementary signal generation circuit GCSX. The first terminal of the seventh transistor M17 is connected to the output terminal G(N). The second terminal of the seventh transistor M17 is coupled to the second voltage level VSS. The complementary signal generation circuit GCSX generates a second control signal SQNX according to the third frequency signal EXCK, and the second terminal of the complementary signal generation circuit GCSX outputs the second control signal SQNX. When the control terminal of the seventh transistor M17 is turned on / conducted according to the high voltage level provided by the second control signal SQNX, the current supplied from the output terminal G(N) can flow through the turned-on / conducted seventh transistor M17, pulling down the output terminal G(N) to the second voltage level VSS.

[0049] The first control terminal of the eighth transistor M18 is coupled to the reset signal RST. The second control terminal of the eighth transistor M18 is coupled to the first voltage level VSS2. The first terminal of the eighth transistor M18 is connected to the first terminal of the first transistor M11, that is, connected to the bias node A(N). The second terminal of the eighth transistor M18 is coupled to the second voltage level VSS. When the eighth transistor M18 is turned on / conducted according to the high voltage level provided by the reset signal RST, the current supplied from the bias node A(N) can flow through the turned-on / conducted eighth transistor M18, pulling down the bias node A(N) to the second voltage level VSS.

[0050] Next, the operation of the capacitorless driver circuit can be divided into four time intervals, and the four time intervals include a pre-charge period T1, an output stage gate signal period T2, a stage gate signal pull-down period T3, and a stage gate signal holding low voltage potential period T4.

[0051] During the pre-charge period T1, the G(N - 4)th stage drive signal is at a high voltage level, and the control terminals of the first control transistor CT1 and the second transistor M12 are coupled to the G(N - 4)th stage drive signal. When the first control transistor CT1 is turned on / conducted according to the signal at the control terminal, the current supplied from the positive scan signal U2D can flow through the turned-on / conducted first control transistor CT1 to charge the control node X. At this time, the control node X located at the control terminal of the fourth control transistor CT4 has a high potential. When the fourth control transistor CT4 is turned on / conducted according to the signal at the control terminal, the fourth control transistor CT4 pulls down the voltage level of the signal node Q to the first voltage level VSS2. At the same time, the control terminal of the third control transistor CT3 is coupled to the signal node Q. Since the voltage level of the signal node Q is pulled down to the first voltage level VSS2, the third control transistor CT3 is turned off, that is, the discharge path of the control node X coupled to the first terminal of the third control transistor CT3 is turned off.

[0052] At this time, the control terminal of the first transistor M11 is coupled to the signal node Q. Since the voltage level of the signal node Q is pulled down to the first voltage level VSS2, the first transistor M11 is turned off, that is, the discharge path of the bias node A(N) coupled to the first terminal of the first transistor M11 is turned off. At the same time, the control terminal of the fourth transistor M14 is coupled to the signal node Q. Since the voltage level of the signal node Q is pulled down to the first voltage level VSS2, the fourth transistor M14 is turned off, that is, the discharge path of the output terminal coupled to the first terminal of the fourth transistor M14 is turned off.

[0053] That is to say, during the pre-charging period T1, the control node X and the bias node A(N) respectively have high voltage levels due to the first control transistor CT1 and the second transistor M12 that are coupled to the G(N-4)-th stage driving signal through their control terminals being turned on. And the signal node Q has a low voltage level due to the fourth control transistor CT4 that is coupled to the control node X through its control terminal being turned on. The third control transistor CT3, the first transistor M11, and the fourth transistor M14 whose control terminals are coupled to the signal node Q are turned off, that is, all discharge paths of the anti-noise control circuit ANC and each output circuit are turned off.

[0054] The G(N-4)-th stage driving signal is at a high voltage level. When the control terminal of the second transistor M12 is coupled to the G(N-4)-th stage driving signal and the second transistor M12 is turned on / conducted according to the signal at the control terminal, the current supplied from the positive sweep signal U2D can flow through the turned-on / conducted second transistor M12 to charge the bias node A(N).

[0055] During the period T2 of outputting gate signals of each stage, the G(N+2)-th stage driving signal is at a high voltage level. The control terminal of the second control transistor CT2 is coupled to the G(N+2)-th stage driving signal. When the second control transistor CT2 is turned on / conducted according to the signal at the control terminal, the current supplied from the voltage source VDD can flow through the turned-on / conducted second control transistor CT2 to continuously charge the control node X. At this time, the control node X located at the control terminal of the fourth control transistor CT4 has a high electric potential. When the fourth control transistor CT4 is turned on / conducted according to the signal at the control terminal, the voltage level of the signal node Q is pulled down to the first voltage level VSS2 by the fourth control transistor CT4. At the same time, the control terminal of the third control transistor CT3 is coupled to the signal node Q. Since the voltage level of the signal node Q is pulled down to the first voltage level VSS2, the third control transistor CT3 is turned off, that is, the discharge path of the control node X coupled to the first end of the third control transistor CT3 is turned off.

[0056] At this time, the control terminal of the first transistor M11 is coupled to the signal node Q. Since the voltage level of the signal node Q is pulled down to the first voltage level VSS2, the first transistor M11 is turned off, that is, the discharge path of the bias node A(N) coupled to the first end of the first transistor M11 is turned off. At the same time, the control terminal of the fourth transistor M14 is coupled to the signal node Q. Since the voltage level of the signal node Q is pulled down to the first voltage level VSS2, the fourth transistor M14 is turned off, that is, the discharge path of the output terminal coupled to the first end of the fourth transistor M14 is turned off.

[0057] Since the discharge paths of the Nth-stage output circuit for the bias node A(N) are all closed, the bias node A(N) maintains the same high voltage level as that during T1 of the pre-charge period. At this time, when the third transistor M13 is turned on / conducted according to the high voltage level provided by the bias node A(N), the current supplied from the second frequency signal CLK1 can flow through the turned-on / conducted third transistor M13 to output a high voltage level to the output terminal G(N) of the Nth-stage output circuit. At the same time, the control terminal of the fourth transistor M14 is coupled to the signal node Q. Since the voltage level of the signal node Q is pulled down to the first voltage level VSS2, the fourth transistor M14 is turned off, that is, the discharge path of the output terminal coupled to the first end of the fourth transistor M14 is closed.

[0058] During the period T2 of outputting the gate signals of each stage, the bias nodes A(N + 1), A(N + 2), and A(N + 3) in the (N + 1)th-stage output circuit, the (N + 2)th-stage output circuit, and the (N + 3)th-stage output circuit have been charged to a high voltage level during the pre-charge period T1. Since the control terminals of the third transistors M23, M33, and M43 located in the (N + 1)th-stage output circuit, the (N + 2)th-stage output circuit, and the (N + 3)th-stage output circuit are coupled to the bias nodes A(N + 1), A(N + 2), and A(N + 3) in the (N + 1)th-stage output circuit, the (N + 2)th-stage output circuit, and the (N + 3)th-stage output circuit respectively, when the third transistors M23, M33, and M43 are turned on / conducted according to the high voltage levels provided by the bias nodes A(N + 1), A(N + 2), and A(N + 3), the currents supplied from the multiple frequency signals CLK2, CLK3, and CLK4 can flow through the turned-on / conducted third transistors M23, M33, and M43 to output a high voltage level to the output terminals G(N + 1), G(N + 2), and G(N + 3) of the (N + 1)th-stage output circuit, the (N + 2)th-stage output circuit, and the (N + 3)th-stage output circuit respectively.

[0059] During the period T3 when the gate signals of each stage are pulled down, the voltage levels of the output circuits of each stage are pulled down from the high voltage level to the second voltage level VSS. Specifically, an anti-noise control circuit ANC provides a high voltage level to turn on the fourth transistors M14, M24, M34, and M44 connected to the output terminals G(N), G(N + 1), G(N + 2), and G(N + 3) respectively, so that the output terminals G(N), G(N + 1), G(N + 2), and G(N + 3) are pulled down to the second voltage level VSS, that is, -12 volts.

[0060] First, it should be noted that an anti-noise control circuit ANC provides a high voltage level through a signal generation circuit GCS. During the pull-down period T3 of each stage gate signal, the first frequency signal ECK is at a high voltage level. The first end of the signal generation circuit GCS receives the first frequency signal ECK. The signal generation circuit GCS generates a first control signal SQN based on the first frequency signal ECK and outputs it to the second end of the signal generation circuit GCS (i.e., the signal node Q), that is, outputs it to the control ends of the fourth transistors M14, M24, M34, and M44.

[0061] During the pull-down period T3 of each stage gate signal, the fourth transistors M14, M24, M34, and M44 located in the (N + 1)-th stage output circuit, the (N + 2)-th stage output circuit, and the (N + 3)-th stage output circuit are turned on due to the high voltage level provided by coupling the control ends to the signal node Q, causing the output terminals G(N + 1), G(N + 2), and G(N + 3) to be pulled down to the second voltage level VSS. It can be seen that in this embodiment, the capacitorless driver circuit can optimize the distribution area of the fourth transistors M14, M24, M34, and M44 in the GOA circuit and effectively reduce the area of the overall driver circuit because it uses a single path for charging and discharging.

[0062] At the same time, since the signal node Q is at a high voltage level, when the first transistor M11 is turned on / conducted according to the high voltage level provided by the signal node Q, the current supplied from the bias node A(N) can flow through the turned-on / conducted first transistor M11, causing the bias node A(N) to be pulled down to the first voltage level VSS2, that is, the potential of the bias node A(N) is pulled down to -18 volts.

[0063] At the same time, the control end of the sixth transistor M16 is coupled to the driving signal of the G(N + 4)-th stage. The first end of the sixth transistor M16 is coupled to the bias node A(N), and the second end of the sixth transistor M16 is coupled to a low voltage. When the driving signal of the G(N + 4)-th stage is at a high voltage level and the sixth transistor M16 is turned on / conducted according to the high voltage level provided by the driving signal of the G(N + 4)-th stage, the potential of the bias node A(N) is pulled down to the first voltage level VSS2.

[0064] At the same time, the first control end of the eighth transistor M18 is coupled to the reset signal RST. The first end of the eighth transistor M18 is coupled to the bias node A(N), and the second end of the eighth transistor M18 is coupled to the second voltage level VSS. When the reset signal RST is at a high voltage level and the eighth transistor M18 is turned on / conducted according to the high voltage level provided by the reset signal RST, the potential of the bias node A(N) is pulled down to the first voltage level VSS2.

[0065] During T4 when the gate signals at all levels maintain a low voltage potential, in the capacitive driverless circuit, multiple transistors that pull down the potential must be turned off or the high-potential end of the pull-down transistor must be pulled down so that each output terminal G(N), G(N + 1), G(N + 2), G(N + 3) maintains a low voltage.

[0066] First, the control terminal of the fifth control transistor CT5 is coupled to the G(N + 7)-th stage driving signal, the first terminal of the fifth control transistor CT5 is coupled to the second scan signal, i.e., the reverse scan signal D2U. The second terminal of the fifth control transistor CT5 is coupled to the control node X. When the G(N + 7)-th stage driving signal is at a high voltage level, when the fifth control transistor CT5 is turned on / conducted according to the high voltage level provided by the G(N + 7)-th stage driving signal, the potential of the control node X is pulled down to a low voltage level.

[0067] Next, it is confirmed that multiple control transistors coupled to the control node X are turned off and cannot input any high voltage level to the control node X. The control terminals of the first control transistor CT1, the second control transistor CT2, and the fourth control transistor CT4 are respectively coupled to the G(N - 1)-th stage driving signal, the G(N + 2)-th stage driving signal, and the G(N + 4)-th stage driving signal. At this time, the G(N - 1)-th stage driving signal, the G(N + 2)-th stage driving signal, and the G(N + 4)-th stage driving signal are at low voltage levels. Therefore, the first control transistor CT1, the second control transistor CT2, and the fourth control transistor CT4 are in an off state.

[0068] At this time, the potential of the control node X is at a low voltage level. The control terminal of the fourth control transistor CT4 is coupled to the control node X, and the fourth control transistor CT4 is in an off state. Therefore, the signal node Q coupled to the first terminal of the fourth control transistor CT4 is the same as that during T3 when the gate signals at all levels are pulled down, and is still at a high voltage level.

[0069] The first terminal of the third control transistor CT3 is coupled to the control node X, and the control terminal of the third control transistor CT3 is coupled to the signal node Q. At this time, when the third control transistor CT3 is turned on / conducted according to the high voltage level provided by the signal node Q, the current supplied from the control node X can flow through the turned-on / conducted third control transistor CT3, pulling down the control node X to the first voltage level VSS2.

[0070] When the first transistor M11 is turned on / conducted according to the high voltage level provided by the signal node Q, the current supplied from the bias node A(N) can flow through the turned-on / conducted first transistor M11, pulling down the bias node A(N) to the first voltage level VSS2, that is, the potential of the bias node A(N) is pulled down to -18 volts.

[0071] At this time, the driving signal of the G(N + 4)th stage is at a low voltage level. The control terminal of the sixth transistor M16 is coupled to the driving signal of the G(N + 4)th stage being at a low voltage level, causing the sixth transistor M16 to be in an off state.

[0072] Although it has been confirmed so far that during the period when each stage of the gate signal maintains a low voltage potential T4, each transistor for pulling down is either off or one end of the transistor is pulled down to a low voltage level. However, when no capacitive driver circuit is applied to the display gate circuit, taking the output terminal of the Nth stage as an example, the output terminal of the Nth stage is at a low voltage for most of the time. That is to say, in the output circuit of the Nth stage, the transistor used for anti-noise must maintain a low voltage for a long time, which easily causes the anti-noise transistor to crack within a short time. The application scope of the capacitive-less driver circuit of this embodiment is not limited to this. This embodiment solves the problem that the transistor for anti-noise fails due to long-term operation through two sets of chargeable anti-noise architectures.

[0073] The second terminal of the fourth control transistor CT4 is coupled to the first voltage level VSS2, that is, -18 volts. When the fourth control transistor CT4 is turned on / conducted according to the high voltage level provided by the control node X, the current supplied from the signal node Q can flow through the turned-on / conducted fourth control transistor CT4, pulling down the signal node Q to the first voltage level VSS2, that is, the potential of the signal node Q is pulled down to -18 volts. When the signal node Q is at a low voltage level, the control terminal of the fourth transistor M14 is connected to the signal node Q, causing the fourth transistor M14 to turn off. And the first terminal of the fourth transistor M14 is connected to the output terminal G(N). Since the fourth transistor M14 is turned off, the output terminal G(N) maintains its original voltage level. Therefore, in the non-working state, when the output terminal G(N) is pulled down to a low level, since the fourth transistor M14 is turned off, the scan line connected to the output terminal G(N) can be continuously maintained at a low voltage, that is, the transistors connected to this scan line in the display area are all turned off, thus ensuring the stability of the liquid crystal voltage value.

[0074] [Advantages of the Embodiment]

[0075] One of the beneficial effects of the present utility model is that a capacitive-less driver circuit of a display device provided by the present utility model includes at least one anti-noise control circuit and a plurality of output circuits. The plurality of output circuits share one anti-noise control circuit, enabling the anti-noise control circuit of a single block to have multiple functions. And the technical feature of omitting capacitors in the capacitive-less driver circuit can reduce the number of transistors used in the driver circuit. The sharing of the anti-noise control circuit by the plurality of output circuits and the capacitive-less circuit design both significantly reduce the layout area of the circuit, effectively narrowing the border of the display, and simultaneously achieving the effects of anti-noise and stable output signal.

[0076] In the present utility model, multiple transistors in the anti-noise control circuit and the output circuit have a double gate structure. The second control terminal in the double gate structure, i.e., the top gate, is coupled to a lower voltage level VSS2. This technical feature can solve the problem that in a capacitorless driver circuit at high temperatures, the transistor connected to the pre-charge point (node A(N)) leaks due to the fast speed of hot carriers, resulting in an extended falling time of the output waveform. By coupling the top gate to the lower voltage level VSS2, this negative bias compensation mechanism can make the anti-noise transistor more stable during the non-operating period. That is to say, the negative bias compensation mechanism ensures that the anti-noise transistor is turned off and will not cause malfunction of the output circuit due to leakage. Furthermore, the reliability of the product is improved under long-term operation.

[0077] Since the use of anti-noise transistors requires maintaining a low voltage for a long time, it is easy for the anti-noise transistors to crack within a short period. Through the alternating use of two sets of charge-type anti-noise architectures in the present utility model, the anti-noise transistors can operate throughout the entire period without accelerating the deterioration of the components, achieving excellent anti-noise effects and stability. Moreover, even when operating for a long time in a high-temperature environment, the product can still operate normally, thereby improving the reliability of the product.

[0078] The content disclosed above is only the preferred and feasible embodiment of the present utility model, and does not limit the protection scope of the claims of the present utility model. Therefore, all equivalent technical changes made by using the content of the specification and drawings of the present utility model are included in the protection scope of the claims of the present utility model.

Claims

1. A capacitive driver circuit for a display device, characterized in that: include: An anti-noise control circuit, comprising: a first control transistor, wherein a control terminal of the first control transistor receives a first driving signal, and a first terminal of the first control transistor receives a first scanning signal; a second control transistor, wherein a control terminal of the second control transistor receives a second driving signal, a first terminal of the second control transistor is connected to a voltage source, and a second terminal of the second control transistor is connected to a second terminal of the first control transistor; a third control transistor, wherein a first terminal of the third control transistor is connected to the second terminal of the first control transistor, and a second terminal of the third control transistor is coupled to a first voltage level; a fourth control transistor, wherein a control terminal of the fourth control transistor is connected to the second terminal of the first control transistor, a first terminal of the fourth control transistor is connected to the control terminal of the third control transistor, and a second terminal of the fourth control transistor is coupled to the first voltage level; and a signal generating circuit configured to generate a first control signal to the control terminal of the third control transistor according to a first frequency signal; and A plurality of output circuits are electrically connected to the anti-noise control circuit, each of the output circuits comprising: a first transistor, wherein a first control terminal of the first transistor is connected to the control terminal of the third control transistor, a second terminal of the first transistor is coupled to a second voltage level, and a second control terminal of the first transistor is coupled to the first voltage level; a second transistor, wherein a first terminal of the second transistor receives the first scanning signal, a second terminal of the second transistor is connected to the first terminal of the first transistor, and a control terminal of the second transistor receives the first driving signal; a third transistor, wherein a first end of the third transistor receives a second frequency signal, a second end of the third transistor is connected to an output end of the output circuit, and a control end of the third transistor is connected to a first end of the first transistor; a fourth transistor, wherein a first terminal of the fourth transistor is connected to the output terminal, a control terminal of the fourth transistor is connected to the control terminal of the third control transistor, and a second terminal of the fourth transistor is coupled to the second voltage level.

2. The capacitive driver circuit of a display device according to claim 1, characterized in that: The anti-noise control circuit also includes: a fifth control transistor, wherein a control end of the fifth control transistor receives a third driving signal, a first end of the fifth control transistor is connected to a second end of the first control transistor, and a second end of the fifth control transistor is connected to a second scanning signal; a sixth control transistor, wherein a control terminal of the sixth control transistor receives a fourth driving signal, a first terminal of the sixth control transistor is connected to the voltage source, and a second terminal of the sixth control transistor is connected to the second terminal of the first control transistor; a seventh control transistor, wherein a control terminal of the seventh control transistor receives a fifth driving signal, a first terminal of the seventh control transistor is connected to the voltage source, and a second terminal of the seventh control transistor is connected to the second terminal of the first control transistor.

3. The capacitive-free driver circuit of a display device according to claim 2, characterized in that: The first end of the signal generating circuit receives the first frequency signal, the second end and the third end of the signal generating circuit are respectively connected to the control end of the third control transistor and the second end of the first control transistor, and the fourth end of the signal generating circuit is coupled to the first voltage level; the first control signal is output from the second end of the signal generating circuit.

4. The capacitive-free driver circuit of a display device according to claim 3, characterized in that: The anti-noise control circuit also includes: a complementary signal generating circuit, wherein a first terminal of the complementary signal generating circuit receives a third frequency signal, a second terminal of the complementary signal generating circuit outputs a second control signal, a third terminal of the complementary signal generating circuit is connected to the second terminal of the first control transistor, and a fourth terminal of the complementary signal generating circuit is coupled to the first voltage level; The complementary signal generating circuit generates the second control signal according to the third frequency signal.

5. The capacitive-free driver circuit of a display device according to claim 4, characterized in that: The anti-noise control circuit also includes: an eighth control transistor, wherein the control end of the eighth control transistor is connected to the second end of the complementary signal generating circuit, the first end of the eighth control transistor is connected to the second end of the first control transistor, and the second end of the eighth control transistor is coupled to the first voltage level.

6. The capacitive-free driver circuit of a display device according to claim 5, characterized in that: The anti-noise control circuit also includes: a ninth control transistor, wherein the control end of the ninth control transistor is connected to the second end of the first control transistor, the first end of the ninth control transistor is connected to the second end of the complementary signal generating circuit, and the second end of the ninth control transistor is coupled to the first voltage level.

7. The capacitive-free driver circuit of a display device according to claim 4, characterized in that: Each of the output circuits further comprises: A fifth transistor, wherein the first control end of the fifth transistor is connected to the second end of the complementary signal generating circuit, the second control end of the fifth transistor is coupled to the first voltage level, the first end of the fifth transistor is connected to the first end of the first transistor, and the second end of the fifth transistor is coupled to the second voltage level.

8. The capacitor-free driver circuit of a display device according to claim 7, characterized in that: Each of the output circuits further comprises: A sixth transistor, wherein the first control end of the sixth transistor receives the fifth driving signal, the second control end of the sixth transistor is coupled to the first voltage level, the first end of the sixth transistor is connected to the first end of the first transistor, and the second end of the sixth transistor receives the second scanning signal.

9. The capacitor-free driver circuit of a display device according to claim 8, characterized in that: Each of the output circuits further comprises: a seventh transistor, wherein a control end of the seventh transistor is connected to the second end of the complementary signal generating circuit, a first end of the seventh transistor is connected to the output end, and a second end of the seventh transistor is coupled to the second voltage level.

10. The capacitor-free driver circuit of a display device according to claim 9, characterized in that: Each of the output circuits further comprises: An eighth transistor, wherein the first control terminal of the eighth transistor receives a reset signal, the second control terminal of the eighth transistor is coupled to the first voltage level, the first terminal of the eighth transistor is connected to the first terminal of the first transistor, and the second terminal of the eighth transistor is coupled to the second voltage level.

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