Double-PXIe interface 25G Ethernet simulation test card with specific inter-board connection structure

Abstract

The utility model discloses a double-PXIe interface 25G Ethernet simulation test card with a specific inter-board connection structure, which is characterized in that an FPGA (Field Programmable Gate Array) and auxiliary functional devices thereof are arranged on an upper-layer PCB (Printed Circuit Board), a D2000 / 8 industrial CPU (Central Processing Unit) and auxiliary functional devices thereof are arranged on a lower-layer PCB, and the D2000 / 8 industrial CPU and the auxiliary functional devices thereof are arranged on the lower-layer PCB. And after the upper-layer inter-board connector and the lower-layer inter-board connector are mutually plugged, the electrical connection between the FPGA and the auxiliary functional device thereof and the D2000 / 8 industrial CPU and the auxiliary functional device thereof is realized. According to the 25G Ethernet simulation test board card provided by the utility model, a solution of a 25G Ethernet simulation test board card designed by adopting an upper-layer board card structure and a lower-layer board card structure is adopted, and an original large-area single 25G Ethernet simulation test board card is converted into the 25G Ethernet simulation test board card adopting the upper-layer board card structure and the lower-layer board card structure; and the specific inter-board connector is adopted to realize electrical connection between the upper-layer FPGA board card and the lower-layer D2000 / 8 board card.

Description

Technical Field

[0001] The utility model relates to a dual-PXIe interface 25G Ethernet simulation test card with a specific inter-board connection structure, belonging to the technical field of avionics systems. Background Art

[0002] In the application scenario of airborne avionics systems, due to the volume limitation of the cabin itself and the extremely large number of electronic devices, the space available for various electronic devices in the cabin is very small. This application scenario has greatly squeezed the 25G Ethernet simulation test card that originally required a large-area circuit board design. The original large-area single 25G Ethernet simulation test card design cannot meet the application in a small volume space. Therefore, there is an urgent need for a structural design that can convert a large-area circuit board into a small-area circuit board, which can not only meet the heat dissipation function of the small-space circuit board structural design, but also meet the board-level signal transmission function of its different high-speed signals and low-speed signals, and should also have highly reliable electrical connection characteristics. Utility Model Content

[0003] The purpose of the utility model is to solve the volume requirement and heat dissipation management demand problems of a dual PXIe interface 25G Ethernet simulation test card in an airborne avionics system application scenario.

[0004] In order to achieve the above-mentioned purpose, the technical solution of the utility model is to provide a dual PXIe interface 25G Ethernet simulation test card with a specific inter-board connection structure, characterized in that the devices on the 25G Ethernet simulation test card are divided into a D2000 / 8 industrial version CPU and its affiliated functional devices and an FPGA and its affiliated functional devices, the FPGA and its affiliated functional devices are arranged on an upper PCB board, the D2000 / 8 industrial version CPU and its affiliated functional devices are arranged on a lower PCB board, an upper inter-board connector which is circuit-connected with the FPGA and its affiliated functional devices is provided on the upper PCB board, and a lower inter-board connector which is circuit-connected with the D2000 / 8 industrial version CPU and its affiliated functional devices is provided on the lower PCB board, and the upper inter-board connector and the lower inter-board connector are plugged into each other to realize the electrical connection between the FPGA and its affiliated functional devices and the D2000 / 8 industrial version CPU and its affiliated functional devices.

[0005] Preferably, the model of the upper inter-board connector is ERM8-060-09.0-L-DV-K-TR.

[0006] Preferably, the model of the lower inter-board connector is ERF8-060-09.0-L-DV-K-TR.

[0007] The solution of the 25G Ethernet emulation test board card designed with an upper and lower two-layer board card structure is adopted in the present utility model. The original large-area single 25G Ethernet emulation test board card is converted into a 25G Ethernet emulation test board card with an upper and lower two-layer structure, and the specific inter-board connector is used to realize the electrical connection between the upper-layer FPGA board card and the lower-layer D2000 / 8 board card.

[0008] Compared with the existing technical solution, the beneficial effects of the present utility model are as follows:

[0009] 1. In terms of the utilization of the board card space volume, the new 25G Ethernet emulation test card with an upper and lower two-layer structure greatly reduces the area of the original single-layer 25G Ethernet emulation test card, enabling it to be better embedded in the narrow airborne avionics cabin.

[0010] 2. In terms of the heat dissipation of the board card, the three-dimensional double-layer board card layout can play a good role in space heat dissipation for each chip in the upper and lower two-layer board cards, especially for the heat generated by the large data transmission of the 25G Ethernet emulation test board card.

[0011] 3. In terms of power supply, the height spacing between the two board cards presented after the board connectors of the upper-layer FPGA board card and the board connectors of the lower-layer D2000 / 8 board card are tightly combined and connected can just make the double PXIe interfaces on the sides of the two board cards be inserted into the chassis card slots, so as to achieve the accurate power supply and data communication of the two board cards with the chassis backplane.

[0012] 4. In terms of signal integrity, when the 25G Ethernet emulation test PXIe interface card was originally designed with a single large-area PCB, the FPGA and its attached functional devices and the D2000 / 8 industrial version CPU and its attached functional devices were located in the same PCB layout. The data interaction between the two functional modules simultaneously had high-speed transmission communication and low-speed transmission communication. In the PCB design, various impedance design indicators should be strictly controlled to meet the requirements in terms of signal integrity. Now, the electrical connection between the upper-layer FPGA board card and the lower-layer D2000 / 8 board card is realized by adopting the connection method of the inter-board connector, and the parasitic parameters and various impedance matching indicators of the inter-board connector meet the requirements of signal integrity.

[0013] 5. In terms of electronic reliability, the inter-board connector has a tightly engaged structure of the male inter-board connector of the upper-layer FPGA board card and the female inter-board connector of the lower-layer D2000 / 8 board card, which is very suitable for the airborne avionics application scenario with high vibration.

[0014] 6. In terms of maintainability, the board design of the upper and lower layers of the board - to - board connector is adopted. When a fault occurs and needs to be repaired, convenient overall plug - and - play replacement and single - board replacement can be carried out. Brief Description of the Drawings

[0015] Figure 1 The front view of a dual - PXIe interface 25G Ethernet emulation test card with a specific board - to - board connection structure disclosed by the present utility model (without the radiator of the lower - layer D2000 / 8 board);

[0016] Figure 2 The front view of a dual - PXIe interface 25G Ethernet emulation test card with a specific board - to - board connection structure disclosed by the present utility model;

[0017] Figure 3 The bottom view of the upper - layer FPGA board of a dual - PXIe interface 25G Ethernet emulation test card with a specific board - to - board connection structure disclosed by the present utility model;

[0018] Figure 4 The top view of the lower - layer D2000 / 8 board of a dual - PXIe interface 25G Ethernet emulation test card with a specific board - to - board connection structure disclosed by the present utility model. Detailed Embodiments

[0019] The present utility model will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present utility model and not to limit the scope of the present utility model. In addition, it should be understood that after reading the content taught by the present utility model, those skilled in the art can make various changes or modifications to the present utility model, and these equivalent forms also fall within the scope defined by the appended claims of this application.

[0020] A dual PXIe interface 25G Ethernet emulation test card with a specific inter-board connection structure disclosed in this embodiment includes an upper board 1 (hereinafter collectively referred to as the "upper FPGA board") composed of an FPGA and its auxiliary functional devices, and a lower board 2 (hereinafter collectively referred to as the "lower D2000 / 8 board") composed of an industrial version D2000 / 8 CPU and its auxiliary functional devices. The 25G Ethernet emulation test card originally designed with a single large-area PCB is re-layout, separating the FPGA and its auxiliary functional devices from the industrial version D2000 / 8 CPU and its auxiliary functional devices. Considering that the FPGA and its auxiliary functional devices need to be downloaded and debugged by software later, the FPGA and its auxiliary functional devices are placed on the upper board 1. Considering the 25G Ethernet emulation test application scenario, various parameter indicators are strictly controlled in the upper and lower two-layer PCB designs to meet the signal integrity requirements. In this 25G Ethernet emulation test application scenario, while taking into account various indicators such as the original high-speed transmission communication and low-speed transmission communication, considering that the accurate height of the inter-board connector can enable the side dual PXIe interfaces to be accurately inserted into the chassis card slot to achieve board power supply and communication, the inter-board connector 3 with the model number ERM8-060-09.0-L-DV-K-TR is selected and placed on the bottom surface of the upper FPGA board, as Figure 3 shown. The inter-board connector 4 with the model number ERF8-060-09.0-L-DV-K-TR is selected and placed on the top surface of the lower D2000 / 8 board, as Figure 4 shown.

[0021] The FPGA and its auxiliary functional devices are common knowledge to those skilled in the art. In this embodiment, it includes an FPGA, an MCU, DDR4, FLASH, a PHY, a temperature sensor, an IIC bus, a PCIE bus, a SERDES bus, a PXIe interface, the inter-board connector 3, and a radiator 5. The FPGA is connected to the MCU, DDR4, and FLASH. At the same time, the FPGA is also connected to the PHY through the SERDES bus. The MCU is connected to the temperature sensor through the IIC bus. The FPGA and its auxiliary functional devices are connected to the PXIe interface on the inter-board connector 3 through the PCIE bus or the IIC bus. The heat dissipation of the FPGA, MCU, DDR4, and PHY is achieved by the radiator 5.

[0022] The D2000 / 8 industrial version CPU and its attached functional devices are common knowledge to those skilled in the art. In this embodiment, it includes a D2000 / 8 industrial version CPU, a CPLD, a FLASH, a UART bus, an IIC bus, an SPI bus, a PCIE bus, a PXIe interface, an inter-board connector 4, and a radiator 6. The D2000 / 8 industrial version CPU is connected to the CPLD via the UART bus, and the CPLD is connected to the FLASH through the SPI bus. The D2000 / 8 industrial version CPU and its attached functional devices are connected to the PXIe interface on the inter-board connector 4 via the PCIE bus or the IIC bus. The radiator 6 is used to dissipate the heat of the D2000 / 8 industrial version CPU and the CPLD.

[0023] The PXIe interface on the inter-board connector 3 is connected to the PXIe interface on the inter-board connector 4, enabling the IIC bus and the SERDES bus on the upper board 1 to communicate with the IIC bus and the SERDES bus circuit on the lower board 2.

[0024] The above-mentioned improved dual PXIe interface 25G Ethernet emulation test card disclosed in this embodiment has now been batch-loaded into the military airborne avionics system cockpit and has received widespread acclaim.

Claims

1. A dual PXIe interface 25G Ethernet simulation test card, characterized in that: The devices on the 25G Ethernet simulation test card are divided into D2000 / 8 industrial version CPU and its auxiliary functional devices and FPGA and its auxiliary functional devices. The FPGA and its auxiliary functional devices are arranged on the upper PCB board, and the D2000 / 8 industrial version CPU and its auxiliary functional devices are arranged on the lower PCB board. The upper PCB board is provided with an upper inter-board connector that is circuit-connected with the FPGA and its auxiliary functional devices, and the lower PCB board is provided with a lower inter-board connector that is circuit-connected with the D2000 / 8 industrial version CPU and its auxiliary functional devices. The upper inter-board connector and the lower inter-board connector are plugged into each other to realize the electrical connection between the FPGA and its auxiliary functional devices and the D2000 / 8 industrial version CPU and its auxiliary functional devices.

2. A dual PXIe interface 25G Ethernet simulation test card as claimed in claim 1, characterized in that: The model of the upper inter-board connector is ERM8-060-09.0-L-DV-K-TR.

3. A dual PXIe interface 25G Ethernet simulation test card as claimed in claim 1, characterized in that: The model of the lower layer inter-board connector is ERF8-060-09.0-L-DV-K-TR.

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