DSI3 interface signal conversion circuit, ultrasonic radar and vehicle

Abstract

The utility model relates to the technical field of data communication, and discloses a DSI3 interface signal conversion circuit, an ultrasonic radar and a vehicle. The DSI3 interface signal conversion circuit comprises a load interface unit, a sampling sub-circuit, a data sending sub-circuit and a data analysis sub-circuit. The data sending sub-circuit is used for outputting a first digital signal to the load interface unit, the load interface unit comprises a DSI3 interface, the load interface unit is connected with the data sending sub-circuit through the sampling sub-circuit and used for outputting a DSI3 signal fed back based on the first digital signal through the DSI3 interface, and the sampling sub-circuit is used for collecting current of the DSI3 signal and sending the current to the load interface unit. A corresponding voltage signal is generated based on the current; and the data analysis sub-circuit is connected with the sampling sub-circuit and is used for analyzing the voltage signal so as to obtain and output a second digital signal. Communication with the ultrasonic sensor is achieved through a DSI3 signal through the DSI3 interface signal conversion circuit, and the data communication cost of a vehicle-mounted product is reduced.

Description

Technical Field

[0001] This application belongs to the field of data communication technology, and particularly relates to a DSI3 interface signal conversion circuit, an ultrasonic radar, and a vehicle. Background Art

[0002] The popularization of autonomous driving and the increasing loading rate of ultrasonic radars in reverse radars and automatic parking systems have promoted the development of the in-vehicle ultrasonic radar market. The current second-generation ultrasonic radar chips adopt DSI3 (the 3rd generation Distributed System Interface) communication mode. Specifically, the MCU (Microcontroller Unit) communicates with a third-party DSI3 conversion chip through the SPI interface (Serial Peripheral Interface), and then the third-party DSI3 conversion chip communicates with the ultrasonic sensor through DSI3 signals. However, the current third-party DSI3 conversion chips on the market are expensive, resulting in an increase in the cost of internal communication in in-vehicle systems containing second-generation ultrasonic radar chips. Summary of the Utility Model

[0003] In view of the above deficiencies in the prior art, the purpose of the embodiments of this application is to provide a DSI3 interface signal conversion circuit, an ultrasonic radar, and a vehicle.

[0004] To achieve the above purpose, the first aspect of this application provides a DSI3 interface signal conversion circuit, including:

[0005] A load interface unit, including a DSI3 interface;

[0006] A sampling sub-circuit;

[0007] A data sending sub-circuit, configured to output a first digital signal to the load interface unit;

[0008] The load interface unit is connected to the data sending sub-circuit through the sampling sub-circuit, and the load interface unit is configured to output a DSI3 signal based on the feedback of the first digital signal through the DSI3 interface;

[0009] The sampling sub-circuit is configured to collect the current of the DSI3 signal and generate a corresponding voltage signal based on the current;

[0010] A data parsing sub-circuit, connected to the sampling sub-circuit, and the data parsing sub-circuit is configured to parse the voltage signal to obtain and output a second digital signal.

[0011] In the embodiments of this application, the sampling sub-circuit includes a sampling module and a voltage amplification module, and the sampling module is connected to the voltage amplification module;

[0012] The sampling module is connected to the DSI3 interface. The sampling module is used to collect the current of the DSI3 signal and generate an initial voltage signal based on the current.

[0013] The voltage amplification module is connected to the sampling module. The voltage amplification module is used to amplify the initial voltage signal and generate a corresponding voltage signal.

[0014] In the embodiment of the present application, the sampling sub-circuit further includes a filtering module, and the load interface unit is grounded through the sampling module and the filtering module in sequence.

[0015] In the embodiment of the present application, the sampling sub-circuit further includes an ADC sampling module. The ADC sampling module is connected to the output end of the voltage amplification module and is used to collect the voltage signal.

[0016] In the embodiment of the present application, the data parsing sub-circuit includes a standard voltage sampling module and a voltage comparison module.

[0017] The standard voltage sampling module is connected to the voltage comparison module. The standard voltage sampling module is used to input a standard voltage to the voltage comparison module.

[0018] The voltage comparison module is used to parse the voltage signal based on the standard voltage to obtain a second digital signal.

[0019] In the embodiment of the present application, the voltage comparison module includes a first voltage comparison sub-module, a second voltage comparison sub-module, and a third voltage comparison sub-module. The standard voltage sampling module includes a first standard voltage sampling sub-module, a second standard voltage sampling sub-module, and a third standard voltage sampling sub-module.

[0020] The first standard voltage sampling sub-module is connected to the first voltage comparison sub-module, the second standard voltage sampling sub-module is connected to the second voltage comparison sub-module, and the third standard voltage sampling sub-module is connected to the third voltage comparison sub-module.

[0021] In the embodiment of the present application, the DSI3 interface signal conversion circuit further includes an overload protection sub-circuit, and the overload protection sub-circuit is connected to the sampling sub-circuit.

[0022] The overload protection sub-circuit includes a sixth voltage comparator. The positive input end of the sixth voltage comparator is connected to the output end of the sampling sub-circuit. The negative input end of the sixth voltage comparator is connected to a preset overload voltage, and the output end of the sixth voltage comparator is used to output an overload signal.

[0023] In the embodiment of the present application, the data sending sub-circuit includes a power supply control module and a data sending module. The data sending module is arranged between the power supply control module and the sampling sub-circuit.

[0024] The second aspect of the present application provides an ultrasonic radar, including:

[0025] The DSI3 interface signal conversion circuit as described in the above embodiment.

[0026] The third aspect of the present application provides a vehicle, including:

[0027] The ultrasonic radar as described in the above embodiment.

[0028] Through the above technical solution, the first digital signal is output by the data sending sub-circuit in the DSI3 interface signal conversion circuit and sent to the load interface unit, so that the ultrasonic sensor generates a DSI3 signal based on the first digital signal, realizing the reception and processing of signals on the link from the host computer to the ultrasonic sensor; and the DSI3 signal fed back by the ultrasonic sensor is output through the load interface unit, and the DSI3 signal is collected and converted by the sampling sub-circuit to generate a voltage signal, so that the data parsing sub-circuit parses the voltage signal to obtain a second digital signal, realizing the reception and processing of signals on the link from the ultrasonic sensor to the host computer. By using the DSI3 interface signal conversion circuit to replace the current third-party DSI3 conversion chip, communication with the ultrasonic sensor through the DSI3 signal is realized, reducing the data communication cost of in-vehicle products.

[0029] Other features and advantages of the embodiments of the present application will be described in detail in the subsequent specific embodiments section. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings are used to provide a further understanding of the embodiments of the present application, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present application, but do not constitute a limitation to the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without creative efforts. In the drawings:

[0031] Figure 1 Schematically shows a structural diagram of a DSI3 interface signal conversion circuit according to an embodiment of the present application;

[0032] Figure 2 Schematically shows a structural diagram of a sampling sub-circuit according to an embodiment of the present application;

[0033] Figure 3 Schematically shows a structural diagram of a data parsing sub-circuit according to an embodiment of the present application;

[0034] Figure 4 Schematically shows a structural diagram of a data sending sub-circuit according to an embodiment of the present application.

[0035] DESCRIPTION OF REFERENCE NUMERALS

[0036] 100, Load Interface Unit; 110, DSI3 Interface; 200, Sampling Sub - circuit; 210, Sampling Module; 220, Voltage Amplification Module; 221, Operational Amplifier; 222, First Resistor; 223, Second Resistor; 224, Third Resistor; 225, Fourth Resistor; 230, Filtering Module; 240, ADC Sampling Module; 300, Data Transmission Sub - circuit; 310, Power Supply Control Module; 311, First Control Interface; 312, First Switching Transistor; 313, First Current - Limiting Resistor; 314, Second Current - Limiting Resistor; 315, Third Current - Limiting Resistor; 316, First Pull - up Resistor; 317, First Switching Transistor; 320, Data Transmission Module; 321, Second Control Interface; 322, Second Switching Transistor; 323, Fourth Current - Limiting Resistor; 324, Fifth Current - Limiting Resistor; 325, Sixth Current - Limiting Resistor; 326, Second Pull - up Resistor; 327, Second Switching Transistor; 328, Zener Diode; 400, Data Analysis Sub - circuit; 410, Standard Voltage Sampling Module; 411, First Standard Voltage Sampling Sub - module; 412, Second Standard Voltage Sampling Sub - module; 413, Third Standard Voltage Sampling Sub - module; 414, First Voltage Sampling Unit; 415, Second Voltage Sampling Unit; 416, Third Voltage Sampling Unit; 417, Fourth Voltage Sampling Unit; 418, Fifth Voltage Sampling Unit; 420, Voltage Comparison Module; 421, First Voltage Comparison Sub - module; 422, Second Voltage Comparison Sub - module; 423, Third Voltage Comparison Sub - module; 424, First Voltage Comparator; 425, Second Voltage Comparator; 426, Third Voltage Comparator; 427, Fourth Voltage Comparator; 428, Fifth Voltage Comparator; 500, Over - load Protection Sub - circuit; 510, Sixth Voltage Comparator. Detailed Embodiment

[0037] The following will explain in detail the specific embodiments of the present application with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for the purpose of illustrating and explaining the present application, and are not used to limit the present application.

[0038] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present application, then such directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If this specific posture changes, then the directional indications will also change accordingly.

[0039] In addition, if the descriptions such as "first" and "second" are involved in the embodiments of the present application, the descriptions of "first", "second", etc. are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between the various embodiments may be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0040] Figure 1 Schematically shows the DSI3 interface signal conversion circuit of the first embodiment of the present application. As Figure 1 shown, in an embodiment of the present application, a DSI3 interface signal conversion circuit is provided. The DSI3 interface signal conversion circuit includes a load interface unit 100, a sampling sub-circuit 200, a data sending sub-circuit 300, and a data parsing sub-circuit 400:

[0041] The data sending sub-circuit 300 is configured to output a first digital signal to the load interface unit 100;

[0042] The load interface unit 100 includes a DSI3 interface 110 and is connected to the data sending sub-circuit 300 through the sampling sub-circuit 200. The load interface unit 100 is configured to output a DSI3 signal based on the feedback of the first digital signal through the DSI3 interface 110;

[0043] The sampling sub-circuit 200 is configured to collect the current of the DSI3 signal and generate a corresponding voltage signal based on the current;

[0044] The data parsing sub-circuit 400 is connected to the sampling sub-circuit 200. The data parsing sub-circuit 400 is configured to parse the voltage signal to obtain and output a second digital signal.

[0045] In this embodiment, it should be noted that for the communication method of existing ultrasonic radar chips, a third-party DSI3 conversion chip is mainly used to realize communication with the ultrasonic sensor through the DSI3 signal. However, the third-party DSI3 conversion chip is expensive, resulting in an increase in the cost of internal communication of the vehicle-mounted system including the second-generation ultrasonic radar chip. To reduce the communication cost, in this embodiment, the current third-party DSI3 conversion chip is replaced by a DSI3 interface signal conversion circuit to realize communication with the ultrasonic sensor through the DSI3 signal. It should be noted that the load connected to the DSI3 interface signal conversion circuit can be not only the ultrasonic sensor, but also other devices that can communicate with the host computer through the DSI3 bus. In one embodiment, taking the MCU (Microcontroller Unit) as the host computer and the ultrasonic sensor as the load, the communication between the MCU and the ultrasonic sensor is used as an example for description. The ultrasonic sensor and the MCU are respectively connected to the input end and the output end of the DSI3 interface signal conversion circuit. The MCU is connected to the data sending sub-circuit 300, and the MCU controls the data sending sub-circuit 300 to output a first digital signal; the ultrasonic sensor is connected to the load interface unit 100 and outputs a DSI3 signal based on the feedback of the first digital signal through the DSI3 interface 110. The DSI3 interface signal conversion circuit analyzes the DSI3 signal into a second digital signal and sends the second digital signal to the MCU, thereby realizing the communication between the ultrasonic sensor and the MCU. It should be noted that the first digital signal includes the digital signal sent by the MCU to the ultrasonic sensor, and the second digital signal includes the digital signal fed back to the MCU by the ultrasonic sensing line based on the first digital signal.

[0046] Specifically, the DSI3 interface signal conversion circuit includes a load interface unit 100, a sampling sub-circuit 200, a data sending sub-circuit 300, and a data parsing sub-circuit 400. Among them, the data sending sub-circuit 300 is used to output a first digital signal to the load interface unit 100. The load interface unit 100 includes a DSI3 interface 110. The load interface unit 100 is connected to the data sending sub-circuit 300 through the sampling sub-circuit 200. The load interface unit 100 sends the first digital signal received from the data sending sub-circuit 300 to the ultrasonic sensor. The ultrasonic sensor outputs a DSI3 signal based on the received first digital signal and outputs the DSI3 signal through the DSI3 interface 110 of the load interface unit 100. The sampling sub-circuit 200 is connected to the DSI3 interface 110 of the load interface unit 100. When the DSI3 signal is output at the DSI3 interface 110, the sampling sub-circuit 200 collects the current of the DSI3 signal and generates a corresponding voltage signal based on the current. The data parsing sub-circuit 400 is used to parse the voltage signal. The data parsing sub-circuit 400 is connected to the sampling sub-circuit 200. After receiving the voltage signal output by the sampling sub-circuit 200, it parses the voltage signal to obtain and output a second digital signal.

[0047] In this embodiment, the first digital signal of the MCU is output through the data sending sub-circuit 300 in the DSI3 interface signal conversion circuit and sent to the load interface unit 100, so that the ultrasonic sensor generates a DSI3 signal based on the first digital signal, realizing the reception and processing of signals on the link from the MCU to the ultrasonic sensor; and the DSI3 signal fed back by the ultrasonic sensor is output through the load interface unit 100. The sampling sub-circuit 200 collects and converts the DSI3 signal to generate a voltage signal, so that the data parsing sub-circuit 400 parses the voltage signal to obtain a second digital signal, realizing the reception and processing of signals on the link from the ultrasonic sensor to the MCU. By using the DSI3 interface signal conversion circuit to replace the current third-party DSI3 conversion chip, communication with the ultrasonic sensor through the DSI3 signal is realized, and the data communication cost of in-vehicle products is reduced.

[0048] Reference Figure 2 , in one embodiment, the sampling sub-circuit 200 includes a sampling module 210 and a voltage amplification module 220, and the sampling module 210 is connected to the voltage amplification module 220;

[0049] The sampling module 210 is connected to the DSI3 interface 110. The sampling module 210 is used to collect the current of the DSI3 signal and generate an initial voltage signal based on the current;

[0050] The voltage amplification module 220 is connected to the sampling module 210. The voltage amplification module 220 is used to amplify the initial voltage signal and generate a corresponding voltage signal.

[0051] In this embodiment, it should be noted that when the DSI3 interface signal conversion circuit analyzes the DSI3 signal, by converting the DSI3 signal into a voltage signal and generating a corresponding second digital signal through the analysis of the voltage signal. The sampling sub-circuit 200 includes a sampling module 210 and a voltage amplification module 220. Among them, the sampling module 210 is connected to the DSI3 interface 110 and is used to collect the current of the DSI3 signal and generate an initial voltage signal based on the current. It can be understood that the initial voltage signal is a signal with a very small voltage value. In this embodiment, to improve the accuracy of data analysis, the initial voltage signal is amplified. Specifically, in this embodiment, the voltage amplification module 220 is connected to the sampling module 210 to amplify the initial voltage signal generated by the sampling module 210 and generate a corresponding voltage signal.

[0052] It should be noted that the voltage amplification module 220 includes an operational amplifier 221, a first resistor 222, a second resistor 223, a third resistor 224, and a fourth resistor 225. In the voltage amplification module 220, the DSI3 interface 110 is connected to the first end of the first resistor 222 through the sampling module 210. The second end of the first resistor 222 is respectively connected to the positive input terminal of the operational amplifier 221 and the first end of the second resistor 223, and the second end of the second resistor 223 is grounded; the DSI3 interface 110 is also connected to the first end of the third resistor 224, and the second end of the third resistor 224 is respectively connected to the negative input terminal of the operational amplifier 221. The second end of the third resistor 224 and the negative input terminal of the operational amplifier 221 are both connected to the output terminal of the operational amplifier 221 through the fourth resistor 225. The amplification factor of the voltage amplification module 220 can be determined based on the resistance values of the second resistor 223 and the fourth resistor 225. The positive power supply terminal of the operational amplifier 221 provides a positive voltage for the operational amplifier, and the negative power supply terminal of the operational amplifier 221 is grounded. It can be understood that in practical applications, the resistance values of the second resistor 223 and the fourth resistor 225 can be adjusted adaptively to obtain a voltage amplification factor that meets the actual requirements. On the basis of ensuring the normal amplification of the initial voltage signal, the internal circuit structure of the voltage amplification module 220 can be adjusted adaptively. Further, the resistance values of the first resistor 222, the second resistor 223, the third resistor 224, and the fourth resistor 225 can all be adjusted adaptively based on actual application requirements to achieve the current limiting protection and voltage amplification requirements.

[0053] In this embodiment, the sampling sub-circuit 200 realizes the acquisition and amplification of voltage based on the circuit of the DSI3 signal, provides a precise signal input for signal analysis, and improves the effectiveness of signal analysis.

[0054] Reference Figure 2, in one embodiment, the sampling sub - circuit 200 further includes a filtering module 230, and the load interface unit 100 is grounded through the sampling module 210 and the filtering module 230 in sequence.

[0055] In this embodiment, it should be noted that the filtering module 230 includes one or more parallel - connected capacitors. One end of each capacitor is connected to the load interface unit 100 through the sampling module 210, and the other end of each capacitor is grounded. For example, if the filtering module 230 includes two capacitors, namely the first capacitor and the second capacitor, then the load interface unit 100 is grounded through the sampling module 210 and the first capacitor in sequence, and is grounded through the sampling module 210 and the second capacitor in sequence. When there is an alternating - current component in the circuit, the capacitor will absorb it and convert it into charge stored inside the capacitor, thereby reducing the influence of the alternating - current component in the circuit.

[0056] In this embodiment, the filtering module 230 effectively filters out high - frequency noise, making the circuit output signal smoother, with higher stability, and improving the accuracy and stability of the circuit.

[0057] Reference Figure 2 , in one embodiment, the sampling sub - circuit 200 further includes an ADC sampling module 240. The ADC sampling module 240 is connected to the output end of the voltage amplification module 220 and is used to collect voltage signals.

[0058] In this embodiment, it should be noted that the ADC (Analog - to - Digital Converter) sampling module 240 can measure the input voltage according to a certain sampling frequency, that is, take values of the voltage within a certain time, convert the voltage value of each sampling point into a digital value, and encode the digital value and then output it to the host computer for the host computer to store or process.

[0059] In this embodiment, the ADC sampling module 240 samples the voltage signal for the host computer to process, providing diversity in data acquisition.

[0060] Reference Figure 3 , in one embodiment, the data parsing sub - circuit 400 includes a standard voltage sampling module 410 and a voltage comparison module 420;

[0061] The standard voltage sampling module 410 is connected to the voltage comparison module 420. The standard voltage sampling module 410 is used to input a standard voltage to the voltage comparison module 420;

[0062] The voltage comparison module 420 is used to parse the voltage signal based on the standard voltage to obtain a second digital signal.

[0063] In this embodiment, it should be noted that the DSI3 signal uses three current change segments as one data, representing a four-digit hexadecimal data. Among them, the lowest bit in the current change segment represents data 0, the second lowest bit represents data 1, and the highest bit represents data 2. Different currents represent different data. For example, when the current is 0 mA, the data is 0; when the current is 12 mA, the data is 1; when the current is 24 mA, the data is 2. In this embodiment, signal analysis is performed based on the voltage signal corresponding to and amplified by the current. Specifically, the current is converted into a voltage signal, and the voltage signal is analyzed. For example, when the current is 0 mA, the corresponding amplified voltage is 0 V; when the current is 12 mA, the corresponding amplified voltage is 1.7 V; when the current is 24 mA, the corresponding amplified voltage is 3.4 V. The standard voltage sampling module 410 is used to sample the standard voltage, and the sampled standard voltage is input to the voltage comparison module 420. The voltage comparison module 420 analyzes the received voltage signal based on the standard voltage to obtain a second digital signal, and the host computer can determine the corresponding specific data after receiving the second digital signal.

[0064] It can be understood that in one embodiment, to improve the fault tolerance of the circuit, different data can also be corresponding to different current ranges. For example, when the current is less than or equal to 2 mA, the data is 0, and the corresponding amplified voltage is less than or equal to 0.2 V at this time; when the current is greater than or equal to 10.5 mA and less than or equal to 13.5 mA, the data is 1, and the corresponding amplified voltage is greater than or equal to 1.5 V and less than or equal to 1.9 V at this time; when the current is greater than or equal to 21 mA and less than or equal to 27 mA, the data is 2, and the corresponding amplified voltage is greater than or equal to 3.0 V and less than or equal to 3.8 V at this time.

[0065] In this embodiment, the standard voltage sampling module 410 samples the standard voltage, provides an effective comparison reference for the voltage comparison module 420 to analyze the voltage signal, and improves the accuracy of signal analysis.

[0066] Reference Figure 3 , in one embodiment, the voltage comparison module 420 includes a first voltage comparison sub-module 421, a second voltage comparison sub-module 422, and a third voltage comparison sub-module 423, and the standard voltage sampling module 410 includes a first standard voltage sampling sub-module 411, a second standard voltage sampling sub-module 412, and a third standard voltage sampling sub-module 413;

[0067] The first standard voltage sampling sub-module 411 is connected to the first voltage comparison sub-module 421, the second standard voltage sampling sub-module 412 is connected to the second voltage comparison sub-module 422, and the third standard voltage sampling sub-module 413 is connected to the third voltage comparison sub-module 423.

[0068] It should be noted that three different voltage signals can be obtained from the three current change segments corresponding to the DSI3 signal. In this embodiment, three standard voltage sampling sub-modules respectively provide corresponding standard voltages for three voltage comparison sub-modules to distinguish the voltage signals through the three voltage comparison sub-modules, thereby realizing data parsing.

[0069] Reference Figure 3 , specifically, in one embodiment, the second digital signal includes a third digital signal, a fourth digital signal, and a fifth digital signal;

[0070] The first voltage comparison sub-module 421 includes a first voltage comparator 424, and the first standard voltage sampling sub-module 411 includes a first voltage sampling unit 414. The negative input terminal of the first voltage comparator 424 is connected to the output terminal of the sampling circuit 200, and the positive input terminal of the first voltage comparator 424 is connected to the first voltage sampling unit 414. Among them, the first voltage sampling unit 414 is used to provide the first standard voltage, and the first voltage comparison sub-module 421 is used to output the third digital signal;

[0071] The second voltage comparison sub-module 422 includes a second voltage comparator 425 and a third voltage comparator 426, and the second standard voltage sampling sub-module 412 includes a second voltage sampling unit 415 and a third voltage sampling unit 416. The positive input terminal of the second voltage comparator 425 is connected to the output terminal of the sampling circuit 200, the negative input terminal of the second voltage comparator 425 is connected to the second voltage sampling unit 415, the negative input terminal of the third voltage comparator 426 is connected to the output terminal of the sampling circuit 200, and the positive input terminal of the third voltage comparator 426 is connected to the third voltage sampling unit 416. Among them, the second voltage sampling unit 415 is used to provide the second standard voltage, the third voltage sampling unit 416 is used to provide the third standard voltage, the output terminal of the second voltage comparator 425 is connected to the output terminal of the third voltage comparator 426, and the second voltage comparison sub-module 422 is used to output the fourth digital signal;

[0072] The third voltage comparator sub-module 423 includes a fourth voltage comparator 427 and a fifth voltage comparator 428. The third standard voltage sampling sub-module 413 includes a fourth voltage sampling unit 417 and a fifth voltage sampling unit 418. The positive input terminal of the fourth voltage comparator 427 is connected to the output terminal of the sampling circuit 200. The negative input terminal of the fourth voltage comparator 427 is connected to the fourth voltage sampling unit 417. The negative input terminal of the fifth voltage comparator 428 is connected to the output terminal of the sampling circuit 200. The positive input terminal of the fifth voltage comparator 428 is connected to the fifth voltage sampling unit 418. The fourth voltage sampling unit 417 is used to provide a fourth standard voltage. Among them, the fifth voltage sampling unit 418 is used to provide a fifth standard voltage. The output terminal of the fourth voltage comparator 427 is connected to the output terminal of the fifth voltage comparator 428. The third voltage comparator sub-module 423 is used to output a fifth digital signal;

[0073] Among them, the first standard voltage is less than the second standard voltage, the second standard voltage is less than the third standard voltage, the third standard voltage is less than the fourth standard voltage, and the fourth standard voltage is less than the fifth standard voltage.

[0074] In this embodiment, it should be noted that the second digital signal is the output signal of the data parsing sub-circuit 400, specifically including a third digital signal, a fourth digital signal, and a fifth digital signal. Among them, the third digital signal is used to determine whether data 0 is read, the fourth digital signal is used to determine whether data 1 is read, and the fifth digital signal is used to determine whether data 2 is read. In this embodiment, a voltage comparator is used to parse the voltage signal. The voltage comparator includes a positive input terminal, a negative input terminal, and an output terminal. When the voltage at the positive input terminal of the voltage comparator is higher than the voltage at the negative input terminal, the output of the voltage comparator is usually high level. On the contrary, when the voltage at the negative input terminal is higher than the voltage at the positive input terminal, the output of the voltage comparator is low level. It can be understood that in a digital logic circuit, the high level and low level of a digital signal are usually represented by binary numbers 0 and 1. By inputting the standard voltage and the voltage signal to be parsed into the voltage comparator and determining the output of the voltage comparator, the binary digital signal corresponding to the voltage signal can be obtained.

[0075] In this embodiment, the first voltage comparison sub-module 421 includes a first voltage comparator 424; the first standard voltage sampling sub-module 411 includes a first voltage sampling unit 414. The first voltage sampling unit 414 is connected to the positive input terminal of the first voltage comparator 424, and the first voltage sampling unit 414 is used to provide a first standard voltage. The sampling circuit 200 converts the current signal of the DSI3 signal into an amplified voltage signal and outputs it to the negative input terminal of the first voltage comparator 424. The first voltage comparator 424 determines whether the voltage signal to be analyzed corresponds to data 0 through the first standard voltage. The first voltage comparison sub-module 421 is used to determine whether data 0 is read, and data 0 corresponds to the lowest bit among the three current change segments of the DSI3 signal. In one embodiment, taking the case where the current is less than or equal to 2 mA indicating data 0 as an example, when the current is less than or equal to 2 mA, the corresponding amplified voltage is less than or equal to 0.2 V. The first standard voltage is sampled as 0.2 V. The voltage signal to be analyzed output by the sampling circuit 200 is input to the negative input terminal of the first voltage comparator 424, and the first standard voltage output by the first voltage sampling unit 414 is input to the positive input terminal of the first voltage comparator 424. When the voltage at the positive input terminal of the first voltage comparator 424 is higher than the voltage at the negative input terminal, that is, when the first standard voltage of 0.2 V is higher than the voltage signal to be analyzed, the output of the first voltage comparator 424 is a high level. At this time, the third digital signal is 1, indicating that data 0 is read. On the contrary, when the voltage at the negative input terminal of the first voltage comparator 424 is higher than the voltage at the positive input terminal, that is, when the voltage signal to be analyzed is higher than the first standard voltage of 0.2 V, the output of the first voltage comparator 424 is a low level. At this time, the third digital signal is 0, indicating that data 0 is not read.

[0076] In this embodiment, the second voltage comparison sub-module 422 includes a second voltage comparator 425 and a third voltage comparator 426, and the second standard voltage sampling sub-module 412 includes a second voltage sampling unit 415 and a third voltage sampling unit 416. The second voltage sampling unit 415 is connected to the negative input terminal of the second voltage comparator 425, and the second voltage sampling unit 415 is used to provide a second standard voltage. The sampling circuit 200 converts the current signal of the DSI3 signal into an amplified voltage signal and outputs it to the positive input terminal of the second voltage comparator 425. The third voltage sampling unit 416 is connected to the positive input terminal of the third voltage comparator 426, and the third voltage sampling unit 416 is used to provide a third standard voltage. The sampling circuit 200 converts the current signal of the DSI3 signal into an amplified voltage signal and outputs it to the negative input terminal of the third voltage comparator 426. The second voltage comparison sub-module 422 combines the second voltage comparator 425 and the third voltage comparator 426 to determine whether the voltage signal to be analyzed corresponds to data 1 based on the second standard voltage and the third standard voltage.

[0077] Data 1 corresponds to the second lowest bit among the three current change segments of the DSI3 signal. In one embodiment, taking the case where when the current is greater than or equal to 10.5 mA and less than or equal to 13.5 mA, it represents Data 1. When the current is greater than or equal to 10.5 mA and less than or equal to 13.5 mA, the corresponding amplified voltage is greater than or equal to 1.5 V and less than or equal to 1.9 V. The second standard voltage is sampled at 1.5 V, and the third standard voltage is sampled at 1.9 V. The second standard voltage output by the second voltage sampling unit 415 is input to the negative input terminal of the second voltage comparator 425, and the voltage signal to be analyzed output by the sampling sub-circuit 200 is input to the positive input terminal of the second voltage comparator 425. The second voltage comparator 425 determines whether the voltage signal to be analyzed is greater than 1.5 V. When the voltage signal to be analyzed is greater than 1.5 V, the second voltage comparator 425 outputs a high level. The third standard voltage output by the third voltage sampling unit 416 is input to the positive input terminal of the third voltage comparator 426, and the voltage signal to be analyzed output by the sampling sub-circuit 200 is input to the negative input terminal of the third voltage comparator 426. The third voltage comparator 426 determines whether the voltage signal to be analyzed is less than 1.9 V. When the voltage signal to be analyzed is less than 1.9 V, the second voltage comparator 425 outputs a high level. Only when both the second voltage comparator 425 and the third voltage comparator 426 output high levels does the second voltage comparison sub-module 422 output a high level. When the second voltage comparison sub-module 422 outputs a high level, the fourth digital signal is 1, indicating that Data 1 is read. When the second voltage comparison sub-module 422 outputs a low level, the fourth digital signal is 0, indicating that Data 1 is not read.

[0078] In this embodiment, the third voltage comparison sub-module 423 includes a fourth voltage comparator 427 and a fifth voltage comparator 428, and the third standard voltage sampling sub-module 413 includes a fourth voltage sampling unit 417 and a fifth voltage sampling unit 418. The fourth voltage sampling unit 417 is connected to the negative input terminal of the fourth voltage comparator 427. The fourth voltage sampling unit 417 is used to provide a fourth standard voltage, and the current signal of the DSI3 signal is converted into an amplified voltage signal through the sampling sub-circuit 200 and output to the positive input terminal of the fourth voltage comparator 427. The fifth voltage sampling unit 418 is connected to the positive input terminal of the fifth voltage comparator 428. The fifth voltage sampling unit 418 is used to provide a fifth standard voltage, and the current signal of the DSI3 signal is converted into an amplified voltage signal through the sampling sub-circuit 200 and output to the negative input terminal of the fifth voltage comparator 428. The third voltage comparison sub-module 423 determines whether the voltage signal to be analyzed corresponds to Data 2 based on the fourth standard voltage and the fifth standard voltage through the combination of the fourth voltage comparator 427 and the fifth voltage comparator 428.

[0079] Data 2 corresponds to the highest bit among the three current change segments of the DSI3 signal. In one embodiment, taking the case where the current is greater than or equal to 21 mA and less than or equal to 27 mA represents Data 2 as an example. When the current is greater than or equal to 21 mA and less than or equal to 27 mA, the corresponding amplified voltage is greater than or equal to 3.0 V and less than or equal to 3.8 V. The fourth standard voltage is sampled at 3.0 V, and the fifth standard voltage is sampled at 3.8 V. The fourth standard voltage output by the fourth voltage sampling unit 417 is input to the negative input terminal of the fourth voltage comparator 427, and the voltage signal to be analyzed output by the sampling sub-circuit 200 is input to the positive input terminal of the fourth voltage comparator 427. It is judged whether the voltage signal to be analyzed is greater than 3.0 V through the fourth voltage comparator 427. When the voltage signal to be analyzed is greater than 3.0 V, the fourth voltage comparator 427 outputs a high level. The fifth standard voltage output by the fifth voltage sampling unit 418 is input to the positive input terminal of the fifth voltage comparator 428, and the voltage signal to be analyzed output by the sampling sub-circuit 200 is input to the negative input terminal of the fifth voltage comparator 428. It is judged whether the voltage signal to be analyzed is less than 3.8 V through the fifth voltage comparator 428. When the voltage signal to be analyzed is less than 3.8 V, the fourth voltage comparator 427 outputs a high level. Only when both the fourth voltage comparator 427 and the fifth voltage comparator 428 output high levels does the third voltage comparison sub-module 423 output a high level. When the third voltage comparison sub-module 423 outputs a high level, the fourth digital signal is 1, indicating that Data 2 is read. When the third voltage comparison sub-module 423 outputs a low level, the fourth digital signal is 0, indicating that Data 2 is not read.

[0080] It can be understood that one or more resistors can be connected to the inside or output terminals of the first voltage comparison sub-module 421, the second voltage comparison sub-module 422, and the third voltage comparison sub-module 423 based on the actual application scenario to achieve current limiting protection for the circuit. One or more resistors can be connected to the inside or output terminals of the first standard voltage sampling sub-module 411, the second standard voltage sampling sub-module 412, and the third standard voltage sampling sub-module 413 based on the actual application scenario to achieve current limiting protection for the circuit and to divide the power supply voltage to sample the standard voltage.

[0081] In this embodiment, the standard voltage sampling module 410 provides the standard voltage, provides an effective signal analysis basis for the voltage comparison module 420, and the voltage comparison module 420 analyzes different voltage signals respectively to obtain the corresponding second digital signal, improving the accuracy of data analysis, and further improving the effectiveness of the DSI3 interface signal conversion circuit.

[0082] Reference Figure 4, in one embodiment, the DSI3 interface signal conversion circuit further includes an overload protection sub-circuit 500, and the overload protection sub-circuit 500 is connected to the sampling sub-circuit 200;

[0083] The overload protection sub-circuit 500 includes a sixth voltage comparator 510. The positive input terminal of the sixth voltage comparator 510 is connected to the output terminal of the sampling sub-circuit 200. The negative input terminal of the sixth voltage comparator 510 is connected to a preset overload voltage, and the output terminal of the sixth voltage comparator is used to output an overload signal.

[0084] In this embodiment, it should be noted that the overload protection sub-circuit 500 is used to protect the circuit and prevent damage to the circuit caused by voltage overload. Specifically, the sixth voltage comparator 510 is used to limit the highest voltage in the DSI3 interface signal conversion circuit. The preset overload voltage is a pre-determined voltage signal. When the voltage in the circuit exceeds the preset overload voltage, a reminder of the overload signal is output. By connecting the output terminal of the sampling sub-circuit 200 to the positive input terminal of the sixth voltage comparator 510 and connecting the preset overload voltage to the negative input terminal of the sixth voltage comparator 510, when the voltage signal output by the output terminal of the sampling sub-circuit 200 is higher than the preset overload voltage, the output terminal of the sixth voltage comparator 510 will output a high level, and at this time, a reminder of the overload signal is output. On the contrary, when the voltage signal output by the output terminal of the sampling sub-circuit 200 is lower than the preset overload voltage, the output terminal of the sixth voltage comparator 510 will output a low level, and no reminder of the overload signal will be output. It can be understood that one or more resistors are connected between the negative input terminal of the sixth voltage comparator 510 and the power supply voltage based on the actual application scenario to sample the preset overload voltage by dividing the power supply voltage, and the voltage value of the preset overload voltage can be limited based on the actual application scenario.

[0085] In this embodiment, the circuit overload reminder is realized through the overload protection sub-circuit 500, which improves the practicability and safety of the DSI3 interface signal conversion circuit.

[0086] Reference Figure 4 , in one embodiment, the data sending sub-circuit 300 includes a power supply control module 310 and a data sending module 320, and the data sending module 320 is arranged between the power supply control module 310 and the sampling sub-circuit 200.

[0087] In this embodiment, it should be noted that the data sending sub-circuit 300 includes a power supply control module 310 and a data sending module 320. The host computer is respectively connected to the power supply control module 310 and the data sending module 320, and is used to control the power supply control module 310 to provide a power supply voltage and control the data sending module 320 to output a first digital signal.

[0088] Specifically, refer to Figure 4, in one embodiment, the power supply control module 310 includes a first control interface 311, a first switching transistor 312, a first current-limiting resistor 313, a second current-limiting resistor 314, a third current-limiting resistor 315, a first pull-up resistor 316, and a first switching transistor 317. The first control interface 311 is grounded through the first current-limiting resistor 313. The first control interface 311 is also connected to the control terminal of the first switching transistor 312 through the second current-limiting resistor 314. The first terminal of the first switching transistor 312 is respectively connected to the first terminal of the third current-limiting resistor 315 and the first terminal of the first pull-up resistor 316. The second terminal of the first switching transistor is grounded. The second terminal of the third current-limiting resistor 315 is connected to the base of the first switching transistor 317. The second terminal of the first pull-up resistor 316 is respectively connected to the power supply voltage and the emitter of the first switching transistor 317;

[0089] It should be noted that the first control interface 311 outputs a high or low level signal based on the control of the host computer to control the on and off of the first switching transistor 312. When a high level is input, the first switching transistor 312 is turned on, and the base level of the first switching transistor 317 is pulled low. At this time, the first switching transistor 317 is turned on, providing a power supply voltage for the DSI3 interface signal conversion circuit. When a low level is input, the first switching transistor 312 is turned off, and the first switching transistor 317 is cut off, stopping to provide a power supply voltage for the DSI3 interface signal conversion circuit.

[0090] The data sending module 320 includes a second control interface 321, a second switching transistor 322, a fourth current-limiting resistor 323, a fifth current-limiting resistor 324, a sixth current-limiting resistor 325, a second pull-up resistor 326, a second switching transistor 327, and a voltage regulator diode 328. The second control interface 321 is grounded through the fourth current-limiting resistor 323. The second control interface 321 is also connected to the control terminal of the second switching transistor 322 through the fifth current-limiting resistor 324. The first terminal of the second switching transistor 322 is respectively connected to the first terminal of the sixth current-limiting resistor 325 and the first terminal of the second pull-up resistor 326. The second terminal of the second switching transistor is grounded. The second terminal of the sixth current-limiting resistor 325 is connected to the base of the second switching transistor 327. The second terminal of the second pull-up resistor 326 is respectively connected to the collector of the first switching transistor 317 and the emitter of the second switching transistor 327. The collector of the first switching transistor 317 is connected to the sampling sub-circuit 200 through the voltage regulator diode 328. The collector of the first switching transistor 317 is also connected to the sampling sub-circuit 200 through the second switching transistor 327.

[0091] It should be noted that the second control interface 321 outputs high and low level signals based on the control of the host computer to control the on / off of the second switching tube 322. When a high level is input, the second switching tube 322 conducts, and the base level of the second switching transistor 327 is pulled low. At this time, the second switching transistor 327 conducts, and the first switching transistor 317 is connected to the sampling sub-circuit 200 through the second switching transistor 327. The power supply voltage output by the power supply control module 310 is input to the load interface unit 100 through the second switching transistor 327 of the data sending module 320 and the sampling sub-circuit 200 in sequence, so as to be transmitted to the ultrasonic sensor through the load interface unit 100. When a low level is input, the second switching tube 322 is turned off, and the second switching transistor 327 is cut off. The power supply voltage output by the power supply control module 310 cannot pass through the second switching transistor. At this time, the power supply voltage is input to the sampling sub-circuit 200 through the voltage stabilizing diode 328, and then input to the load interface unit 100 through the sampling sub-circuit 200, so as to be transmitted to the ultrasonic sensor through the load interface unit 100. It should be noted that in this embodiment, the voltage stabilizing diode 328 is used to form a voltage drop, and the power supply voltage passing through the voltage stabilizing diode 328 will be reduced by a certain voltage value. The power supply voltage after the voltage value is reduced is input to the sampling sub-circuit 200. For example, if the power supply voltage is 9V and the voltage stabilizing diode 328 forms a voltage drop of 2V, when the host computer controls the output of a high level, the second switching transistor 327 conducts, and the 9V power supply voltage output by the power supply control module 310 is input to the load interface unit 100 through the second switching transistor 327 of the data sending module 320 and the sampling sub-circuit 200 in sequence; when the host computer controls the output of a low level, the second switching transistor 327 is cut off, and the source voltage forms a voltage drop through the voltage stabilizing diode 328 and becomes 7V. At this time, the 7V power supply voltage will be input to the sampling sub-circuit 200, and then input to the load interface unit 100 through the sampling sub-circuit 200. By controlling the second control interface 321 to output high and low levels by the host computer, corresponding to the high and low voltage changes entering the load interface unit 100, the signal transmission is realized.

[0092] It can be understood that in this embodiment, the resistance values of resistors such as the first current limiting resistor 313, the second current limiting resistor 314, the third current limiting resistor 315, the first pull-up resistor 316, the fourth current limiting resistor 323, the fifth current limiting resistor 324, the sixth current limiting resistor 325, and the second pull-up resistor 326 can all be determined based on the actual application scenario.

[0093] In this embodiment, the power supply control module 310 is used to realize the on / off control of the power supply voltage of the DSI3 interface signal conversion circuit, improve the flexibility of the circuit, and the data sending module 320 is used to realize the data access of the host computer, realizing the data flow from the host computer to the load, and improving the practicability and effectiveness of the DSI3 interface signal conversion circuit.

[0094] An embodiment of the present application provides an ultrasonic radar, including:

[0095] The DSI3 interface signal conversion circuit as described in the above embodiment.

[0096] An embodiment of the present application provides a vehicle, including:

[0097] The ultrasonic radar as described in the above embodiment.

[0098] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. Among them, the terms "first position" and "second position" are two different positions, and moreover, the first feature being "above", "over" and "on" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "under" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.

[0099] In the present application, unless otherwise clearly specified and defined, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection, an electrical connection or communication with each other; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the connection inside two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0100] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0101] It should also be noted that the term "comprising", "including", or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, commodity, or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, commodity, or device including the element.

[0102] Although the embodiments of this application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limitations to this application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A DSI3 interface signal conversion circuit, characterized in that: Including load interface unit, sampling subcircuit, data transmission subcircuit, data analysis subcircuit: The data sending sub-circuit is used to output a first digital signal to the load interface unit; The load interface unit includes a DSI3 interface and is connected to the data sending subcircuit through the sampling subcircuit, and the load interface unit is used to output a DSI3 signal based on the first digital signal feedback through the DSI3 interface; The sampling subcircuit is used to collect the current of the DSI3 signal and generate a corresponding voltage signal based on the current; The data analysis sub-circuit is connected to the sampling sub-circuit, and is used to analyze the voltage signal to obtain and output a second digital signal.

2. The DSI3 interface signal conversion circuit according to claim 1, characterized in that: The sampling subcircuit comprises a sampling module and a voltage amplification module, and the sampling module is connected to the voltage amplification module; The sampling module is connected to the DSI3 interface, and the sampling module is used to collect the current of the DSI3 signal and generate an initial voltage signal based on the current; The voltage amplification module is connected to the sampling module, and is used to amplify the initial voltage signal to generate a corresponding voltage signal.

3. The DSI3 interface signal conversion circuit according to claim 2, characterized in that: The sampling subcircuit further includes a filtering module, and the load interface unit is grounded via the sampling module and the filtering module in sequence.

4. The DSI3 interface signal conversion circuit according to claim 2, characterized in that: The sampling subcircuit further includes an ADC sampling module, which is connected to the output end of the voltage amplification module and is used to collect the voltage signal.

5. The DSI3 interface signal conversion circuit according to claim 1, characterized in that: The data analysis subcircuit includes a standard voltage sampling module and a voltage comparison module; The standard voltage sampling module is connected to the voltage comparison module, and the standard voltage sampling module is used to input a standard voltage to the voltage comparison module; The voltage comparison module is used to analyze the voltage signal based on the standard voltage to obtain a second digital signal.

6. The DSI3 interface signal conversion circuit according to claim 5, characterized in that: The voltage comparison module includes a first voltage comparison submodule, a second voltage comparison submodule and a third voltage comparison submodule, and the standard voltage sampling module includes a first standard voltage sampling submodule, a second standard voltage sampling submodule and a third standard voltage sampling submodule; The first standard voltage sampling submodule is connected to the first voltage comparison submodule, the second standard voltage sampling submodule is connected to the second voltage comparison submodule, and the third standard voltage sampling submodule is connected to the third voltage comparison submodule.

7. The DSI3 interface signal conversion circuit according to claim 1, characterized in that: The DSI3 interface signal conversion circuit also includes an overload protection subcircuit, and the overload protection subcircuit is connected to the sampling subcircuit; The overload protection subcircuit includes a sixth voltage comparator, the positive input terminal of the sixth voltage comparator is connected to the output terminal of the sampling subcircuit, the negative input terminal of the sixth voltage comparator is connected to a preset overload voltage, and the output terminal of the sixth voltage comparator is used to output an overload signal.

8. The DSI3 interface signal conversion circuit according to claim 1, characterized in that: The data sending subcircuit comprises a power supply control module and a data sending module, and the data sending module is arranged between the power supply control module and the sampling subcircuit.

9. An ultrasonic radar, characterized in that: include: A DSI3 interface signal conversion circuit according to any one of claims 1 to 8.

10. A vehicle, characterized in that: include: The ultrasonic radar according to claim 9.

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