Adaptive power supply positive and negative connection circuit

Abstract

The utility model provides a self-adaptive power supply positive and negative connection circuit, a first connection end of a first switching device is connected with a second power supply input end, a control end of the first switching device is connected with a first power supply input end, and a second connection end of the first switching device is connected with a second power supply output end; the first connecting end of the second switching device is connected with the second power input end, the control end is connected with the first power input end, and the second connecting end is connected with the first power output end; the first connecting end of the third switching device is connected with the first power input end, the control end is connected with the second power input end, and the second connecting end is connected with the second power output end; the first connecting end of the fourth switching device is connected with the first power input end, the control end is connected with the second power input end, and the second connecting end is connected with the first power output end. Compared with the prior art, the high-power load can work normally under the condition that the power supply at the input end is positively and negatively connected, and the self-adaptive power supply input polarity is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit design, and particularly relates to an adaptive power supply reverse connection circuit, which is applicable to products with high power consumption and requires normal operation when the power supply is connected in reverse or forward.

Background Art

[0002] The ports of products usually need to be connected to an external power supply, and the external connected DC power supply has positive and negative poles. Products usually need to be correctly connected to the positive and negative poles to work properly. To avoid the product not working or malfunctioning due to the reverse connection of the positive and negative poles of the power supply when using the product, it is necessary to provide an application circuit for adaptive power supply reverse connection for power loads. Regardless of whether the positive and negative poles of the power supply are reversely connected, the circuit can work normally and adapt to the connection of the positive and negative poles of the power supply input.

[0003] Please refer to Figure 1 as shown, which is an application circuit for adaptive power supply reverse connection for power loads in the prior art. Figure 1 The circuit shown contains a rectifier bridge component 110, which utilizes the unidirectional conductivity of diodes D1, D2, D3, and D4. Regardless of whether the voltage directions of the input terminals Vin1 and Vin2 are correct, the voltage direction at the load terminal output is that Vout1 is the positive pole and Vout2 is the negative pole.

[0004] Figure 1 Problems and disadvantages of the prior art solution shown:

[0005] a. The voltage drops of diodes D1, D2, D3, and D4 are relatively large;

[0006] b. The thermal power consumption is relatively large. When the load RL is a high-power load, a heat sink may be required, and thus a larger structural space may also be required.

[0007] Therefore, it is necessary to propose a new technical solution to solve the above problems.

Content of the Utility Model

[0008] One of the purposes of the utility model is to provide an adaptive power supply reverse connection circuit, which enables a high-power load to work normally when the input power supply is connected in reverse or forward, and adapts to the input polarity of the power supply.

[0009] According to one aspect of the present utility model, the present utility model provides an adaptive power supply positive and negative connection circuit, which includes a first switching device Q1, a second switching device Q2, a third switching device Q3, a fourth switching device Q4, a first power input terminal Vin1, a second power input terminal Vin2, a first power output terminal Vout1, and a second power output terminal Vout2. The first connection end of the first switching device Q1 is connected to the second power input terminal Vin2, its control end is connected to the first power input terminal Vin1, and its second connection end is connected to the second power output terminal Vout2; the first connection end of the second switching device Q2 is connected to the second power input terminal Vin2, its control end is connected to the first power input terminal Vin1, and its second connection end is connected to the first power output terminal Vout1; the first connection end of the third switching device Q3 is connected to the first power input terminal Vin1, its control end is connected to the second power input terminal Vin2, and its second connection end is connected to the second power output terminal Vout2; the first connection end of the fourth switching device Q4 is connected to the first power input terminal Vin1, its control end is connected to the second power input terminal Vin2, and its second connection end is connected to the first power output terminal Vout1.

[0010] Compared with the prior art, the present utility model uses multiple components with better on-resistance or stronger current-carrying capacity for switches to build a circuit, realizing that a high-power load can work normally when the input power supply is connected in reverse, adapting to the input polarity of the power supply.

Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. Among them:

[0012] Figure 1 It is an application circuit for adapting to the positive and negative connection of a power load in the prior art;

[0013] Figure 2 It is a schematic diagram of the adaptive power supply positive and negative connection circuit in an embodiment of the present utility model;

[0014] Figure 3 It is a schematic diagram of the adaptive power supply positive and negative connection circuit in another embodiment of the present utility model.

Detailed Embodiment

[0015] To make the above objects, features, and advantages of the present utility model more apparent and understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] As used herein, the term "one embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present utility model. The phrase "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it an individual or alternative embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words indicating electrical connection such as "coupled", "connected", "linked", and "joined" in this article all mean directly or indirectly connected. For example, when A is connected to B, it includes both A and B being directly electrically connected, and also A being connected to B through electrical components or circuits.

[0017] In the description of the present utility model, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "front", "rear", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings. These are only for the convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present utility model.

[0018] Please refer to Figure 2 shown, which is a schematic diagram of the adaptive power supply positive and negative connection circuit in one embodiment of the present utility model. Figure 2 The shown adaptive power supply positive and negative connection circuit includes a first switching device Q1, a second switching device Q2, a third switching device Q3, a fourth switching device Q4, a first power input terminal Vin1, a second power input terminal Vin2, a first power output terminal Vout1, and a second power output terminal Vout2.

[0019] Among them, the first connection end of the first switching device Q1 is connected to the second power input terminal Vin2, its control end is connected to the first power input terminal Vin1, and its second connection end is connected to the second power output terminal Vout2; the first connection end of the second switching device Q2 is connected to the second power input terminal Vin2, its control end is connected to the first power input terminal Vin1, and its second connection end is connected to the first power output terminal Vout1; the first connection end of the third switching device Q3 is connected to the first power input terminal Vin1, its control end is connected to the second power input terminal Vin2, and its second connection end is connected to the second power output terminal Vinout2; the first connection end of the fourth switching device Q4 is connected to the first power input terminal Vin1, its control end is connected to the second power input terminal Vin2, and its second connection end is connected to the first power output terminal Vout1.

[0020] When the positive pole Vin of the power supply 210 is connected to the second power supply input terminal Vin2 and the negative pole GND of the power supply 210 is connected to the first power supply input terminal Vin1, the first switching device Q1 is turned off, the second switching device Q2 is turned on, the third switching device Q3 is turned on, and the fourth switching device Q4 is turned off, so that the first power supply output terminal Vout1 is the positive pole and the second power supply output terminal Vout2 is the negative pole; when the negative pole GND of the power supply 210 is connected to the second power supply input terminal Vin2 and the positive pole Vin of the power supply 210 is connected to the first power supply input terminal Vin1, the first switching device Q1 is turned on, the second switching device Q2 is turned off, the third switching device Q3 is turned off, and the fourth switching device Q4 is turned on, so that the first power supply output terminal Vout1 is the positive pole and the second power supply output terminal Vout2 is the negative pole. Thus, in the case of reverse connection of the power supply, the first power supply output terminal Vout1 is always the positive pole and the second power supply output terminal Vout2 is always the negative pole.

[0021] In Figure 2 In the specific embodiment shown, one end of the load RL is connected to the first power supply output terminal Vout1 and the other end is connected to the second power supply output terminal Vout2; one end of the capacitor C1 is connected to the first power supply output terminal Vout1 and the other end is connected to the second power supply output terminal Vout2.

[0022] In Figure 2 In the specific embodiment shown, the first switching device Q1 is an NMOS transistor (N-Metal-Oxide-Semiconductor), and the first connection terminal, the second connection terminal, and the control terminal of the first switching device Q1 are the drain, the source, and the gate of the NMOS transistor respectively; the second switching device Q2 is a PMOS transistor (positive channel Metal Oxide Semiconductor), and the first connection terminal, the second connection terminal, and the control terminal of the second switching device Q2 are the drain, the source, and the gate of the PMOS transistor respectively; the third switching device Q3 is an NMOS transistor, and the first connection terminal, the second connection terminal, and the control terminal of the third switching device Q3 are the drain, the source, and the gate of the NMOS transistor respectively; the fourth switching device Q4 is a PMOS transistor, and the first connection terminal, the second connection terminal, and the control terminal of the fourth switching device Q4 are the drain, the source, and the gate of the PMOS transistor respectively.

[0023] Figure 2The shown adaptive power supply positive and negative connection circuit further includes a resistor R102, a resistor R104, a resistor R108, and a resistor R106. Among them, one end of the resistor R102 is connected to the control end of the first switching device Q1, and the other end is connected to the first power input terminal Vin1; one end of the resistor R104 is connected to the control end of the second switching device Q2, and the other end is connected to the first power input terminal Vin1; one end of the resistor R108 is connected to the control end of the third switching device Q3, and the other end is connected to the second power input terminal Vin2; one end of the resistor R106 is connected to the control end of the fourth switching device Q4, and the other end is connected to the second power input terminal Vin2.

[0024] Figure 2 The shown adaptive power supply positive and negative connection circuit further includes a resistor R101, a resistor R103, a resistor R107, and a resistor R105. Among them, one end of the resistor R101 is connected to the second connection end of the first switching device Q1, and the other end is connected to the control end of the first switching device Q1; one end of the resistor R103 is connected to the second connection end of the second switching device Q2, and the other end is connected to the control end of the second switching device Q2; one end of the resistor R107 is connected to the second connection end of the third switching device Q3, and the other end is connected to the control end of the third switching device Q3; one end of the resistor R105 is connected to the second connection end of the fourth switching device Q4, and the other end is connected to the control end of the fourth switching device Q4.

[0025] Among them, the selection of the resistance values of the resistor R101 and the resistor R102 satisfies: making the first switching device Q1 within the safe voltage range of conduction and cutoff; the selection of the resistance values of the resistor R103 and the resistor R104 satisfies: making the second switching device Q2 within the safe voltage range of conduction and cutoff; the selection of the resistance values of the resistor R105 and the resistor R106 satisfies: making the fourth switching device Q4 within the safe voltage range of conduction and cutoff; the selection of the resistance values of the resistor R107 and the resistor R108 satisfies: making the third switching device Q3 within the safe voltage range of conduction and cutoff.

[0026] Based on the selection of the resistance values of the resistor R101 and the resistor R102, the conduction and cutoff response time of the first switching device Q1 can be set; based on the selection of the resistance values of the resistor R103 and the resistor R104, the conduction and cutoff response time of the second switching device Q2 can be set; based on the selection of the resistance values of the resistor R105 and the resistor R106, the conduction and cutoff response time of the fourth switching device Q4 can be set; based on the selection of the resistance values of the resistor R107 and the resistor R108, the conduction and cutoff response time of the third switching device Q3 can be set. In this way, based on the selection of the resistance values of the resistor R101 to the resistor R108, it can be set Figure 2The response time of the shown adaptive power supply reverse and forward connection circuit from power-on to supplying power to the load RL. In other words, the design of resistors R101 to R108 can keep the Vgs of MOS transistors Q1 to Q4 within a safe voltage range, meet the conditions for conduction and cutoff, and set the response time of the conduction and cutoff of the MOS transistors from power-on to the output of Vout1 to Vout2.

[0027] The following is a specific introduction Figure 2 The working process of the shown adaptive power supply reverse and forward connection circuit. Among them, the on-voltage drops of the body diodes of MOS transistors Q1, Q2, Q3, and Q4 are all 0.7V.

[0028] 1. When the power supply is connected in the forward direction (that is, when the positive pole Vin of the power supply 210 is connected to the second power input terminal Vin2, and the negative pole GND of the power supply 210 is connected to the first power input terminal Vin1): Q2 is a PMOS transistor. The direction of the body diode of Q2 is the same as the current direction, so the body diode conducts, making the source voltage Vs of MOS transistor Q2 approximately Vin - 0.7V. Q2_Vgs = (Vin1 - Q2_Vs) * R103 / (R103 + R104) = (0V - (Vin - 0.7V)) * R103 / (R103 + R104). Q2_Vgs is the gate-source voltage of PMOS transistor Q2.

[0029] Design R103 / (R103 + R104) to be approximately 1 (or make Q2_Vgs meet the voltage range of the Vgs specification requirements). Therefore, Q2_Vgs ≈ -Vin + 0.7V.

[0030] Q2_Vgs < Vgs(th) (Vgs(th) is the turn-on voltage of the MOS transistor), and PMOS transistor Q2 conducts. At this time, Q2_Vs will be approximately equal to Vin2 = Vin.

[0031] So the first power output terminal Vout1 is the positive pole;

[0032] Q4 is a PMOS transistor. Q4_Vd (Vd is the drain voltage of the MOS transistor) = Vin1 = GND, Q4_Vs = Q2_Vs = Vout1 ≈ Vin2 = Vin. Therefore, the body diode of PMOS transistor Q4 is cut off.

[0033] Q4_Vgs = (Vin2 - Q4_Vs) * R105 / (R106 + R105) ≈ (Vin - Vin) * R105 / (R106 + R105) ≈ 0V.

[0034] Q4_Vgs > Vgs(th). Therefore, PMOS transistor Q4 is cut off; the first power output terminal Vout1 will not be short-circuited to the first power input terminal Vin1 through PMOS transistor Q4.

[0035] The current passes through the load RL. The body diode of the NMOS transistor Q3 has the same direction as the current direction, so the body diode conducts, and Q3_Vs = 0.7V.

[0036] Q3_Vgs = (Vin2 - Q3_Vs) * R107 / (R108 + R107) = (Vin - 0.7V) * R107 / (R108 + R107)

[0037] Design R107 / (R108 + R107) to be approximately 1 (or make Q3_Vgs meet the voltage range requirements of the Vgs specification). Therefore, Q3_Vgs ≈ Vin - 0.7V.

[0038] Q3_Vgs > Vgs(th), the NMOS transistor Q3 conducts. At this time, Q3_Vs will be approximately equal to Vin1 = GND.

[0039] So the second power supply output terminal Vout2 is the negative pole.

[0040] Q1 is an NMOS transistor, Q1_Vd = Vin2 = Vin, Q1_Vs = Q3_Vs ≈ Vin1 = GND. Therefore, the body diode of the NMOS transistor Q1 is cut off.

[0041] Q1_Vgs = (Vin1 - Q1_Vs) * R101 / (R101 + R102) ≈ (GND - GND) * R101 / (R101 + R102) ≈ 0V.

[0042] Q1_Vgs < Vgs(th), so the NMOS transistor Q1 is cut off (or turned off); the second power supply output terminal Vout2 will not be short - circuited to the second power supply input terminal Vin2 through the NMOS transistor Q1.

[0043] 2. When the power supply is reversely connected (that is, when the negative pole GND of the power supply 210 is connected to the second power supply input terminal Vin2, and the positive pole Vin of the power supply 210 is connected to the first power supply input terminal Vin1): Q4 is a PMOS transistor. The body diode of Q4 has the same direction as the current direction, so the body diode conducts, making the MOS transistor Q4_Vs approximately Vin - 0.7V.

[0044] Q4_Vgs = (Vin2 - Q4_Vs) * R105 / (R106 + R105) = (0V - (Vin - 0.7V)) * R105 / (R106 + R105).

[0045] Design R105 / (R106 + R105) to be approximately 1 (or make Q4_Vgs meet the voltage range requirements of the Vgs specification). Therefore, Q4_Vgs ≈ -Vin + 0.7V.

[0046] When Q4_Vgs < Vgs(th), PMOS transistor Q4 conducts. At this time, Q4_Vs will be approximately equal to Vin1 = Vin.

[0047] Therefore, the first power output terminal Vout1 is positive.

[0048] Q2 is a PMOS transistor, Q2_Vd = Vin2 = GND, Q2_Vs = Q4_Vs = Vout1 ≈ Vin1 = Vin. Therefore, the body diode of PMOS transistor Q2 is cut off.

[0049] Q2_Vgs = (Vin1 - Q2_Vs) * R103 / (R103 + R104) ≈ (Vin - Vin) * R103 / (R103 + R104) ≈ 0V.

[0050] Q2_Vgs > Vgs(th). Therefore, PMOS transistor Q2 is cut off; the first power output terminal Vout1 will not be short - circuited to the second power input terminal Vin2 through PMOS transistor Q2.

[0051] The current passes through the load RL. The direction of the body diode of NMOS transistor Q1 is the same as the current direction, so the body diode conducts and Q1_Vs = 0.7V.

[0052] Q1_Vgs = (Vin1 - Q1_Vs) * R101 / (R101 + R102) = (Vin - 0.7V) * R101 / (R101 + R102)

[0053] Design R101 / (R101 + R102) to be approximately 1 (or make Q1_Vgs meet the voltage range of the Vgs specification requirements). Therefore, Q1_Vgs ≈ Vin - 0.7V.

[0054] Q1_Vgs > Vgs(th), NMOS transistor Q1 conducts. At this time, Q1_Vs will be approximately equal to Vin2 = GND.

[0055] Therefore, the second power output terminal Vout2 is negative.

[0056] Q3 is an NMOS transistor, Q3_Vd = Vin1 = Vin, Q3_Vs = Q1_Vs ≈ Vin2 = GND. Therefore, the body diode of Q3 is cut off.

[0057] Q3_Vgs = (Vin2 - Q3_Vs) * R107 / (R107 + R108) ≈ (GND - GND) * R107 / (R107 + R108) ≈ 0V.

[0058] Q3_Vgs < Vgs(th), so the NMOS transistor Q3 is cut off (or turned off); the second power output terminal Vout2 will not be short-circuited to the first power input terminal Vin1 through the NMOS transistor Q3.

[0059] That is to say, when the power supply is connected correctly, the positive pole Vin of the power supply 210 is connected to the second power input terminal Vin2, and the negative pole GND of the power supply 210 is connected to the first power input terminal Vin1. The Vgs of the PMOS transistor Q2 < Vgs(th) is turned on, the Vgs of the PMOS transistor Q4 > Vgs(th) is turned off, the Vgs of the NMOS transistor Q3 > Vgs(th) is turned on, and the Vgs of the NMOS transistor Q1 < Vgs(th) is turned off. Therefore, the first power output terminal Vout1 connected to the load RL is the positive pole, and the second power output terminal Vout2 is the negative pole. When the power supply is connected reversely, the negative pole GND of the power supply 210 is connected to the second power input terminal Vin2, and the positive pole Vin of the power supply 210 is connected to the first power input terminal Vin1. The Vgs of the PMOS transistor Q2 > Vgs(th) is turned off, the Vgs of the PMOS transistor Q4 < Vgs(th) is turned on, the Vgs of the NMOS transistor Q3 < Vgs(th) is turned off, and the Vgs of the NMOS transistor Q1 > Vgs(th) is turned on. Still, the first power output terminal Vout1 connected to the load RL is the positive pole, and the second power output terminal Vout2 is the negative pole, thus realizing that in the case of the power supply being connected correctly or reversely, the first power output terminal Vout1 connected to the load RL is the positive pole, and the second power output terminal Vout2 is the negative pole.

[0060] It should be particularly noted that: 1. The MOS transistors Q1, Q2, Q3, and Q4 can be replaced with other components with better conduction impedance or stronger current-carrying capacity for switching; 2. The MOS transistors Q1, Q2, Q3, and Q4 can be connected in parallel in multiple numbers to make the conduction impedance smaller, the heat of a single MOS transistor lower, and the voltage drop lower.

[0061] Please refer to Figure 3 shown, which is a schematic diagram of the adaptive power supply reverse connection circuit in another embodiment of the present invention. Compared with Figure 2 In Figure 3In the shown adaptive power supply forward and reverse connection circuit, replace the resistor R101 with the zener diode D1; replace the resistor R103 with the zener diode D2; replace the resistor R107 with the zener diode D3; replace the resistor R105 with the zener diode D4. Among them, the positive electrode of the zener diode D1 is connected to the second connection end of the first switching device Q1, and its negative electrode is connected to the control end of the first switching device Q1; the negative electrode of the zener diode D2 is connected to the second connection end of the second switching device Q2, and its positive electrode is connected to the control end of the second switching device Q2; the positive electrode of the zener diode D3 is connected to the second connection end of the third switching device Q3, and its negative electrode is connected to the control end of the third switching device Q3; the negative electrode of the zener diode D4 is connected to the second connection end of the fourth switching device Q4, and its positive electrode is connected to the control end of the fourth switching device Q4.

[0062] Among them, the zener diode D1 plays a role in protecting the NMOS transistor Q1. When the power supply voltage Vin exceeds the Vgs requirement, it can clamp the Vgs (i.e., the gate-source voltage) of the NMOS transistor Q1 at the regulated voltage value to prevent the voltage between the gate and the source of the NMOS transistor Q1 from exceeding the rated voltage value (or exceeding the breakdown voltage between the gate and the source of the NMOS transistor Q1). It can also be said that the operating voltage value of the zener diode D1 is greater than the turn-on voltage value of the NMOS transistor Q1 and less than the maximum rated voltage value between the gate and the source of the NMOS transistor Q1, where the turn-on voltage value of the NMOS transistor Q1 is less than the maximum rated voltage value between the gate and the source of the NMOS transistor Q1.

[0063] The zener diode D2 plays a role in protecting the PMOS transistor Q2. When the power supply voltage Vin exceeds the Vgs requirement, it can clamp the Vgs (i.e., the gate-source voltage) of the PMOS transistor Q2 at the regulated voltage value to prevent the voltage between the gate and the source of the PMOS transistor Q2 from exceeding the rated voltage value (or exceeding the breakdown voltage between the gate and the source of the PMOS transistor Q2). It can also be said that the operating voltage value of the zener diode D2 is greater than the absolute value of the turn-on voltage value of the PMOS transistor Q2 and less than the absolute value of the maximum rated voltage value between the gate and the source of the PMOS transistor Q2, where the absolute value of the turn-on voltage value of the PMOS transistor Q2 is less than the absolute value of the maximum rated voltage value between the gate and the source of the PMOS transistor Q2, where the turn-on voltage value of the PMOS transistor Q2 is negative, and the maximum rated voltage value between the gate and the source of the PMOS transistor Q2 is negative.

[0064] Similarly, the zener diode D3 plays a role in protecting the NMOS transistor Q3. When the power supply voltage Vin exceeds the Vgs requirement, it can clamp the Vgs (i.e., the gate-source voltage) of the NMOS transistor Q3 at the regulated voltage value to prevent the voltage between the gate and source of the NMOS transistor Q3 from exceeding the rated voltage value (or exceeding the breakdown voltage between the gate and source of the NMOS transistor Q3). It can also be said that the operating voltage value of the zener diode D3 is greater than the turn-on voltage value of the NMOS transistor Q3 and less than the maximum rated voltage value between the gate and source of the NMOS transistor Q3, where the turn-on voltage value of the NMOS transistor Q3 is less than the maximum rated voltage value between the gate and source of the NMOS transistor Q3.

[0065] The zener diode D4 plays a role in protecting the PMOS transistor Q4. When the power supply voltage Vin exceeds the Vgs requirement, it can clamp the Vgs (i.e., the gate-source voltage) of the PMOS transistor Q4 at the regulated voltage value to prevent the voltage between the gate and source of the PMOS transistor Q4 from exceeding the rated voltage value (or exceeding the breakdown voltage between the gate and source of the PMOS transistor Q4). It can also be said that the operating voltage value of the zener diode D4 is greater than the absolute value of the turn-on voltage value of the PMOS transistor Q4 and less than the absolute value of the maximum rated voltage value between the gate and source of the PMOS transistor Q4, where the absolute value of the turn-on voltage value of the PMOS transistor Q4 is less than the absolute value of the maximum rated voltage value between the gate and source of the PMOS transistor Q4, where the turn-on voltage value of the PMOS transistor Q4 is negative and the maximum rated voltage value between the gate and source of the PMOS transistor Q4 is negative.

[0066] In summary, through the combination of NMOS transistors and PMOS transistors and the design of resistors, the present invention enables the MOS transistors Q1, Q2, Q3, and Q4 to operate in a safe voltage range and can also keep the MOS transistors Q1, Q2, Q3, and Q4 in a reasonable off or on state. Since the on-resistance of the MOS transistor is extremely small (only a dozen milliohms), the MOS transistor can pass a larger operating current, so a higher power can be output. When the power supply is connected to the circuit in either the positive or negative direction, the first power output terminal Vout1 connected to the load RL is always positive, and the second power output terminal Vout2 is always negative, realizing that the high-power load can work normally when the input power supply is connected in either the positive or negative direction, adapting to the power supply input polarity. In addition, due to the low on-resistance of the MOS transistor when it is on, the on-voltage drop is low, the power consumption on the MOS transistor is smaller, and the heat generated is lower. No heat sink is required under a certain operating current, which does not affect the structural space.

[0067] It should be noted that any changes made by those skilled in the art to the specific embodiments of the present invention do not depart from the scope of the claims of the present invention. Correspondingly, the scope of the claims of the present invention is not limited to the foregoing specific embodiments.

Claims

1. An adaptive power supply forward and reverse connection circuit, characterized in that: It includes a first switch device Q1, a second switch device Q2, a third switch device Q3, a fourth switch device Q4, a first power input terminal Vin1, a second power input terminal Vin2, a first power output terminal Vout1 and a second power output terminal Vout2, The first connection end of the first switching device Q1 is connected to the second power input terminal Vin2, the control end thereof is connected to the first power input terminal Vin1, and the second connection end thereof is connected to the second power output terminal Vout2; the first connection end of the second switching device Q2 is connected to the second power input terminal Vin2, the control end thereof is connected to the first power input terminal Vin1, and the second connection end thereof is connected to the first power output terminal Vout1; the first connection end of the third switching device Q3 is connected to the first power input terminal Vin1, the control end thereof is connected to the second power input terminal Vin2, and the second connection end thereof is connected to the second power output terminal Vout2; the first connection end of the fourth switching device Q4 is connected to the first power input terminal Vin1, the control end thereof is connected to the second power input terminal Vin2, and the second connection end thereof is connected to the first power output terminal Vout1.

2. The adaptive power supply forward and reverse connection circuit according to claim 1, characterized in that: When the positive electrode of the power supply is connected to the second power input terminal Vin2 and the negative electrode of the power supply is connected to the first power input terminal Vin1, the first switch device Q1 is turned off, the second switch device Q2 is turned on, the third switch device Q3 is turned on, and the fourth switch device Q4 is turned off, so that the first power output terminal Vout1 is positive and the second power output terminal Vout2 is negative; When the negative electrode of the power supply is connected to the second power input terminal Vin2 and the positive electrode of the power supply is connected to the first power input terminal Vin1, the first switch device Q1 is turned on, the second switch device Q2 is turned off, the third switch device Q3 is turned off, and the fourth switch device Q4 is turned on, so that the first power output terminal Vout1 is the positive electrode and the second power output terminal Vout2 is the negative electrode.

3. The adaptive power supply forward and reverse connection circuit according to claim 2, characterized in that: The first switch device Q1 is an NMOS tube, and the first connection terminal, the second connection terminal and the control terminal of the first switch device Q1 are respectively the drain, the source and the gate of the NMOS tube; The second switch device Q2 is a PMOS tube, and the first connection terminal, the second connection terminal and the control terminal of the second switch device Q2 are respectively the drain, the source and the gate of the PMOS tube; The third switch device Q3 is an NMOS tube, and the first connection terminal, the second connection terminal and the control terminal of the third switch device Q3 are respectively the drain, the source and the gate of the NMOS tube; The fourth switch device Q4 is a PMOS tube, and the first connection terminal, the second connection terminal and the control terminal of the fourth switch device Q4 are respectively the drain, the source and the gate of the PMOS tube.

4. The adaptive power supply forward and reverse connection circuit according to claim 3, characterized in that: It also includes a resistor R102, a resistor R104, a resistor R108 and a resistor R106, One end of the resistor R102 is connected to the control end of the first switch device Q1, and the other end thereof is connected to the first power input end Vin1; One end of the resistor R104 is connected to the control end of the second switch device Q2, and the other end thereof is connected to the first power input end Vin1; One end of the resistor R108 is connected to the control end of the third switch device Q3, and the other end thereof is connected to the second power input end Vin2; One end of the resistor R106 is connected to the control end of the fourth switch device Q4, and the other end of the resistor R106 is connected to the second power input end Vin2.

5. The adaptive power supply forward and reverse connection circuit according to claim 4, characterized in that: It also includes a resistor R101, a resistor R103, a resistor R107 and a resistor R105, One end of the resistor R101 is connected to the second connection end of the first switch device Q1, and the other end of the resistor R101 is connected to the control end of the first switch device Q1; One end of the resistor R103 is connected to the second connection end of the second switch device Q2, and the other end of the resistor R103 is connected to the control end of the second switch device Q2; One end of the resistor R107 is connected to the second connection end of the third switch device Q3, and the other end of the resistor R107 is connected to the control end of the third switch device Q3; One end of the resistor R105 is connected to the second connection end of the fourth switch device Q4 , and the other end of the resistor R105 is connected to the control end of the fourth switch device Q4 .

6. The adaptive power supply forward and reverse connection circuit according to claim 5, characterized in that: The resistance values ​​of the resistor R101 and the resistor R102 are selected to ensure that the first switch device Q1 is within a safe voltage range for on and off; The resistance values ​​of the resistor R103 and the resistor R104 are selected to ensure that the second switch device Q2 is within a safe voltage range for on and off; The resistance values ​​of the resistor R105 and the resistor R106 are selected to ensure that: the fourth switch device Q4 is within a safe voltage range for on and off; The resistance values ​​of the resistor R107 and the resistor R108 are selected to ensure that the third switch device Q3 is within a safe voltage range for turning on and off.

7. The adaptive power supply forward and reverse connection circuit according to claim 6, characterized in that: Based on the selection of the resistance values ​​of the resistor R101 and the resistor R102, setting the response time of turning on and off the first switch device Q1; Based on the selection of the resistance values ​​of the resistor R103 and the resistor R104, setting the response time of turning on and off the second switch device Q2; Based on the selection of the resistance values ​​of the resistor R105 and the resistor R106, setting the response time of turning on and off the fourth switch device Q4; Based on the selection of the resistance values ​​of the resistor R107 and the resistor R108, setting the response time of turning on and off the third switch device Q3; Based on the resistance value selection of the resistors R101 to R108, the response time of the adaptive power supply forward and reverse connection circuit from power-on to power supply is set.

8. The adaptive power supply forward and reverse connection circuit according to claim 4, characterized in that: It also includes a Zener diode D1, a Zener diode D2, a Zener diode D3 and a Zener diode D4. The positive electrode of the voltage stabilizing diode D1 is connected to the second connection terminal of the first switch device Q1, and the negative electrode thereof is connected to the control terminal of the first switch device Q1; The cathode of the voltage stabilizing diode D2 is connected to the second connection terminal of the second switch device Q2, and the anode of the voltage stabilizing diode D2 is connected to the control terminal of the second switch device Q2; The positive electrode of the voltage stabilizing diode D3 is connected to the second connection terminal of the third switch device Q3, and the negative electrode thereof is connected to the control terminal of the third switch device Q3; The cathode of the voltage stabilizing diode D4 is connected to the second connection terminal of the fourth switch device Q4, and the anode of the voltage stabilizing diode D4 is connected to the control terminal of the fourth switch device Q4.

9. The adaptive power supply forward and reverse connection circuit according to claim 8, characterized in that: The operating voltage value of the voltage stabilizing diode D1 is greater than the turn-on voltage value of the NMOS tube Q1 and less than the maximum rated voltage value between the gate and the source of the NMOS tube Q1, wherein the turn-on voltage value of the NMOS tube Q1 is less than the maximum rated voltage value between the gate and the source of the NMOS tube Q1; The operating voltage value of the voltage zener diode D2 is greater than the absolute value of the turn-on voltage value of the PMOS tube Q2 and less than the absolute value of the maximum rated voltage value between the gate and the source of the PMOS tube Q2, wherein the absolute value of the turn-on voltage value of the PMOS tube Q2 is less than the absolute value of the maximum rated voltage value between the gate and the source of the PMOS tube Q2; The operating voltage value of the voltage stabilizing diode D3 is greater than the turn-on voltage value of the NMOS tube Q3 and less than the maximum rated voltage value between the gate and the source of the NMOS tube Q3, wherein the turn-on voltage value of the NMOS tube Q3 is less than the maximum rated voltage value between the gate and the source of the NMOS tube Q3; The operating voltage value of the Zener diode D4 is greater than the absolute value of the turn-on voltage value of the PMOS tube Q4 and less than the absolute value of the maximum rated voltage value between the gate and the source of the PMOS tube Q4, wherein the absolute value of the turn-on voltage value of the PMOS tube Q4 is less than the absolute value of the maximum rated voltage value between the gate and the source of the PMOS tube Q4.

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