Multipath selection circuit, measuring system, measuring instrument and battery system

Abstract

The utility model provides a multi-path selection circuit, a measuring system, a measuring instrument and a battery system, which relate to the technical field of signal transmission and comprise an input unit, a primary switching circuit, a secondary switching circuit, a control unit and an output unit, for each primary switch circuit, the first input end is connected with the input unit; for each secondary switch circuit, the second input end is connected with the first output end of each primary switch, and each first output end of each primary switch corresponds to a different second input end; for each output unit, each third input end is connected with the second output end of one secondary switch, and each third input end corresponds to one non-repeated second output end on different secondary switches; the controller is connected with the first control end and the second control end. The multi-channel selector solves the problems that in the prior art, the number of channels of the multi-channel selector is too small, switching of one group of input signals corresponding to multiple groups of output channels is difficult, and the sequence of the input signals is difficult to switch.

Description

Technical Field

[0001] The utility model relates to the technical field of signal transmission, and particularly to the technical fields of a multiplexing circuit, a measurement system, a measuring instrument and a battery system. Background Art

[0002] When measuring the sheet resistance of the surface of a silicon wafer of a solar cell in the prior art, when it is necessary to sort the target signals and selectively output them to the target output channels, a two-channel analog multi-group lighting control card circuit such as the one described in the application number: 202022610399.9 is usually adopted. By using the regulation of a control chip, the signals are sorted and the channels are selected for output.

[0003] However, in this structure, there are still problems that the number of channels of the multiplexer is too small, it is difficult to switch a group of input signals corresponding to multiple groups of output channels, and it is difficult to switch the order of the input signals, resulting in the switching speed not meeting the required requirements. Summary of the Utility Model

[0004] Aiming at the deficiencies in the prior art, the utility model provides a multiplexing circuit, a measurement system, a measuring instrument and a battery system, which solve the problems in the prior art that the number of channels of the multiplexer is too small, it is difficult to switch a group of input signals corresponding to multiple groups of output channels, and it is difficult to switch the order of the input signals.

[0005] At least one embodiment of the utility model provides a multiplexing circuit, including: an input unit, a first-stage switch circuit, a second-stage switch circuit, a control unit and an output unit. Among them, there are multiple first-stage switch circuits, second-stage switch circuits and output units. Each first-stage switch circuit has a first input end, multiple first output ends and a first control end. Each second-stage switch circuit has a second input end, multiple second output ends and a second control end. Each output unit has multiple third input ends;

[0006] For each first-stage switch circuit, the first input end is connected to the input unit;

[0007] For each second-stage switch circuit, the second input end is connected to the first output end of each first-stage switch, and among them, each first output end of each first-stage switch corresponds to a different second input end;

[0008] For each output unit, each third input end is connected to the second output end of one of the second-stage switches, and among them, each third input end corresponds to a non-repeating second output end on a different second-stage switch;

[0009] The controller is connected to each first control end and each second control end.

[0010] The technical solution provided by the present utility model at least has the following beneficial effects:

[0011] By using the cooperation of the primary switch circuit and the secondary switch circuit, the primary switch circuit can be used to change the order of multiple signals transmitted by the input unit, and the secondary switch circuit can also be used to switch between multiple output ports for the multiple signals whose order has been changed, so as to control the information of the preset signal order output by any output unit.

[0012] In a multiplexer circuit provided in one embodiment of the present utility model, the number of the primary switch circuit, the secondary switch circuit, the first output terminal located on the same primary switch circuit, the second input terminal located on the same secondary switch circuit, and the third input terminal located on the same output unit is the same as the number of terminals of the input unit.

[0013] The technical solution provided by the present utility model at least has the following beneficial effects:

[0014] The above-mentioned primary switch circuit, secondary switch circuit, first output terminal, second output terminal and third input terminal with the same number can just realize the sorting and switching of the input unit signals to be received, ensuring the maximum utilization of the terminals.

[0015] In a multiplexer circuit provided in one embodiment of the present utility model, the number of terminals of the output unit is 4, the primary switch circuit is a 4-channel analog switch circuit, and the secondary switch circuit is a 16-channel analog switch circuit.

[0016] The technical solution provided by the present utility model at least has the following beneficial effects:

[0017] Both the 4-channel analog switch circuit and the 16-channel analog switch circuit can receive a signal from the input terminal according to the signal of their control terminals and output the above signal at one of their output terminals;

[0018] Furthermore, the four signals of the input unit can be re-sorted and switched to one output unit that needs to be output without generating other redundant signals.

[0019] In a multiplexer circuit provided in one embodiment of the present utility model, the control unit includes 8 third control terminals and 4 fourth control terminals;

[0020] Each of the 4-channel analog switch circuits has 2 first control terminals, and 8 of the third control terminals are respectively connected to one of the first control terminals without repetition;

[0021] Each of the 16-channel analog switch circuits has 4 second control terminals, and for each of the fourth control terminals, it is connected to a non-repeating second control terminal on each of the 16-channel analog switch circuits.

[0022] The technical solution provided by the present utility model at least has the following beneficial effects:

[0023] Through the above connection method, the third control terminal can be used to independently control each first control terminal, so as to realize any sorting and output of the signals of the input unit. The fourth control terminal is used to commonly control each second control terminal, so as to realize the selective output of the sorted signals.

[0024] In a multiplexer circuit provided in one embodiment of the present utility model, the number of second output terminals on each of the secondary switch circuits and the number of output units are both 16.

[0025] The technical solution provided by the present utility model at least has the following beneficial effects:

[0026] By using 16 output units, the maximum utilization of ports can be realized.

[0027] In a multiplexer circuit provided in one embodiment of the present utility model, the first output terminals on each of the 4-channel analog switch circuits are respectively the first output terminal S1, the first output terminal S2, the first output terminal S3, and the first output terminal S4. Among them,

[0028] The second input terminal of the first 16-channel analog switch circuit is connected to each of the first output terminals S1, the second input terminal of the second 16-channel analog switch circuit is connected to each of the first output terminals S2, the second input terminal of the third 16-channel analog switch circuit is connected to each of the first output terminals S3, and the second input terminal of the fourth 16-channel analog switch circuit is connected to each of the first output terminals S4.

[0029] The technical solution provided by the present utility model at least has the following beneficial effects:

[0030] After the above connection, at this time, under the control signal of the control unit, the first 4-channel analog switch circuit can output a signal at its first output terminal, and this signal can be transmitted to one of the 16-channel analog switch circuits. At the same time, under the control signal of the control unit, the second 4-channel analog switch circuit can output a signal at its first output terminal, and this signal can be transmitted to another 16-channel analog switch circuit, until the last signal is transmitted to the last 16-channel analog switch circuit. Thus, after the four input signals are sorted by the 4-channel switch analog circuit, they are sequentially output to different 16-channel analog switch circuits, so as to facilitate the output of the above 16-channel analog switch circuit to a preset output unit.

[0031] In a multiplexing circuit provided in one embodiment of the present invention, the control unit is an MCU chip.

[0032] The MCU chip can quickly and accurately control the output terminals of the first-stage switch circuit and the second-stage switch circuit.

[0033] One embodiment of the present invention further provides a surface sheet resistance measurement system for a solar cell silicon wafer, including a multiplexing circuit as described above.

[0034] One embodiment of the present invention further provides a surface sheet resistance measuring instrument for a solar cell silicon wafer, including a multiplexing circuit as described above.

[0035] One embodiment of the present invention further provides a solar cell system, which is characterized in that it includes a surface sheet resistance measurement system for a solar cell silicon wafer as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the specific connection relationship of a multiplexing circuit according to the present invention;

[0037] Figure 2 It is a schematic diagram of the principle of a multiplexing circuit according to the present invention;

[0038] Figure 3 It is a control logic diagram of the MCU control chip for the 4-channel analog switch circuit according to the present invention;

[0039] Figure 4 It is a control logic diagram of the MCU control chip for the 16-channel analog switch circuit according to the present invention.

[0040] In the drawings, the list of components represented by each reference numeral is as follows:

[0041] IN, output unit; T1 to T4, first - stage switch circuit; T5 to T8, second - stage switch circuit; MCU, control unit; OUT1 to OUT16, output unit. Detailed implementation mode

[0042] The principles and features of the present utility model will be described below in conjunction with the accompanying drawings. The examples given are only for explaining the present utility model and are not intended to limit the scope of the present utility model.

[0043] In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0044] The present utility model provides a multiplexer circuit. Please refer here Figure 1 As shown, it includes: an input unit IN, a first - stage switch circuit, a second - stage switch circuit, a control unit MCU, and an output unit. Among them,

[0045] There are multiple first - stage switch circuits, second - stage switch circuits, and output units;

[0046] There are multiple above - mentioned first - stage switch circuits. For reference, Figure 1 T1, T2, T3, and T4 in [reference] represent different first - stage switch circuits. In the following text, they are represented and distinguished as first - stage switch circuit T1, first - stage switch circuit T2, first - stage switch circuit T3, and first - stage switch circuit T4;

[0047] Each first - stage switch circuit has a first input terminal, which is represented by the symbol D in the corresponding first - stage switch circuit in Figure 1 ;

[0048] Each first - stage switch circuit also has multiple first output terminals and a first control terminal;

[0049] Among them, for each first - stage switch circuit, the multiple first output terminals can be referred to Figure 1 S1, S2, S3, and S4 in [reference]. For convenience of description, in the following text, they are described and distinguished as first output terminal S1, first output terminal S2, first output terminal S3, and first output terminal S4. The multiple first control terminals can be referred to Figure 1 A0 and A1 in [reference]. For convenience of description, in the following text, they are represented as first control terminal A0 and first control terminal A1;

[0050] That is, the first - stage switch circuit T1, the first - stage switch circuit T2, the first - stage switch circuit T3, and the first - stage switch circuit T4 all include: first control terminal AO, first control terminal A1, first output terminal S1, first output terminal S2, first output terminal S3, first output terminal S4, and first input terminal D;

[0051] Each secondary switch circuit has a second input terminal, a plurality of second output terminals, and a second control terminal, and each output unit has a plurality of third input terminals;

[0052] The above-mentioned plurality of second output terminals can be referred to as T5, T6, T7, and T8 in Figure 1 which respectively represent different secondary switch circuits, and are hereinafter referred to and distinguished as secondary switch circuit T5, secondary switch circuit T6, secondary switch circuit T7, and secondary switch circuit T8;

[0053] Each secondary switch circuit has a second input terminal, which is represented by the symbol D in the corresponding secondary switch circuit in Figure 1 ;

[0054] Each secondary switch circuit also has a plurality of second output terminals and a second control terminal. Among them, for each secondary switch circuit, the plurality of second output terminals are respectively represented by S1, S2... S16 in Figure 1 . For the convenience of description, they are hereinafter described and distinguished as second output terminal S1, second output terminal S2, second output terminal S3, up to second output terminal S16. The plurality of second control terminals are represented by A0, A1, A2, and A3 in Figure 1 ; for the convenience of description, they are hereinafter represented as second control terminal A0, second control terminal A1, second control terminal A2, and second control terminal A3;

[0055] That is, secondary switch circuit T5, secondary switch circuit T6, secondary switch circuit T7, and secondary switch circuit T8 all include: second control terminal A0, second control terminal A1, second control terminal A2, second control terminal A3, second output terminal S1, second output terminal S1, second output terminal S2, second output terminal S3, second output terminal S4, second output terminal S5, second output terminal S7, second output terminal S8, second output terminal S9, second output terminal S10, second output terminal S11, second output terminal S12, second output terminal S13, second output terminal S14, second output terminal S15, second output terminal S16, and second input terminal D;

[0056] For each primary switch circuit, the first input terminal is connected to the input unit IN;

[0057] For each secondary switch circuit, the second input terminal is connected to the first output terminal of each primary switch, where each first output terminal of each primary switch corresponds to a different second input terminal;

[0058] For each output unit, each third input terminal is connected to the second output terminal of one of the secondary switches, where each third input terminal corresponds to a non-repeating second output terminal on a different secondary switch;

[0059] The control unit MCU is connected to each first control terminal and each second control terminal.

[0060] Please refer here Figure 2 As shown, that is, the present utility model adopts the cooperation of a first-level switching circuit and a second-level switching circuit, and under the control of the control unit for the first-level switching circuit and the second-level switching circuit, the first-level switching circuit can be used to change the order of multiple signals transmitted by the input unit, and the second-level switching circuit can also be used to switch between multiple output ports for the multiple signals whose order has been changed, so as to control the information of the preset signal order to be output at any output unit.

[0061] Specifically, the number of the first-level switching circuit, the second-level switching circuit, the first output terminals on the same first-level switching circuit, the second input terminals on the same second-level switching circuit, and the third input terminals on the same output unit are all the same as the number of terminals of the input unit;

[0062] The above-mentioned first-level switching circuit, second-level switching circuit, and first output terminals, second output terminals, and third input terminals with the same number can just realize the sorting and switching of the input unit signals to be received, ensuring the maximum utilization of the terminals.

[0063] Specifically, the number of terminals of the output unit is 4, such as Figure 1 In the figure, the 1st terminal, 2nd terminal, 3rd terminal, and 4th terminal of the input unit, the first-level switching circuit is a 4-channel analog switching circuit, and the second-level switching circuit is a 16-channel analog switching circuit;

[0064] The 1st terminal of the input unit is connected to the first input terminal D of the first first-level switching circuit, the 2nd terminal of the input unit is connected to the first input terminal D of the second first-level switching circuit, the 3rd terminal of the input unit is connected to the first input terminal D of the third first-level switching circuit, and the 4th terminal of the input unit is connected to the first input terminal D of the fourth first-level switching circuit.

[0065] Both the 4-channel analog switching circuit and the 16-channel analog switching circuit can receive a signal from the input terminal according to the signal of its control terminal and output the above signal at one of its output terminals;

[0066] Furthermore, the four signals of the input unit are re-sorted and switched to one output unit that needs to be output, without generating other redundant signals.

[0067] Specifically, the control unit includes 8 third control terminals and 4 fourth control terminals. Among them, as Figure 1 shown, the 8 third control terminals are respectively P1 to P8 of the control unit, and the 4 fourth control terminals are respectively P9 to P12 of the control unit;

[0068] Each 4-channel analog switch circuit has 2 first control terminals, and 8 third control terminals are respectively connected to a non-repeating first control terminal;

[0069] Each 16-channel analog switch circuit has 4 second control terminals. For each fourth control terminal, it is connected to a non-repeating second control terminal on each 16-channel analog switch circuit.

[0070] That is, the third control terminal P1 of the control unit MCU is connected to the first control terminal A0 on the first-stage switch circuit T1, the third control terminal P2 of the control unit MCU is connected to the first control terminal A1 on the first-stage switch circuit T1, the third control terminal P3 of the control unit MCU is connected to the first control terminal A0 on the first-stage switch circuit T2, the third control terminal P4 of the control unit MCU is connected to the first control terminal A1 on the first-stage switch circuit T2, the third control terminal P5 of the control unit MCU is connected to the first control terminal A0 on the first-stage switch circuit T3, the third control terminal P6 of the control unit MCU is connected to the first control terminal A1 on the first-stage switch circuit T3, the third control terminal P7 of the control unit MCU is connected to the first control terminal A0 on the first-stage switch circuit T4, and the third control terminal P8 of the control unit MCU is connected to the first control terminal A1 on the first-stage switch circuit T4;

[0071] The fourth control terminal P9 of the control unit MCU is respectively connected to the second control terminal A0 on the second-stage switch circuit T5, the second control terminal A0 on the second-stage switch circuit T6, the second control terminal A0 on the second-stage switch circuit T7, and the second control terminal A0 on the second-stage switch circuit T8. The fourth control terminal P10 of the control unit MCU is respectively connected to the second control terminal A1 on the second-stage switch circuit T5, the second control terminal A1 on the second-stage switch circuit T6, the second control terminal A1 on the second-stage switch circuit T7, and the second control terminal A1 on the second-stage switch circuit T8. The fourth control terminal P11 of the control unit MCU is respectively connected to the second control terminal A2 on the second-stage switch circuit T5, the second control terminal A2 on the second-stage switch circuit T6, the second control terminal A2 on the second-stage switch circuit T7, and the second control terminal A2 on the second-stage switch circuit T8. The fourth control terminal P12 of the control unit MCU is respectively connected to the second control terminal A3 on the second-stage switch circuit T5, the second control terminal A3 on the second-stage switch circuit T6, the second control terminal A3 on the second-stage switch circuit T7, and the second control terminal A3 on the second-stage switch circuit T8;

[0072] Through the above wiring method, the third control terminal can be used to independently control each first control terminal, thereby realizing any sorting of the signals of the input unit and outputting them. The fourth control terminal is used to commonly control each second control terminal, thereby realizing the selective output of the sorted signals.

[0073] Specifically, the number of second output terminals on each secondary switch circuit and the number of output units are both 16. Among them, each output unit is represented by OUT1 to OU16 in Figure 1 respectively, and the four ports in each output unit are represented by port 1, port 2, port 3, and port 4 of the corresponding output unit.

[0074] By using 16 output units, the maximized utilization of the terminals can be achieved.

[0075] Specifically, the first output terminals on each 4-channel analog switch circuit are respectively the first output terminal S1, the first output terminal S2, the first output terminal S3, and the first output terminal S4. Among them,

[0076] the second input terminal D of the first 16-channel analog switch circuit is connected to each first output terminal S1, the second input terminal D of the second 16-channel analog switch circuit is connected to each first output terminal S2, the second input terminal D of the third 16-channel analog switch circuit is connected to each first output terminal S3, and the second input terminal D of the fourth 16-channel analog switch circuit is connected to each first output terminal S4.

[0077] After the above connections, at this time, under the control signal of the control unit, the first 4-channel analog switch circuit can output a signal at its first output terminal, and this signal can be transmitted to one of the 16-channel analog switch circuits. At the same time, under the control signal of the control unit, the second 4-channel analog switch circuit can output a signal at its first output terminal, and this signal can be transmitted to another 16-channel analog switch circuit, until the last signal is transmitted to the last 16-channel analog switch circuit. Thus, after the four input signals are sorted by the 4-channel switch analog circuit, they are sequentially output to different 16-channel analog switch circuits to facilitate the output of the above 16-channel analog switch circuits to a preset output unit.

[0078] Specifically, the control unit is an MCU chip.

[0079] By using the MCU chip, the output terminals of the primary switch circuit and the secondary switch circuit can be controlled quickly and accurately.

[0080] Specifically, the second output terminals S1 of the second-level switch circuits T5, T6, T7, and T8 are successively connected to the 1-port, 2-port, 3-port, and 4-port of the first output unit OUT1; the second output terminals S2 of the second-level switch circuits T5, T6, T7, and T8 are successively connected to the 1-port, 2-port, 3-port, and 4-port of the output unit OUT2; the second output terminals S3 of the second-level switch circuits T5, T6, T7, and T8 are successively connected to the 1-port, 2-port, 3-port, and 4-port of the output unit OUT3..... until the second output terminals S16 of the second-level switch circuits T5, T6, T7, and T8 are successively connected to the 1-port, 2-port, 3-port, and 4-port of the output unit OUT16;

[0081] After adopting the above solution, please combine it here Figure 1 , Figure 3 and Figure 4 as shown;

[0082] The third control terminals P1 to P8 of the control unit MCU are used to send independent control signals to each first-level switch circuit respectively, so as to control one of the first output terminals in each first-level switch circuit to output a target signal, so as to Figure 3 One of the embodiments shown in is used for illustrative explanation. When both the third control terminal P1 and the third control terminal P2 output the control signal 1, the first output terminal S4 of the first-level switch circuit T1 outputs the target signal. Since the first input terminal D of the first-level switch circuit T1 is connected to the 1-port of the input unit IN, the above target signal is the information of the 1-port of the input unit IN;

[0083] Similarly, when the third control terminal P3 outputs the control signal 1 and the third control port P4 outputs the control signal 0, the first output terminal S3 of the first-level switch circuit T2 outputs the target signal. Since the first input terminal D of the first-level switch circuit T2 is connected to the 2-port of the input unit IN, the above target signal is the information of the 2-port of the input unit IN;

[0084] When the third control terminal P5 outputs the control signal 0 and the third control port P4 outputs the control signal 0, the first output terminal S1 of the first-level switch circuit T3 outputs the target signal. Since the first input terminal D of the first-level switch circuit T3 is connected to the 3-port of the input unit IN, the above target signal is the information of the 3-port of the input unit IN;

[0085] When the third control terminal P7 outputs a control signal of 0 and the third control port P8 outputs a control signal of 1, the first output terminal S2 of the first-stage switch circuit T4 outputs a target signal. Since the first input terminal D of the first-stage switch circuit T4 is connected to the 4-port of the input unit IN, the above-mentioned target signal is the information of the 4-port of the input unit IN;

[0086] At this time, the second-stage switch circuits T5, T6, T7, and T8 sequentially receive the information of the 4-port, 3-port, 1-port, and 2-port of the output unit, thereby completing the reordering of the target information;

[0087] At this time, the fourth control terminals P9 to P11 of the control unit MCU are used to respectively send a common control signal to each second-stage switch circuit to control one of the second output terminals in each second-stage switch circuit to output a target signal, so as to Figure 4 Taking one of the embodiments shown as an example for illustration, when the fourth control terminal P9, the fourth control terminal P10, the fourth control port P11, and the fourth control port P12 all output a control signal of 1, the second output terminals S16 of each second-stage switch circuit output a target signal;

[0088] At this time, the 1-port of the output unit OUT16 receives the information of the 4-port of the input unit IN, the 2-port of the output unit OUT16 receives the information of the 3-port of the input unit IN, the 3-port of the output unit OU16 receives the information of the 1-port of the input unit IN, and the 4-port of the output unit OUT16 receives the information of the 2-port of the input unit IN;

[0089] Obviously, through the above method, the sorting of the multi-channel information of the input unit and the selection of the output unit can be conveniently, reliably, and quickly realized.

[0090] One embodiment of the present invention also provides a surface sheet resistance measurement system for a solar cell silicon wafer, including a multi-channel selection circuit as described above.

[0091] One embodiment of the present invention also provides a surface sheet resistance measuring instrument for a solar cell silicon wafer, including a multi-channel selection circuit as described above.

[0092] One embodiment of the present invention also provides a solar cell system, characterized in that it includes a surface sheet resistance measurement system for a solar cell silicon wafer as described above.

[0093] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A multiplex selection circuit, characterized in that: include: An input unit, a primary switch circuit, a secondary switch circuit, a control unit and an output unit, wherein the primary switch circuit, the secondary switch circuit and the output unit are multiple, each of the primary switch circuits has a first input terminal, multiple first output terminals and a first control terminal, each of the secondary switch circuits has a second input terminal, multiple second output terminals and a second control terminal, and each of the output units has multiple third input terminals; For each of the first-level switch circuits, the first input terminal is connected to the input unit; For each of the secondary switch circuits, the second input terminal is connected to the first output terminal of each of the primary switches, wherein each of the first output terminals of each of the primary switches corresponds to a different second input terminal; For each of the output units, each of the third input terminals is connected to the second output terminal of one of the secondary switches, wherein each of the third input terminals corresponds to a non-repeated second output terminal on different secondary switches; The control unit is connected to each of the first control terminals and each of the second control terminals.

2. A multiplex selection circuit according to claim 1, characterized in that: The number of the primary switch circuit, the secondary switch circuit, the first output terminal on each primary switch circuit, the second input terminal on each secondary switch circuit, and the third input terminal on each output unit is the same as the number of terminals of the input unit.

3. A multi-way selection circuit according to claim 2, characterized in that: The output unit has four terminals, the primary switch circuit is a 4-way analog switch circuit, and the secondary switch circuit is a 16-way analog switch circuit.

4. A multiplex selection circuit according to claim 3, characterized in that: The control unit includes 8 third control terminals and 4 fourth control terminals; Each of the 4-way analog switch circuits has 2 first control terminals, and the 8 third control terminals are respectively connected to a non-repeated first control terminal; Each of the 16-way analog switch circuits has four second control terminals, and each of the fourth control terminals is connected to a non-repeated second control terminal on each of the 16-way analog switch circuits.

5. A multiplex selection circuit according to claim 4, characterized in that: The number of the second output terminals on each of the secondary switch circuits and the number of the output units are both 16.

6. A multiplex selection circuit according to claim 5, characterized in that: The first output terminals of the four analog switch circuits are respectively a first output terminal S1, a first output terminal S2, a first output terminal S3 and a first output terminal S4, wherein: The second input end of the first 16-way analog switch circuit is connected to each of the first output ends S1, the second input end of the second 16-way analog switch circuit is connected to each of the first output ends S2, the second input end of the third 16-way analog switch circuit is connected to each of the first output ends S3, and the second input end of the fourth 16-way analog switch circuit is connected to each of the first output ends S4.

7. A multiplex selection circuit according to claim 1, characterized in that: The control unit is an MCU chip.

8. A solar cell silicon wafer surface resistance measurement system, characterized in that: It comprises a multiple-way selection circuit as claimed in any one of claims 1 to 7.

9. A solar cell silicon wafer surface resistance measuring instrument, characterized in that: It comprises a multiple-way selection circuit as claimed in any one of claims 1 to 7.

10. A solar cell system, characterized in that: It comprises a solar cell silicon wafer surface resistance measurement system as described in claim 8.

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