Solar cell and photovoltaic module

Abstract

The utility model relates to the technical field of solar cells, and discloses a solar cell and a photovoltaic module. The solar cell comprises: a silicon substrate having a first region and a second region on the rear surface thereof; the first semiconductor layers and the second semiconductor layers are alternately distributed and arranged on the rear surface at intervals and correspond to the first area and the second area; a plurality of non-pyramid microstructures are arranged on the rear surface of the silicon substrate and comprise first microstructures in a first area and second microstructures in a second area, the one-dimensional size a1 of each first microstructure is 2.5-30 microns, and the one-dimensional size a2 of each second microstructure is 4-50 microns; the longest one-dimensional size of the first microstructure is a1max, and the shortest one-dimensional size of the first microstructure is a1min; the longest one-dimensional size of the second microstructure is a2max, the shortest one-dimensional size of the second microstructure is a2min, and the ratio of (a2max + a2min) / 2 to (a1max + a1min) / 2 is 1-1.7.

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and particularly to a solar cell and a photovoltaic module. Background Art

[0002] When the front surface of a silicon-based solar cell is designed without electrode grid lines, this front-surface unobstructed structure eliminates the shading loss caused by the grid line electrodes and realizes the maximum utilization of incident photons. However, at the same time, when both the positive and negative electrode grid lines of this solar cell are transferred to the back surface of the silicon substrate, it will have an adverse effect on the contact performance between the semiconductor layer and the metal electrode located on the back surface of the silicon substrate, which is not conducive to improving the photoelectric conversion efficiency of the solar cell. Summary of the Utility Model

[0003] The purpose of the embodiments of this application is to provide a solar cell and a photovoltaic module, and this solar cell has a lower series resistance, a higher short-circuit current, and a higher photoelectric conversion efficiency.

[0004] In the first aspect, the embodiments of this application provide a solar cell, and the solar cell includes:

[0005] A silicon substrate, the silicon substrate has a front surface and a back surface arranged opposite to each other, the back surface has a first region and a second region, and the silicon substrate has a first conductivity type;

[0006] A first semiconductor layer and a second semiconductor layer alternately distributed on the back surface, the first semiconductor layer and the second semiconductor layer are separated by an isolation region; wherein, the first semiconductor layer corresponds to the position of the first region, and the first semiconductor layer has a second conductivity type; the second semiconductor layer corresponds to the position of the second region, and the second semiconductor layer has the first conductivity type, and the first conductivity type is opposite to the second conductivity type;

[0007] The back surface of the silicon substrate has a plurality of non-pyramid microstructures, the non-pyramid microstructures are recessed or protruded relative to the back surface, and the horizontal projection shape of the non-pyramid microstructures on the back surface is a polygon;

[0008] The non-pyramid microstructures include a first microstructure located in the first region and a second microstructure located in the second region, the one-dimensional size a1 of the first microstructure is 2.5 μm to 30 μm, and the one-dimensional size a2 of the second microstructure is 4 μm to 50 μm; the longest one-dimensional size of the first microstructure is a 1max , the shortest one-dimensional size is a 1min ; the longest one-dimensional size of the second microstructure is a 2max , the shortest one-dimensional size is a 2min , (a 2max+a 2min ) / 2 and (a 1max +a 1min ) / 2 ranges from 1 to 1.7;

[0009] A first electrode, in ohmic contact with the first semiconductor layer;

[0010] A second electrode, in ohmic contact with the second semiconductor layer.

[0011] Further, the area S1 of the first microstructure is 4 μm 2 to 625 μm 2 , and the area S2 of the second microstructure is 9 μm 2 to 1225 μm 2 ;

[0012] The average value of the areas of a plurality of the first microstructures is The average value of the areas of a plurality of the second microstructures is

[0013] Further, the height l1 of the first microstructure is 300 nm to 1000 nm, and the height l2 of the second microstructure is 100 nm to 600 nm;

[0014] The average value of the heights of a plurality of the first microstructures is The average value of the heights of a plurality of the second microstructures is

[0015] Further, the first conductivity type and the second conductivity type are N-type and P-type, respectively.

[0016] Further, the solar cell further includes:

[0017] A first dielectric layer, disposed between the rear surface of the silicon substrate and the first semiconductor layer;

[0018] A second dielectric layer, disposed between the rear surface of the silicon substrate and the second semiconductor layer.

[0019] Further, the thickness of the first doped polysilicon layer is 220 nm to 380 nm; the thickness of the second doped polysilicon layer is 110 nm to 280 nm.

[0020] Further, a first pyramid structure is provided on the rear surface located in the isolation region.

[0021] Further, a second pyramid structure is provided on the front surface of the silicon substrate.

[0022] Further, in a direction away from the silicon substrate, a first functional layer is provided on the first semiconductor layer and the second semiconductor layer. The first electrode is in ohmic contact with the first semiconductor layer through the first functional layer, and the second electrode is in ohmic contact with the second semiconductor layer through the first functional layer; and / or,

[0023] A second functional layer is provided on the front surface of the silicon substrate.

[0024] In a second aspect, an embodiment of the present application provides a photovoltaic module, and the photovoltaic module includes the solar cell as described in the first aspect.

[0025] Compared with the prior art, the beneficial effects of the embodiments of the present application are as follows:

[0026] In the embodiments of the present application, by disposing both the first electrode and the second electrode on the rear surface of the silicon substrate, and simultaneously controlling the structure and size of the non-pyramid-shaped first microstructures and second microstructures on the rear surface of the silicon substrate, it is possible to maximize the utilization of incident light by taking advantage of the unobstructed front surface of the silicon substrate, and at the same time improve the contact performance between the metal electrode and the semiconductor layer, reduce the series resistance, and improve the photoelectric conversion efficiency of the solar cell. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0028] Figure 1 is a schematic structural diagram of a solar cell provided by an embodiment of the present application;

[0029] Figure 2 is a schematic diagram for measuring the one-dimensional size of the first microstructures in the solar cell according to an embodiment of the present application;

[0030] Figure 3 is a scanning electron microscope image of the first microstructures from a first perspective provided by an embodiment of the present application;

[0031] Figure 4 is a scanning electron microscope image of the second microstructures from a first perspective provided by an embodiment of the present application;

[0032] Figure 5 is a scanning electron microscope image of the first microstructures from a second perspective provided by an embodiment of the present application;

[0033] Figure 6 is a scanning electron microscope image of the second microstructures from a second perspective provided by an embodiment of the present application.

[0034] Reference numerals:

[0035] 1. Silicon substrate; 101. First region; 102. Second region; 103. Isolation region; 11. First microstructure; 12. Second microstructure; 21. First semiconductor layer; 22. Second semiconductor layer; 31. First electrode; 32. Second electrode; 41. First dielectric layer; 42. Second dielectric layer; 51. First functional layer; 52. Second functional layer. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0037] In the present application, the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", and "longitudinal" is based on the orientation or positional relationship shown in the accompanying drawings. These terms are mainly used to better describe the present application and its embodiments, and are not used to limit that the indicated devices, elements, or components must have a specific orientation, or be constructed and operated in a specific orientation.

[0038] Moreover, in addition to being able to represent the orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the present application can be understood according to specific circumstances.

[0039] In addition, the terms "installed", "set", "provided with", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral structure; it may be a mechanical connection or an electrical connection; it may be directly connected, or indirectly connected through an intermediate medium, or there may be internal communication between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0040] In addition, the terms "first", "second", etc. are mainly used to distinguish different devices, elements, or components (the specific types and structures may be the same or different), and are not used to indicate or imply the relative importance and quantity of the indicated devices, elements, or components. Unless otherwise specified, the meaning of "a plurality" is two or more.

[0041] The technical solution provided by the present application will be further described below in conjunction with embodiments and the accompanying drawings.

[0042] Refer to Figure 1 , an embodiment of the present application provides a solar cell, including:

[0043] A silicon substrate 1, the silicon substrate 1 has a front surface and a back surface arranged opposite to each other, the back surface has a first region 101 and a second region 102, and the silicon substrate 1 has a first conductivity type;

[0044] A first semiconductor layer 21 and a second semiconductor layer 22 alternately distributed on the back surface, the first semiconductor layer 21 and the second semiconductor layer 22 are separated by an isolation region 103, the first semiconductor layer 21 corresponds to the position of the first region 101, and the first semiconductor layer 21 has a second conductivity type, the second semiconductor layer 22 corresponds to the position of the second region 102, and the second semiconductor layer 22 has a first conductivity type, and the first conductivity type is opposite to the second conductivity type;

[0045] The back surface of the silicon substrate 1 has a plurality of non-pyramid microstructures, the non-pyramid microstructures are recessed or protruded relative to the back surface, and the horizontal projection shape of the non-pyramid microstructures on the back surface is a polygon;

[0046] The non-pyramid microstructures include a first microstructure 11 located in the first region 101 and a second microstructure 12 located in the second region 102. The one-dimensional size a1 of the first microstructure 11 is 2.5 μm to 30 μm, and the one-dimensional size a2 of the second microstructure 12 is 4 μm to 50 μm; the longest one-dimensional size of the first microstructure 11 is a 1max , the shortest one-dimensional size is a 1min ; the longest one-dimensional size of the second microstructure 12 is a 2max , the shortest one-dimensional size is a 2min , (a 2max + a 2min ) / 2 and (a 1max + a 1min ) / 2 have a ratio range of 1 to 1.7;

[0047] A first electrode 31, in ohmic contact with the first semiconductor layer 21;

[0048] A second electrode 32, in ohmic contact with the second semiconductor layer 22.

[0049] In the embodiment of the present application, by disposing both the first electrode 31 and the second electrode 32 on the rear surface of the silicon substrate 1, and simultaneously controlling the structure and size settings of the non-pyramid-shaped first microstructure 11 and the second microstructure 12 on the rear surface of the silicon substrate 1, it is possible to maximize the utilization of incident light by taking advantage of the unobstructed front surface of the silicon substrate 1, and at the same time improve the contact performance between the metal electrode and the semiconductor layer, reduce the series resistance, and improve the photoelectric conversion efficiency of the solar cell.

[0050] The series resistance of a solar cell is mainly composed of the electrode lateral resistance, the contact resistance between the metal and the semiconductor, the base region resistance, and the emitter lateral resistance. It can be seen that the contact resistance between the semiconductor layer and the metal electrode in different conductivity type regions and the lateral resistance of the emitter region will affect the resistance of the solar cell, and the morphological differences of the non-pyramid-shaped first microstructure 11 and the second microstructure 12 will also affect the base region resistance, thereby comprehensively affecting the series resistance of the solar cell. The applicant has found that when the average one-dimensional size of the first microstructure 11 and the second microstructure 12 and the overall size ratio of the two satisfy a certain range, that is, the ratio range of the average value of the longest diagonal to the shortest diagonal of the second microstructure 12 to the average value of the longest diagonal to the shortest diagonal of the first microstructure 11 is 1 to 1.7, the overall series resistance of the solar cell is smaller, the short-circuit current is increased, and the conversion efficiency of the solar cell is improved.

[0051] Thus, it can be seen that the solar cell of the embodiment of the present application can not only give full play to the structural advantage of the front surface of the silicon substrate 1 without metal electrodes, but also improve the contact performance between the semiconductor layer on the rear surface of the silicon substrate 1 and the metal electrode, and well solve the adverse effects on the series resistance and the like caused by the metal electrodes being all disposed on the rear surface of the silicon substrate 1.

[0052] It can be understood that the non-pyramid-shaped microstructure refers to a structure whose shape is no longer a complete pyramid shape. For example, the rear surface of the silicon substrate 1 is first textured to obtain a pyramid structure, and then operations such as polishing are performed on the pyramid structure. After etching off most of the tips and the body of the pyramid structure, the remaining pyramid bases are the non-pyramid-shaped microstructures. In this case, the non-pyramid-shaped microstructures protrude from the rear surface of the silicon substrate 1. In other cases, after etching off the entire pyramid structure, it is easier to form non-pyramid-shaped microstructures that are concave with respect to the rear surface of the silicon substrate 1.

[0053] In addition, in the non-pyramid-shaped microstructure, the longest one-dimensional size a of the first microstructure 11 1max refers to the two farthest points of the first microstructure 11 along the first direction, and the straight-line distance between these two points is a 1max . The shortest one-dimensional size a of the first microstructure 11 1minIt means that the first microstructure 11 has two closest points in the second direction, and the second direction is generally perpendicular to the first direction, and the linear distance between the two closest points is a 1min For example Figure 2 As shown, when the horizontal projection shape of the first microstructure 11 on the rear surface of the silicon substrate 1 is a rhombus, a 1max refers to the length of the long diagonal of the rhombus, and a 1min refers to the length of the short diagonal of the rhombus. The one-dimensional dimension a1 is the diagonal length of the rhombus, and a1 is between a1min and a1max. For the second microstructure 12, the definitions of a2, a 2max and a 2min are the same as those of the first microstructure 11 and will not be elaborated here.

[0054] Furthermore, the area S1 of the first microstructure 11 is 4 μm 2 to 625 μm 2 , and the area S2 of the second microstructure 12 is 9 μm 2 to 1225 μm 2 ; the average value of the areas of a number of first microstructures 11 is the average value of the areas of a number of second microstructures 12 is

[0055] To a certain extent, the area of the non-pyramid microstructure can reflect the contact area size that can be provided for the metal electrode paste. In the embodiments of the present application, the areas and their ratios of the first microstructure 11 and the second microstructure 12 are controlled within the above ranges. The area ratio of the first microstructure 11 to the second microstructure 12 is relatively close and the area of the second microstructure 12 is relatively large. This is beneficial to optimizing the contact area between the metal electrode paste and the semiconductor layer, enabling the metal electrode to be more stably formed on the semiconductor layer, thereby facilitating the reduction of the overall series resistance and improving the photoelectric conversion efficiency of the solar cell. The average value of the area of the non-pyramid microstructure is measured by the following method: Use a scanning electron microscope to test the first microstructure 11 and the second microstructure 12. Randomly select 5 different regions on the four sides and in the middle of the back of the wafer to measure the first microstructure 11 and the second microstructure 12. Test from the surface direction of the battery (that is, from the angle looking down on the surface of the solar cell). The area of this field of view is approximately 200 μm × 125 μm. Measure the largest and smallest non-pyramid microstructure areas within this region and take the average value. It should be noted that when testing the first microstructure 11 and the second microstructure 12, the metal electrodes (i.e., the first electrode 31 and the second electrode 32), the passivation layer, and the semiconductor layer (i.e., the first semiconductor layer 21 and the second semiconductor layer 22) have been removed by chemical etching method, and only the silicon substrate 1 remains. Therefore, the first microstructure 11 and the second microstructure 12 on the rear surface of the silicon substrate 1 can be observed and measured.

[0056] Further, the height l1 of the first microstructure 11 is 300 nm to 1000 nm, and the height l2 of the second microstructure 12 is 100 nm to 600 nm; the average value of the heights of a plurality of first microstructures 11 is The average value of the heights of a plurality of second microstructures 12 is

[0057] To a certain extent, the height of the non - pyramid - shaped microstructure can reflect the flatness of the contact interface with the non - pyramid - shaped microstructure. The higher the non - pyramid - shaped microstructure, the lower the flatness of the contact interface with the non - pyramid - shaped microstructure. Lower flatness will lead to higher non - uniformity of the contact interface and an increase in dangling bonds. The height of the first microstructure 11 can be greater than or equal to the height of the second microstructure 12, that is, the flatness of the first region 101 is less than or equal to the flatness of the second region 102. In the embodiments of the present application, by controlling the flatness of the contact interface, good contact between the metal electrode and the silicon wafer can be achieved while reducing the number of dangling bonds, which helps to reduce the recombination of electron - hole pairs at the dangling bonds. The average value of the height of the non - pyramid - shaped microstructure is measured by the following method: Use a scanning electron microscope to measure the height of the non - pyramid - shaped microstructures in the first region 101 and the second region 102. Randomly select 5 different regions on the four sides and the middle of the back of the wafer to measure the first microstructure 11 and the second microstructure 12. Measure through the battery cross - section direction, measure the maximum and minimum heights of the non - pyramid - shaped microstructures in this region, and take the average value. It should be noted that when measuring the first microstructure 11 and the second microstructure 12, the metal electrodes (i.e., the first electrode 31 and the second electrode 32), the passivation layer, and the semiconductor layers (i.e., the first semiconductor layer 21 and the second semiconductor layer 22) have been removed by chemical etching method, and only the silicon substrate 1 remains. Therefore, the first microstructure 11 and the second microstructure 12 on the back surface of the silicon substrate 1 can be observed and measured.

[0058] Further, the first conduction type is N - type, and the second conduction type is P - type. That is to say, the silicon substrate 1 is an N - type silicon substrate 1, the first semiconductor layer 21 is a P - type semiconductor layer, which is used to form a PN junction with the silicon substrate 1. For example, the first semiconductor layer 21 is a boron - doped crystalline silicon layer, and the second semiconductor layer 22 is an N - type semiconductor layer. For example, the second semiconductor layer 22 is a phosphorus - doped semiconductor layer.

[0059] In the first region 101 on the back surface of the silicon substrate 1 corresponding to the P - type semiconductor layer, the first microstructure 11 with the above - mentioned structural characteristics is provided, which is beneficial to reducing the recombination of the first electrode 31 and the N - type silicon substrate 1 and reducing the emitter contact resistance. In the second region 102 on the back surface of the silicon substrate 1 corresponding to the N - type semiconductor layer, the second microstructure 12 with the above - mentioned structural characteristics is provided, which is beneficial to improving the passivation ability of the N - type semiconductor layer and reducing the carrier recombination probability.

[0060] Further, the first semiconductor layer 21 is a first doped polysilicon layer doped with a P-type conductive element, and the second semiconductor layer 22 is a second doped polysilicon layer doped with an N-type conductive element. The solar cell further includes: a first dielectric layer 41 disposed between the rear surface of the silicon substrate 1 and the first doped polysilicon layer; and a second dielectric layer 42 disposed between the rear surface of the silicon substrate 1 and the second doped polysilicon layer.

[0061] That is to say, in the above embodiment, a passivation contact structure is provided on the first microstructure 11 and the second microstructure 12. The presence of the passivation contact structure avoids the direct contact between the electrode and the silicon wafer, can effectively reduce the carrier recombination in the metal contact region, and can significantly improve the open voltage and efficiency of the battery.

[0062] The material of the dielectric layer may include various dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the dielectric layer may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation performance, can minimize the recombination loss of minority carriers on the surface of the semiconductor substrate, and is a film with excellent durability for subsequent high-temperature processes. The dielectric layer, as a barrier for electrons and holes, can combine with the doped polysilicon layer to prevent the passage of minority carriers. The dielectric layer can also have the function of a pinhole channel, enabling the carriers in the solar cell to move freely, generating selective passage for majority carriers through heavily doped polysilicon, which is beneficial to reducing the recombination loss of minority carriers. In addition, the dielectric layer can be used as a diffusion barrier to prevent the dopant in the doped polysilicon layer from diffusing into the semiconductor substrate.

[0063] Further, the thickness of the first doped polysilicon layer is 220 nm to 380 nm; the thickness of the second doped polysilicon layer is 110 nm to 280 nm. It can be seen that the thickness of the first doped polysilicon layer is greater than that of the second doped polysilicon layer. This is because the P-type region is mainly responsible for collecting hole carriers, and a thicker P-type region can collect hole carriers more effectively while suppressing the recombination of hole carriers at the interface. The electrons in the N-type region are minority carriers, and their diffusion length is relatively short. A thinner N-type region can meet the transmission requirements of electrons, and a thinner N-type region can reduce the recombination of carriers in the N-type region and improve the battery efficiency.

[0064] Further, in a direction away from the silicon substrate 1, a first functional layer 51 is provided on the first semiconductor layer 21 and the second semiconductor layer 22. The first electrode 31 is in ohmic contact with the first semiconductor layer 21 through the first functional layer 51, and the second electrode 32 is in ohmic contact with the second semiconductor layer 22 through the first functional layer 51. A second functional layer 52 is provided on the front surface of the silicon substrate 1. Among them, the first functional layer 51 and the second functional layer 52 can be a composite layer of one or more layers of an alumina layer, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

[0065] Further, a first pyramid structure is provided on the rear surface of the silicon substrate 1 in the isolation region 103. Providing the first pyramid structure in the isolation region 103 helps to increase the absorption of solar energy by the battery and enhance the light trapping effect, thereby improving the photoelectric conversion efficiency of the battery.

[0066] Further, a second pyramid structure is provided on the front surface of the silicon substrate 1. This pyramid structure can further improve the absorption and utilization efficiency of light by the solar cell, thereby improving the electrical performance of the solar cell.

[0067] In a second aspect, an embodiment of the present application provides a photovoltaic module, and the photovoltaic module includes the solar cell as in the first aspect.

[0068] Embodiment

[0069] This embodiment provides a solar cell, including:

[0070] An N-type silicon substrate having a front surface and a rear surface disposed opposite to each other, and the rear surface has a first region and a second region;

[0071] In a direction away from the silicon substrate, a first dielectric layer, a first semiconductor layer, a first passivation layer, and a first electrode are sequentially provided on the rear surface of the silicon substrate. The first electrode is in ohmic contact with the first semiconductor layer after passing through the first passivation layer;

[0072] In a direction away from the silicon substrate, a second dielectric layer, a second semiconductor layer, a second passivation layer, and a second electrode are sequentially provided on the rear surface of the silicon substrate. The second electrode is in ohmic contact with the second semiconductor layer after passing through the second passivation layer; wherein, the first semiconductor layer and the second semiconductor layer are alternately distributed and separated by an isolation region. The first semiconductor layer is a boron-doped polysilicon layer corresponding to the position of the first region, and the second semiconductor layer is a phosphorus-doped polysilicon layer corresponding to the position of the second region;

[0073] On the rear surface of the silicon substrate, there are a number of non-pyramid microstructures, these non-pyramid microstructures protrude relative to the rear surface, and the horizontal projection shape of the non-pyramid microstructures on the rear surface is a polygon;

[0074] The non-pyramid microstructures include a first microstructure located in a first region and a second microstructure located in a second region. The one-dimensional size a1 of the first microstructure is 2.5 μm to 30 μm, and the one-dimensional size a2 of the second microstructure is 4 μm to 50 μm; the longest one-dimensional size of the first microstructure is a 1max , and the shortest one-dimensional size is a 1min ; the longest one-dimensional size of the non-pyramid substructure in the second region is a 2max , and the shortest one-dimensional size is a 2min , (a 2max + a 2min ) / 2 and (a 1max + a 1min ) / 2 have a ratio range of 1 to 1.7;

[0075] The area S1 of the first microstructure is 4 μm 2 to 625 μm 2 , and the area S2 of the second microstructure is 9 μm 2 to 1225 μm 2 ;

[0076] The average value of the areas of a number of first microstructures is The average value of the areas of a number of second microstructures is

[0077] The height l1 of the first microstructure is 300 nm to 1000 nm, and the height l2 of the second microstructure is 100 nm to 600 nm;

[0078] The average value of the heights of a number of first microstructures is The average value of the heights of a number of second microstructures is

[0079] See Figures 3 to 6 , which is the scanning electron microscope image of this embodiment. Among them, Figure 3 and Figure 4 are the scanning electron microscope images from the top view of the surface of the solar cell as the first perspective. At point A in Figure 3 and point B in Figure 4 are the first microstructure and the second microstructure respectively. Figure 5 and Figure 6 are the scanning electron microscope images from the side view of the solar cell as the second perspective. At point C in Figure 5 and point D in Figure 6 show the height of the first microstructure and the height of the second microstructure respectively.

[0080] The solar cells of the above embodiments were tested for electrical performance. A halm test and sorting device was used to test the performance in aspects such as open-circuit voltage, short-circuit current, and fill factor. The halm machine is a device that simulates sunlight, and is equipped with an electronic load, data acquisition, and calculation devices for testing the electrical performance of the solar cells. The results are shown in Table 1.

[0081] Table 1 Performance test results of solar cells

[0082]

[0083] The above has introduced in detail a solar cell and a photovoltaic module disclosed in the embodiments of the present application. Specific examples are used herein to elaborate on the principles and implementation manners of the embodiments of the present application. The description of the above embodiments is only used to help understand the technical solutions and their core ideas of the embodiments of the present application; at the same time, for those of ordinary skill in the art, according to the ideas of the embodiments of the present application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation on the embodiments of the present application.

Claims

1. A solar cell, characterized in that, The solar cell includes: a silicon substrate having a front surface and a rear surface disposed opposite to each other, the rear surface having a first region and a second region, and the silicon substrate having a first conductivity type; a first semiconductor layer and a second semiconductor layer alternately distributed on the rear surface, the first semiconductor layer and the second semiconductor layer being separated by an isolation region, the first semiconductor layer corresponding to the position of the first region and having a second conductivity type, the second semiconductor layer corresponding to the position of the second region and having the first conductivity type, the first conductivity type being opposite to the second conductivity type; the rear surface of the silicon substrate having a plurality of non-pyramid microstructures, the non-pyramid microstructures being concave or convex with respect to the rear surface, and the horizontal projection shape of the non-pyramid microstructures on the rear surface being a polygon; The non-pyramid microstructures include a first microstructure located in the first region and a second microstructure located in the second region. The one-dimensional size a1 of the first microstructure is 2.5 μm to 30 μm, and the one-dimensional size a2 of the second microstructure is 4 μm to 50 μm; the longest one-dimensional size of the first microstructure is a 1max , and the shortest one-dimensional size is a 1min ; the longest one-dimensional size of the second microstructure is a 2max , and the shortest one-dimensional size is a 2min , (a 2max + a 2min ) / 2 and (a 1max + a 1min ) / 2 have a ratio range of 1 to 1.7; a first electrode in ohmic contact with the first semiconductor layer; a second electrode in ohmic contact with the second semiconductor layer.

2. The solar cell according to claim 1, characterized in that, The area S1 of the first microstructure is 4 μm 2 ~625 μm 2 and the area S2 of the second microstructure is 9 μm 2 ~1225 μm 2 ; The average value of the areas of a plurality of the first microstructures is S1, the average value of the areas of a plurality of the second microstructures is S2, and 1 ≤ S2 / S1 < 2.

3. The solar cell according to claim 1, characterized in that, The height l1 of the first microstructure is 300 nm to 1000 nm, and the height l2 of the second microstructure is 100 nm to 600 nm; The average value of the heights of a plurality of the first microstructures is l1, the average value of the heights of a plurality of the second microstructures is l2, and 1 ≤ l1 / l2 < 1.

9.

4. The solar cell according to claim 1, wherein, The first conductivity type and the second conductivity type are N-type and P-type, respectively.

5. The solar cell according to any one of claims 1 to 4, characterized in that, The solar cell further includes: a first dielectric layer disposed between the rear surface of the silicon substrate and the first semiconductor layer; a second dielectric layer disposed between the rear surface of the silicon substrate and the second semiconductor layer.

6. The solar cell according to claim 5, wherein, The thickness of the first semiconductor layer is 220 nm to 380 nm; the thickness of the second semiconductor layer is 110 nm to 280 nm.

7. The solar cell according to any one of claims 1 to 4, characterized in that, In a direction away from the silicon substrate, a first functional layer is disposed on the first semiconductor layer and the second semiconductor layer, the first electrode passing through the first functional layer to be in ohmic contact with the first semiconductor layer, and the second electrode passing through the first functional layer to be in ohmic contact with the second semiconductor layer; and / or, a second functional layer is disposed on the front surface of the silicon substrate.

8. The solar cell according to any one of claims 1 to 4, characterized in that, A first pyramid structure is disposed on the rear surface of the isolation region.

9. The solar cell according to any one of claims 1 to 4, characterized in that, A second pyramid structure is disposed on the front surface of the silicon substrate.

10. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell according to any one of claims 1-9.

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