Integrated device based on 3D packaging

Abstract

The utility model relates to an integrated device based on 3D packaging, the device comprises an intermediate layer, at least one system-on-chip, at least one storage module and a packaging layer, each storage module comprises a plurality of storage modules stacked in sequence, and the adjacent storage modules are connected in a hybrid bonding mode. The system-on-chip is respectively fixed on the front surface of the interposer through the micro bumps, and is electrically connected with the bumps on the back surface of the interposer through the micro bumps and the silicon through holes in the interposer; the storage modules are stacked above the corresponding system-on-chip and are connected with the system-on-chip in a hybrid bonding manner; the packaging layer is located on the front face of the interposer and used for packaging the at least one system-on-chip and the at least one storage module. The size of the interposer can be reduced, the warping rate is reduced, the yield is improved, the power loss of the device is reduced, and the heat dissipation performance is good.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly relates to an integrated device based on 3D packaging. Background Art

[0002] A system-on-chip (SoC) is an integrated circuit (IC) that integrates multiple components of an electronic system onto a single chip. The SoC design aims to reduce design complexity, lower power consumption, reduce costs, and improve overall performance. In an integrated device integrating an SoC, a storage device needs to be set for the SoC. In related technologies, there are problems such as poor heat dissipation performance, high warpage curvature, and low yield rate in the packaging methods of the SoC and the storage device in the integrated device. Summary of the Utility Model

[0003] In view of this, the utility model provides an integrated device based on 3D packaging.

[0004] According to one aspect of the utility model, there is provided an integrated device based on 3D packaging, the device comprising: an interposer, at least one system-on-chip, at least one memory module, and a packaging layer, each memory module comprising a plurality of memory modules stacked in sequence, and adjacent memory modules being connected by hybrid bonding.

[0005] The system-on-chip is respectively fixed on the front of the interposer through microbumps, and realizes electrical connection with bumps on the back of the interposer through the microbumps and through-silicon vias in the interposer.

[0006] The memory module is stacked above the corresponding system-on-chip and realizes connection with the system-on-chip where it is located through hybrid bonding.

[0007] The packaging layer is located on the front of the interposer and is used to package the at least one system-on-chip and the at least one memory module.

[0008] In a possible implementation, the memory module further comprises an auxiliary module, and a plurality of sequentially stacked memory modules are stacked on the auxiliary module, and the auxiliary module is connected to the adjacent memory module by hybrid bonding.

[0009] In a possible implementation, the device further comprises a filling layer, and the filling layer covers the side surface of the memory module.

[0010] In a possible implementation, the device further comprises a reinforcement layer, and the reinforcement layer covers the exposed surface of the outermost memory module in the memory module, and the reinforcement layer also covers the filling layer.

[0011] In a possible implementation, the active surface of the system-on-chip faces the interposer.

[0012] In a possible implementation, the system-on-chips are arranged in an array on the front side of the interposer.

[0013] In a possible implementation, the material of the reinforcement layer includes silicon or silicon carbide; and / or, the material of the filling layer is silicon dioxide.

[0014] In a possible implementation, through-silicon vias are provided in some of the storage modules of the storage module, in the auxiliary module, and in the system-on-chip. Each storage module realizes electrical connection with the underlying system-on-chip through the corresponding through-silicon vias in the storage module where it is located and the electrical connection path formed by the hybrid bonding.

[0015] In a possible implementation, the system-on-chips are electrically connected through the wiring in the interposer.

[0016] The integrated device based on 3D packaging provided by the embodiments of the present invention includes an interposer, at least one system-on-chip, at least one storage module, and a packaging layer. Each storage module includes a plurality of storage modules stacked in sequence, and adjacent storage modules are connected by hybrid bonding. The system-on-chip is respectively fixed on the front side of the interposer through micro-bumps, and realizes electrical connection with the bumps on the back side of the interposer through the micro-bumps and the through-silicon vias in the interposer; the storage module is stacked above the corresponding system-on-chip and realizes connection with the system-on-chip where it is located by hybrid bonding; the packaging layer is located on the front side of the interposer and is used to package the at least one system-on-chip and the at least one storage module. It can reduce the size of the interposer, reduce the warpage rate, improve the yield, reduce the power consumption loss of the device, and have good heat dissipation performance.

[0017] According to the following detailed description of the exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present invention will become clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings included in the specification and constituting a part of the specification show the exemplary embodiments, features, and aspects of the present invention together with the specification, and are used to explain the principles of the present invention.

[0019] Figure 1 Shows a top view of an integrated device according to an embodiment of the present invention.

[0020] Figure 2 Shows a cross-sectional view of an integrated device according to an embodiment of the present invention.

[0021] Figure 3 A top view of an integrated device based on 3D packaging according to an embodiment of the present invention is shown.

[0022] Figures 4 - 6 A cross-sectional view of an integrated device based on 3D packaging according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0023] Various exemplary embodiments, features and aspects of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0024] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0025] In addition, in order to better illustrate the utility model, numerous specific details are given in the specific embodiments below. It should be understood by those skilled in the art that the utility model can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the utility model.

[0026] like Figure 1 , Figure 2 As shown, the integrated device includes 2 SoCs and 8 high bandwidth memories (HBM). Figure 2 It is for Figure 1 A cross-section at the midline AA, and Figure 1 Not shown Figure 2 The packaging layer in the HBM. Each HBM includes a base die located below and multiple DRAM chips (DRAM die) stacked on top of the base chip. The base chip and DRAM chip inside the HBM are connected through silicon via (TSV) technology and microbumps (microbumps, or μbump) technology, and to ensure the stability of the connection, it is necessary to fill the HBM with underfill glue. The HBM and SoC are respectively fixedly connected to the interposer using microbumps, and each HBM and SoC, and SoCs communicate with each other through the lines in the interposer. The HBM and SoC are connected to the outside through the silicon vias in the interposer and the pillars (such as copper Cu bumps) on the interposer. Figure 2As shown, the silicon (Si) substrates of the base chip, DRAM chip, and SoC face the interposer.

[0027] Although, Figure 1 、 Figure 2 the device shown can achieve 2.5D packaging with a relatively high-density stacked package, but there are the following defects:

[0028] The size of the SoC is limited by the maximum reticle size of 26 mm × 33 mm.

[0029] The area of the interposer is large. When the device has 2 SoCs and 8 HBMs, the size of the interposer in the device will be more than 3 times the maximum reticle size. This will lead to an increased warpage curvature of the entire interposer and a low yield.

[0030] When the device has 8 HBMs, the device has a high bandwidth of 8 × 1024 × 8 Gbps, and the power consumption between the HBM and the SoC and between chips will be very high.

[0031] The underfill glue added for stability due to the use of micro-bumps to achieve connection within the HBM will cause the heat dissipation performance of each HBM to deteriorate.

[0032] To further increase the stacking degree of the device to achieve 3D packaging of the device, the embodiments of the present utility model provide an integrated device based on 3D packaging, which can reduce the size of the interposer, reduce the warpage curvature, improve the yield, reduce the power consumption loss of the device, and have good heat dissipation performance.

[0033] As Figure 3 、 Figure 4 shown, the device includes: an interposer 13, at least one system-on-chip 11, at least one memory module 12, and a packaging layer 15. Among them, Figure 3 、 Figure 4 and as described below Figure 5 、 Figure 6 only two system-on-chips are schematically shown in the device shown. In fact, the number of system-on-chips in the device can be set as needed, and the present utility model does not limit this.

[0034] As Figure 3 、 Figure 4 shown, each memory module 12 includes a plurality of sequentially stacked memory modules 121, and adjacent memory modules 121 are connected by means of hybrid bonding Q1.

[0035] In this embodiment, each storage module 121 can be a storage component for data storage such as a DRAM chip, and the present utility model places no restrictions thereon. The storage module 12 formed by stacking multiple storage modules 121 can form a storage device such as HBM, and the present utility model places no restrictions thereon. Among them, the hybrid bonding technology is an advanced packaging technology that allows for very tight physical and electrical connections between different materials (such as silicon and silicon, or silicon and glass). This technology can be achieved at room temperature, and compared with traditional high-temperature bonding, it can reduce the thermal budget and the impact on chip performance. In the hybrid bonding technology, through the direct copper-to-copper connection method, the traditional bump connection is replaced, resulting in lower resistance and better electrical performance being introduced between the storage modules 121 in the storage module 12. Moreover, no underfill glue is required in the storage module 12, ensuring good heat dissipation performance of the storage module 12 and making the heat dissipation performance better.

[0036] In some embodiments, the number of storage modules 121 in different storage modules 12 can be the same or different, and the number of storage modules 121 in the storage module 12 can be set according to actual needs, and the present utility model places no restrictions thereon.

[0037] Such as Figure 3 、 Figure 4 As shown, the system-on-chip 11 is respectively fixed on the front side (Front Side or Active Side) of the interposer 13 through micro-bumps Q2, and electrical connection with the bumps 14 on the back side (Back Side or Passive Side) of the interposer 13 is achieved through the micro-bumps Q2 and the through-silicon vias Q3 in the interposer 13.

[0038] In this embodiment, the material of the bumps 14 can be a conductive metal such as copper Cu, so that the device can be fixedly installed on the PCB board through the bumps 14.

[0039] Such as Figure 3 、 Figure 4 As shown, the storage module 12 is stacked above the corresponding system-on-chip 11 and connected to the system-on-chip 11 where it is located through the hybrid bonding Q1 method.

[0040] In this embodiment, since the storage module 12 is stacked on the system-on-chip 11, in fact, as long as the size of each storage module 121 in the storage module 12 is less than or equal to the size of the system-on-chip 11, stacking can be achieved, which greatly expands the effective area of each storage module 121, far greater than Figure 1In the manner shown, the DRAM chip, and thus the storage capacity of the storage module 12 can be greatly improved, and the storage capacity can reach 160 GB. Moreover, since the effective area of the storage module 121 in the storage module 12 increases, in the case of the same storage capacity requirement (such as compared with Figure 2 the device shown), the thickness of the device will be significantly reduced, which can be reduced to less than 2 mm, and the overall size of the device will be reduced.

[0041] In addition, since the storage module 12 is stacked on the system-on-chip 11, the size requirement for the interposer 13 is reduced and can be reduced to about 2.1 times the maximum reticle size, achieving a significant reduction in the size of the interposer 13, which can reduce the warpage curvature of the interposer 13 and improve the yield of the interposer 13. Furthermore, the warpage curvature of the device can be reduced and the yield of the device can be improved.

[0042] Such as Figure 3 , Figure 4 shown, the encapsulation layer 15 is located on the front side of the interposer 13 and is used to encapsulate the at least one system-on-chip 11 and the at least one storage module 12.

[0043] In this embodiment, the encapsulation layer 15 encapsulates the system-on-chip 11 and the storage module 12, fixedly encapsulating the system-on-chip 11 and the storage module 12 on the interposer 13, further fixing the positions of the system-on-chip 11 and the storage module 12 in the device, and also providing functions such as support, protection, heat dissipation, and insulation for the device. In some embodiments, the encapsulation layer can be manufactured through processes such as Molding.

[0044] In a possible implementation manner, such as Figure 5 , Figure 6 shown, the device may further include a filling layer 122, and the filling layer 122 covers the side surface of the storage module 12. The material of the filling layer can be silicon dioxide SiO2, etc., and the present invention is not limited thereto. Among them, the filling layer 122 may include a plurality of filling structures, and each filling structure is used to cover the side surface of a storage module 12. The filling structure wraps and covers the storage module 12 in a "ring shape" so that each storage module 121 in the storage module 12 is isolated from the external environment.

[0045] In a possible implementation manner, such as Figure 5 , Figure 6As shown, the device may further include a reinforcement layer 123. The reinforcement layer 123 covers the exposed surface of the outermost memory module 121 in the memory module 12, and the reinforcement layer 123 also covers the filling layer 122. Wherein, the reinforcement layer 123 may include a plurality of reinforcement structures, and each reinforcement structure covers the top of a memory module 12, covers the exposed surface (i.e., the back surface) of the outermost memory module 121 below, and the filling layer 122, serving as the "lid" of the memory module 12, improving the heat dissipation performance of the memory module 12 and also improving the structural stability of the memory module 12. In some embodiments, the shape and area of the reinforcement structure may be the same as the shape and area of the underlying system-on-chip 11.

[0046] In some embodiments, the material of the reinforcement layer 123 may include silicon (Si) or silicon carbide (SiC), etc., and the present utility model is not limited thereto.

[0047] In a possible implementation manner, as Figure 6 shown, the memory module 12 may further include an auxiliary module 124. A plurality of memory modules 121 stacked in sequence are stacked on the auxiliary module 124, and the auxiliary module 124 is connected to the adjacent memory module 121 by means of hybrid bonding Q1. Wherein, the front surface of the auxiliary module 124 faces the memory module 121, and the back surface faces the system-on-chip 11. The auxiliary module 124 is used to assist the system-on-chip 11 to implement control over each memory module 121 in the memory module 12. For example, the auxiliary module 124 may be a base die, and the present utility model is not limited thereto.

[0048] In a possible implementation manner, as Figures 4 - 6 shown, the active surface of the system-on-chip 11 faces the interposer 13.

[0049] In a possible implementation manner, the system-on-chip 11 is arranged in an array on the front surface of the interposer 13. The arrangement of the array can be set according to the number of system-on-chips 11 in the device. For example, when there are two system-on-chips 11 in the device, the long sides of the two system-on-chips 11 can be placed adjacent to each other as Figure 3 shown to reduce the size of the device. In some embodiments, the arrangement of the system-on-chip 11 can also be set according to the installation space limitation of the device on the PCB to ensure that the device can be installed in the given PCB space, and the present utility model is not limited thereto.

[0050] In this embodiment, among some memory modules 121 of the memory module 12 (such as Figures 4 - 6Other memory modules 121 other than the outermost memory module 121 shown), through-silicon vias Q3 are provided in the auxiliary module 124 and in the system-on-chip 11. Each memory module 121 realizes electrical connection with the underlying system-on-chip 11 through the corresponding through-silicon vias Q1 in the memory module 12 where it is located and the electrical connection path formed by the hybrid bonding Q1. In this way, a vertical electrical connection is achieved between the memory module 121 and the system-on-chip 11. Compared with Figure 2 the manner shown, the power consumption loss is lower (as low as <0.1 pJ / b).

[0051] In this embodiment, the system-on-chips 11 are electrically connected through the wiring in the interposer 13.

[0052] It should be noted that although the above embodiments are used as examples to introduce the integrated device based on 3D packaging as above, those skilled in the art can understand that the present invention should not be limited thereto. In fact, users can flexibly set each part according to personal preferences and / or actual application scenarios as long as it conforms to the technical solution of the present invention.

[0053] The embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is also not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. An integrated device based on 3D packaging, characterized in that, The device includes: an interposer, at least one system-on-chip, at least one memory module, and a packaging layer. Each memory module includes a plurality of memory modules stacked in sequence, and adjacent memory modules are connected by hybrid bonding. The system-on-chip is respectively fixed on the front of the interposer through micro-bumps, and realizes electrical connection with the bumps on the back of the interposer through the micro-bumps and through-silicon vias in the interposer. The memory module is stacked above the corresponding system-on-chip and is connected to the system-on-chip where it is located by hybrid bonding. The packaging layer is located on the front of the interposer and is used to package the at least one system-on-chip and the at least one memory module.

2. The device according to claim 1, characterized in that The memory module further includes an auxiliary module. A plurality of memory modules stacked in sequence are stacked on the auxiliary module, and the auxiliary module is connected to the adjacent memory modules by hybrid bonding.

3. The device according to claim 1, characterized in that, The device further includes a filling layer, and the filling layer covers the side surface of the memory module.

4. The device according to claim 3, characterized in that, The device further includes a reinforcement layer. The reinforcement layer covers the exposed surface of the outermost memory module in the memory module, and the reinforcement layer also covers the filling layer.

5. The device according to claim 1, characterized in that The active surface of the system-on-chip faces the interposer.

6. The device according to claim 1, characterized in that, The system-on-chips are arranged in an array on the front of the interposer.

7. The device according to claim 4, characterized in that The material of the reinforcement layer includes silicon or silicon carbide; and / or, the material of the filling layer is silicon dioxide.

8. The device according to claim 2, characterized in that Through-silicon vias are provided in some memory modules of the memory module, in the auxiliary module, and in the system-on-chip. Each memory module realizes electrical connection with the system-on-chip below through the corresponding through-silicon vias in the memory module where it is located and the electrical connection path formed by the hybrid bonding.

9. The device according to claim 1, characterized in that, The system-on-chips are electrically connected through the wiring in the interposer.

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