Heterogeneous computing system, server and data center

Abstract

The utility model belongs to the technical field of server architecture design, and particularly provides a heterogeneous computing system, a server and a data center, the system comprises a switching unit and at least two types of computing units, the number of the computing units of each type is a plurality, all the computing units are standard high-speed serial computer expansion bus board cards, and the switching unit is provided with a plurality of high-speed serial computer expansion bus slots; and all the computing units are respectively connected with the high-speed serial computer expansion bus slots on the switching unit. The computing unit is designed in the form of a PCIe card, the appearance form of a general server mainboard in the past is changed, different types of computing units can be conveniently subjected to heterogeneous system construction on a Switch bottom plate, and the heterogeneous computing system capable of being freely matched and deployed can improve the utilization efficiency of computing resources.

Description

Technical Field

[0001] The utility model relates to the technical field of server architecture design, and particularly relates to a heterogeneous computing system, a server and a data center. Background Art

[0002] With the rapid development and wide application of artificial intelligence (AI) technology, data centers are facing unprecedented challenges in computing power demand. The application scenarios such as the training and inference of AI models, big data analysis, and cloud computing services have increasingly high requirements for computing performance, which prompts data centers to continuously optimize the computing power supply strategy and strengthen the construction of computing power infrastructure. In this context, as the core infrastructure for computing power supply, the performance and efficiency of servers have become the focus of attention.

[0003] Traditionally, servers have occupied an important position in the field of high-performance computing with their high-speed computing power, long-term stable operation ability, and powerful data throughput ability. However, with the increase in application complexity, relying solely on the computing power of the central processing unit (CPU) in the server is difficult to meet the needs of all scenarios. Therefore, the heterogeneous computing architecture has emerged. It realizes the flexible expansion and efficient utilization of computing power by mixing and coordinating the use of multiple computing units such as CPUs, graphics processing units (GPUs), and field-programmable gate arrays (FPGAs). The motherboard architecture of a general dual-processor server, as an important carrier to support heterogeneous computing, is mainly composed of key components such as CPUs, platform controller hubs (PCHs), baseboard management controllers (BMCs), complex programmable logic devices (CPLDs), memories, hard disks, and peripheral interfaces. In this architecture, except for specific peripheral expansion cards (such as OCP Cards, Raid cards, Riser cards), storage devices (hard disks), and memory modules, most of the other components are integrated on the motherboard, forming a highly integrated computing platform. Through the SATA and MiniSAS interfaces on the PCH, the server can connect and manage various types of hard disks to meet the needs of data storage and access. To further enhance the computing power, users can insert high-performance computing units such as FPGA acceleration cards and GPU acceleration cards into the Riser card, so as to realize the collaborative work of multiple computing resources such as CPUs, GPUs, and FPGAs, that is, heterogeneous computing.

[0004] In this general server architecture, there are generally two or more CPUs. Since the CPU components are all integrated on the motherboard, and heterogeneous computing resources such as FPGA acceleration cards and GPU acceleration cards are added through the Riser card, the connection method is fixed. This fixed matching method will lead to the problem of low CPU resource utilization. Summary of the Invention

[0005] In view of the problems existing in the fixed matching method of the heterogeneous computing system for the traditional general server architecture, the present utility model provides a heterogeneous computing system, a server and a data center.

[0006] In a first aspect, the present utility model provides a heterogeneous computing system, comprising a switching unit and at least two types of computing units; the number of each type of computing unit is several, and all the computing units are standard high-speed serial computer expansion bus boards, and the switching unit is provided with several high-speed serial computer expansion bus slots;

[0007] All the computing units are respectively connected to the high-speed serial computer expansion bus slots on the switching unit.

[0008] By designing at least two types of computing units to conform to the standard high-speed serial computer expansion bus boards and matching them with a switching unit having a plurality of high-speed serial computer expansion bus slots, users can flexibly select and combine different types of computing resources according to actual needs, and easily achieve the expansion of system performance or the customization of functions. The computing units are seamlessly connected through a high-speed serial bus, effectively reducing data transmission latency and significantly improving the overall computing efficiency and system performance. By reasonably deploying and matching the computing units, the idle of resources under the traditional fixed architecture is avoided, thereby effectively reducing the system energy consumption.

[0009] By introducing at least two types of computing units, the heterogeneous computing system can provide more diverse acceleration capabilities. These two types of computing units may be optimized for different types of computing tasks. For example, one type of computing unit may be more proficient in handling integer operations or encryption and decryption tasks, and another type of computing unit may be proficient in handling floating-point operations and graphics rendering. This diversity enables the system to handle more complex and changeable application scenarios, improving the computing efficiency and adaptability.

[0010] Due to the presence of two or more types of computing units, the heterogeneous computing system can simultaneously and parallelly process different types of computing tasks. This parallel processing ability greatly improves the overall throughput of the system, shortens the task completion time, and meets the requirements of real-time or high-performance computing.

[0011] During the use of the heterogeneous computing system, different computing units can be dynamically scheduled and allocated according to the actual needs of the tasks. This diversity enables the system to handle more complex and changeable application scenarios, improving the computing efficiency and adaptability.

[0012] As an optimization of the technical solution of the present utility model, the system further comprises a high-speed interconnected memory expansion unit, and the high-speed interconnected memory expansion unit is a standard high-speed serial computer expansion bus board;

[0013] The high-speed interconnection memory expansion unit is connected to the high-speed serial computer expansion bus slot of the switching unit.

[0014] As an optimization of the technical solution of the present utility model, the computing unit includes a central processing unit computing card; the central processing unit computing card is provided with a central processing unit and a gold finger connector, and the central processing unit is connected to the gold finger connector; the central processing unit computing card is plugged into the high-speed serial computer expansion bus slot of the switching unit through the gold finger connector.

[0015] The combination of the gold finger connector and the high-speed serial computer expansion bus (such as a PCIe slot) ensures high-speed data transmission, further enhancing the system's processing power and response speed. This modular design makes the system easy to expand, and more computing cards can be added as needed to meet the growing computing requirements. The central processing unit computing card, as an independent module, can be flexibly compatible with the switching unit or the system platform, reducing the cost of hardware replacement and upgrade. The gold finger connector, as a standardized interface, ensures that the computing card can be easily inserted and removed, facilitating maintenance and upgrade.

[0016] Compared with traditional integrated computing systems, the modular design allows users to deploy necessary computing resources according to actual needs, avoiding unnecessary waste and reducing the overall cost.

[0017] As an optimization of the technical solution of the present utility model, the central processing unit computing card further includes a first voltage regulation power module, an auxiliary power interface, and a baseboard management controller, a complex programmable logic device, a storage chip, a memory slot, a hard disk connector, and a high-speed connector connected to the central processing unit; the baseboard management controller is connected to the complex programmable logic device;

[0018] The gold finger connector of the central processing unit computing card is connected to the first voltage regulation power module, and the auxiliary power interface is connected to the first voltage regulation power module.

[0019] As an optimization of the technical solution of the present utility model, the computing unit includes a field programmable gate array acceleration card, the field programmable gate array acceleration card is provided with a main control chip and a gold finger connector, and the main control chip is connected to the gold finger connector of the field programmable gate array acceleration card; the field programmable gate array acceleration card is plugged into the high-speed serial computer expansion bus slot of the switching unit through the gold finger connector of the field programmable gate array acceleration card;

[0020] The field programmable gate array acceleration card includes a second voltage regulation power module and a complex programmable logic device, a storage chip, a memory strip slot, an optical port connector, and a high-speed connector supporting multiple communication protocols connected to the main control chip;

[0021] The gold finger connector of the field programmable gate array acceleration card is connected to the second voltage regulation power module.

[0022] As an optimization of the technical solution of the present utility model, the computing unit includes a graphics processor acceleration card, the graphics processor acceleration card is provided with a gold finger connector, and the graphics processor acceleration card is plugged into the high-speed serial computer expansion bus slot of the switching unit through the gold finger connector.

[0023] As an optimization of the technical solution of the present utility model, the high-speed interconnected memory expansion unit includes a high-speed interconnected memory expansion card, the high-speed interconnected memory expansion card is provided with a high-speed interconnected memory expansion control chip and a gold finger connector, and the high-speed interconnected memory expansion control chip is connected to the gold finger connector of the high-speed interconnected memory expansion card; the high-speed interconnected memory expansion card is plugged into the high-speed serial computer expansion bus slot of the switching unit through the gold finger connector;

[0024] The high-speed interconnected memory expansion card further includes a third voltage regulation power module, a complex programmable logic device connected to the high-speed interconnected memory expansion control chip, a storage chip, and a memory card slot;

[0025] The gold finger connector of the high-speed interconnected memory expansion card is connected to the third voltage regulation power module.

[0026] As an optimization of the technical solution of the present utility model, the switching unit includes a conversion backplane, the conversion backplane is provided with a high-speed serial computer expansion bus conversion chip, and the high-speed serial computer expansion bus conversion chip is connected to a plurality of high-speed serial computer expansion bus slots;

[0027] The conversion backplane is further provided with a power supply unit of the heterogeneous computing system, a power supply of the conversion backplane, and a complex programmable logic device for managing and monitoring the conversion backplane.

[0028] In a second aspect, the technical solution of the present utility model further provides a server, and the server is provided with the heterogeneous computing system as described in the first aspect.

[0029] In a third aspect, the technical solution of the present utility model further provides a data center, and the data center includes a plurality of servers as described in the second aspect.

[0030] It can be seen from the above technical solutions that the present utility model has the following advantages: The computing unit is designed in the form of a standard PCIe card, changing the appearance form of the conventional general server motherboard, facilitating the construction of heterogeneous systems for different types of computing units and CXL memory expansion cards on the Swith backplane. This freely configurable and deployable heterogeneous computing system can improve the utilization efficiency of computing resources. Description of the Drawings

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0032] Figure 1 It is a schematic block diagram of a heterogeneous system provided by an embodiment of the present invention.

[0033] Figure 2 It is a connection block diagram of an embodiment of the present invention.

[0034] Figure 3 It is a connection block diagram in which the acceleration unit is an FPGA acceleration card in an embodiment of the present invention.

[0035] Figure 4 It is a connection block diagram in which the acceleration unit is a GPU acceleration card in an embodiment of the present invention.

[0036] Figure 5 It is a general architecture block diagram provided by an embodiment of the present invention.

[0037] Figure 6 It is a CPU computing card block diagram provided by an embodiment of the present invention.

[0038] Figure 7 It is an FPGA acceleration card block diagram provided by an embodiment of the present invention.

[0039] Figure 8 It is a CXL memory expansion card block diagram provided by an embodiment of the present invention.

[0040] Figure 9 It is a Switch backplane block diagram provided by an embodiment of the present invention. Detailed implementation manners

[0041] To enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. For a clearer description of the embodiments, the following definitions of abbreviations and key terms are provided:

[0042] CPU Central Processing Unit, central processing unit;

[0043] GPU Graphic Processing Unit Graphics Processing Unit;

[0044] FPGA Field Programmable Gate Array Field Programmable Gate Array;

[0045] CPLD Complex Programmable Logic Device Complex Programmable Logic Device;

[0046] BMC Base-board Management Controller Base-board Management Controller;

[0047] QSFP Quad Small Form-factor Pluggable Quad Small Form-factor Pluggable optical module connector;

[0048] NVMe Non-Volatile Memory express Non-Volatile Memory host controller interface specification;

[0049] CXL Compute Express Link Compute Express Link, a new high-speed interconnection technology standard, defined as high-speed interconnection in this application;

[0050] MCIO Mini Cool Edge IO A high-density high-speed connector;

[0051] OCP Open Computing Project Open Computing Project, OCP card refers to OCP network card;

[0052] BIOS Basic Input Output System Basic Input Output System;

[0053] PSU Power Supply Unit Power Supply Unit;

[0054] PCIe Peripheral Component Interconnect express High-speed serial computer expansion bus;

[0055] VRM Voltage Regulator Module, Voltage Regulator Module.

[0056] Such as Figure 1As shown in the figure, the present utility model provides a heterogeneous computing system, which includes a switching unit and at least two types of computing units; the number of each type of computing unit is several, and all computing units are standard PCIe boards, and the switching unit is provided with several PCIe slots;

[0057] All computing units are respectively connected to the PCIe slots on the switching unit.

[0058] By designing at least two types of computing units to conform to standard PCIe boards and matching them with a switching unit having multiple PCIe slots, users can flexibly select and combine different types of computing resources according to actual needs, and easily achieve the expansion of system performance or the customization of functions. The computing units are seamlessly connected through a high-speed serial bus, effectively reducing data transmission latency and significantly improving the overall computing efficiency and system performance. By reasonably deploying and matching the computing units, the idle resources under the traditional fixed architecture are avoided, thereby effectively reducing the system power consumption.

[0059] In some embodiments, as Figure 2 shown, one type of computing unit includes a CPU computing card; another type of computing unit includes an FPGA acceleration card;

[0060] The CPU computing card includes a CPU and a BMC, a CPLD, a Flash, a memory slot and a hard disk connector connected to the CPU; the BMC is connected to the CPLD; the CPU computing card is provided with a gold finger connector, and the CPU computing card is plugged into the PCIe slot of the switching unit through the gold finger connector; the CPU is connected to the gold finger connector of the CPU computing card. The CPU computing card further includes a first VRM power module, an auxiliary power interface and a high-speed connector; the power supply end of the gold finger connector of the CPU computing card is connected to the first VRM power module, and the auxiliary power interface is connected to the first VRM power module; the high-speed connector of the CPU computing card is connected to the CPU. Specifically, the block diagram of the CPU computing card is as Figure 6As shown in the figure, the main components of the board card include a CPU, BMC, CPLD, Flash, memory, hard disk, VRM power module, and other clocks. Among them, the CPU is mainly responsible for resource allocation and calculation; the BMC is mainly responsible for device information management, server status monitoring and management, server remote control management, and VGA display, etc.; the CPLD is mainly responsible for controlling the power supply timing and GPIO communication, etc., and the VRM is different power modules that output different voltage values for the components on the board card to use; DDR_CH1~DDR_CH4 represent RDIMM memory slots; the MCIOX8 connector is respectively connected to the optical port QSFP28, PCIe GEN4, and PCIe GEN5 signals, where QSFP28 can perform optical communication with other devices, and PCIe GEN4 and PCIe GEN5 can be connected to NVMe SSDs or other PCIe devices; XDP, UART, etc. are the standard debugging interfaces of the CPU; in addition, as long as the CPU computing card is connected to 12V at the auxiliary power supply interface (Power AUX), a monitor is connected to the VGA port, and a mouse and keyboard are connected to the USB port, the CPU computing card can work independently as a micro server normally.

[0061] The FPGA acceleration card includes a second voltage regulation power module, a main control chip, and a complex programmable logic device, a storage chip, and a memory module slot connected to the main control chip;

[0062] The FPGA acceleration card also includes an optical port connector and a high-speed connector supporting multiple communication protocols connected to the main control chip; the FPGA acceleration card is provided with a gold finger connector, and the FPGA acceleration card is inserted into the high-speed serial computer expansion bus slot of the switching unit through the gold finger connector; the main control chip is connected to the gold finger connector of the FPGA acceleration card; the power supply end of the gold finger connector of the FPGA acceleration card is connected to the second voltage regulation power module.

[0063] Specifically, the block diagram of the FPGA acceleration card is as Figure 7As shown in the figure, the main components of the board are FPGA, CPLD, Flash, and VRM power modules. Among them, FPGA is the main control chip responsible for accelerating calculations and communications. CPLD is responsible for controlling power supply timing and GPIO communications. VRM is different power modules that output different voltage values for other components on the board. DDR5_1~DDR5_4 represent four-channel memory slots, and 4 memory modules can be configured. QSFP28_1 and QSFP28_2 are optical port connectors of FPGA, which can communicate with other computing units or acceleration units. 2*MCIO X8 are two high-speed connectors, both of which support PCIe Gen5.0 and CXL protocol communications. When used for NVMe SSD hard disk expansion, 2*MCIO X8 and the gold fingers both use the PCIe Gen5.0 protocol for communication. When used for memory expansion, 2*MCIO X8 and the gold fingers both use the CXL protocol for communication.

[0064] The heterogeneous computing system combines the advantages of general-purpose processors (CPU computing cards) and dedicated accelerators (FPGA acceleration cards). Through this combination, the allocation of computing resources can be optimized. The FPGA acceleration card can execute highly parallelized computing tasks, while the CPU computing card is responsible for complex logic processing and data management. The two are seamlessly connected through a high-speed serial bus, effectively reducing data transmission latency and significantly improving the overall computing efficiency and system performance. By reasonably deploying these two types of computing units, the heterogeneous computing system can allocate resources according to requirements, avoiding resource idleness in traditional single fixed computing architectures, thereby effectively reducing system power consumption.

[0065] In some embodiments, as Figure 3 shown, one type of computing unit includes a CPU computing card, and the other type of computing unit includes a GPU acceleration card;

[0066] The CPU computing card includes a CPU, and a BMC, CPLD, Flash, memory slots, and a hard disk connector connected to the CPU; the BMC is connected to the CPLD; the CPU computing card is provided with a gold finger connector, and the CPU computing card is plugged into the PCIe slot of the switching unit through the gold finger connector; the CPU is connected to the gold finger connector of the CPU computing card. The CPU computing card also includes a first VRM power module, an auxiliary power interface, and a high-speed connector; the power supply terminal of the gold finger connector of the CPU computing card is connected to the first VRM power module, and the auxiliary power interface is connected to the first VRM power module; the high-speed connector of the CPU computing card is connected to the CPU.

[0067] The GPU acceleration card is plugged into the high-speed serial computer expansion bus slot on the switching unit through a gold finger. It should be noted that the GPU acceleration card is a standard PCIe interface GPU acceleration card that already exists.

[0068] In some embodiments, such as Figure 4 shown, the heterogeneous system includes three types of computing units, specifically including a CPU computing card, an FPGA acceleration card, and a GPU acceleration card;

[0069] The heterogeneous computing system can provide more diverse acceleration capabilities. The FPGA acceleration card and the GPU acceleration card, as acceleration units, can be optimized for different types of computing tasks. For example, the FPGA acceleration card may be better at handling integer operations or encryption and decryption tasks, while the GPU acceleration card may be good at handling floating-point operations and graphics rendering. This diversity enables the system to handle more complex and variable application scenarios, improving computing efficiency and adaptability.

[0070] Due to the existence of multiple computing units, the heterogeneous computing system can simultaneously and parallelly process multiple different types of computing tasks. This parallel processing ability greatly improves the overall throughput of the system, shortens the task completion time, and meets the requirements of real-time or high-performance computing.

[0071] In the heterogeneous computing system, the combination of different computing units can be dynamically scheduled and allocated according to actual needs. For example, when dealing with a large number of integer operations, resources can be preferentially allocated to the FPGA acceleration card; when facing compute-intensive tasks, the GPU acceleration card can be activated. This dynamic resource scheduling mechanism can optimize resource utilization, reduce resource waste, and further improve system performance.

[0072] In some embodiments, the heterogeneous system includes three types of computing units, specifically including a CPU computing card, an FPGA acceleration card, and a GPU acceleration card. Here, the number of CPU computing cards can be greater than 1, and the numbers of FPGA acceleration cards and GPU acceleration cards can also be set according to needs.

[0073] In some embodiments, the heterogeneous system includes two types of computing units. Here, the two types of computing units are the FPGA acceleration card and the GPU acceleration card respectively.

[0074] In some embodiments, such as Figure 5 shown, the system further includes a CXL memory expansion unit, and the CXL memory expansion unit is a standard PCIe board;

[0075] The CXL memory expansion unit is connected to the PCIe slot on the switching unit. The CXL memory expansion unit includes a CXL memory expansion card, and the CXL memory expansion card includes a third voltage regulation power module, a CXL memory expansion control chip, a complex programmable logic device connected to the CXL memory expansion control chip, a storage chip, and a memory card slot;

[0076] The CXL memory expansion card is provided with a gold finger connector, and the CXL memory expansion card is plugged into the PCIe slot of the switching unit through the gold finger connector; the CXL memory expansion control chip is connected to the gold finger connector of the CXL memory expansion card; the power supply end of the gold finger connector of the CXL memory expansion card is connected to the third voltage regulation power module. Specifically, the block diagram of the CXL memory expansion card is as Figure 8 shown. The main components of this board are the CXL memory expansion control chip, CPLD, Flash, debugging interface, and RDIMM memory card slot. Inserted into the PCIe slot of the switching unit, memory expansion can be performed.

[0077] In the embodiment of the present utility model, the switching unit includes a Switch baseboard, and a PCIe conversion chip is arranged on the Switch baseboard. The PCIe conversion chip is connected to a plurality of PCIe slots; a power supply unit for the heterogeneous computing system, the power supply of the Switch baseboard, and a CPLD for managing and monitoring the Switch baseboard are also arranged on the Switch baseboard. The block diagram of the Switch baseboard is as Figure 9 shown. The main components of this board are the PCIe Gen5.0 Switch, CPLD, VRM, PSU CONN, and PCIe GEN5.0 Slot. Among them, the PCIe Gen5.0 Switch is the main component. Its upstream input is the CPU computing card, and its downstream output is the FPGA acceleration card, GPU acceleration card, memory expansion card, etc. The specific number of supported boards is determined by the Lane of the PCIe 5.0 Switch; the PSU is the power supply unit of the entire heterogeneous computing system, and the VRM is to output other power required by the Switch board; the CPLD is to manage and monitor the Switch baseboard; the GPU accelerator is not introduced and described in the present utility model because this Switch baseboard supports the standard PCIe form GPU acceleration cards on the market.

[0078] This heterogeneous computing system can configure the number of CPU computing cards, FPGA acceleration cards, GPU acceleration cards, and CXL memory expansion cards according to the actual business situation. Except for the CPU computing card with a fixed slot position, i.e., the upstream port of the Switch, the other acceleration cards and memory expansion cards can be randomly configured in terms of position and number at the downstream ports of the Switch. The traditional server motherboard is designed as a standard PCIe card. Additionally, the appearance forms of the FPGA acceleration card, GPU acceleration card, and CXL memory expansion card are all standard PCIe cards. They are combined and inserted into the Switch backplane to freely form a heterogeneous computing system, and the number of CPU computing cards, acceleration cards, and CXL memory expansion cards can be freely selected according to the application scenario to reasonably allocate resources.

[0079] It should be noted that for the Switch backplane provided by the present utility model, other types of PCIe-formatted boards can also be inserted into the PCIe Slots of the Switch backplane, such as DPU cards, ASIC acceleration cards, and network cards. Additionally, the number of Switches and the number of PCIe Slots used in the Switch backplane can be increased.

[0080] The embodiment of the present utility model also provides a server, and the server is provided with the heterogeneous computing system as described in the above embodiment.

[0081] The embodiment of the present utility model also provides a data center, and the data center includes a plurality of servers as described in the above embodiment.

[0082] Although the present utility model has been described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the present utility model is not limited thereto. Without departing from the spirit and essence of the present utility model, those of ordinary skill in the art can make various equivalent modifications or substitutions to the embodiments of the present utility model, and these modifications or substitutions should all be within the scope covered by the present utility model. / Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present utility model, and all should be covered within the protection scope of the present utility model.

Claims

1. A heterogeneous computing system, characterized in that, It includes a switching unit and at least two types of computing units; the number of each type of computing unit is several, and all computing units are standard high-speed serial computer expansion bus boards, and the switching unit is provided with several high-speed serial computer expansion bus slots; All computing units are respectively connected to the high-speed serial computer expansion bus slots of the switching unit.

2. The heterogeneous computing system according to claim 1, wherein This system further includes a high-speed interconnected memory expansion unit, and the high-speed interconnected memory expansion unit is a standard high-speed serial computer expansion bus board; The high-speed interconnected memory expansion unit is connected to the high-speed serial computer expansion bus slots of the switching unit.

3. The heterogeneous computing system according to claim 1, wherein The computing unit includes a central processing unit computing card; the central processing unit computing card is provided with a central processing unit and a gold finger connector, and the central processing unit is connected to the gold finger connector; the central processing unit computing card is plugged into the high-speed serial computer expansion bus slots of the switching unit through the gold finger connector.

4. The heterogeneous computing system according to claim 3, wherein The central processing unit computing card further includes a first voltage regulating power supply module, an auxiliary power interface, and a baseboard management controller, a complex programmable logic device, a storage chip, a memory slot, a hard disk connector, and a high-speed connector connected to the central processing unit; the baseboard management controller is connected to the complex programmable logic device; The gold finger connector of the central processing unit computing card is connected to the first voltage regulating power supply module, and the auxiliary power interface is connected to the first voltage regulating power supply module.

5. The heterogeneous computing system according to claim 1 or 4, wherein The computing unit includes a field programmable gate array acceleration card, the field programmable gate array acceleration card is provided with a main control chip and a gold finger connector, and the main control chip is connected to the gold finger connector of the field programmable gate array acceleration card; the field programmable gate array acceleration card is plugged into the high-speed serial computer expansion bus slots of the switching unit through the gold finger connector of the field programmable gate array acceleration card; The field programmable gate array acceleration card includes a second voltage regulating power supply module and a complex programmable logic device, a storage chip, a memory strip slot, an optical port connector, and a high-speed connector supporting multiple communication protocols connected to the main control chip; The gold finger connector of the field programmable gate array acceleration card is connected to the second voltage regulating power supply module.

6. The heterogeneous computing system according to claim 5, wherein The computing unit includes a graphics processing unit acceleration card, the graphics processing unit acceleration card is provided with a gold finger connector, and the graphics processing unit acceleration card is plugged into the high-speed serial computer expansion bus slots of the switching unit through the gold finger connector.

7. The heterogeneous computing system according to claim 2, wherein The high-speed interconnected memory expansion unit includes a high-speed interconnected memory expansion card, the high-speed interconnected memory expansion card is provided with a high-speed interconnected memory expansion control chip and a gold finger connector, and the high-speed interconnected memory expansion control chip is connected to the gold finger connector of the high-speed interconnected memory expansion card; the high-speed interconnected memory expansion card is plugged into the high-speed serial computer expansion bus slots of the switching unit through the gold finger connector; The high-speed interconnected memory expansion card further includes a third voltage regulating power supply module and a complex programmable logic device, a storage chip, and a memory card slot connected to the high-speed interconnected memory expansion control chip; The gold finger connector of the high-speed interconnected memory expansion card is connected to the third voltage regulation power supply module.

8. The heterogeneous computing system according to claim 6, wherein The switching unit includes a conversion base plate, on which a high-speed serial computer expansion bus conversion chip is arranged. The high-speed serial computer expansion bus conversion chip is connected to a plurality of high-speed serial computer expansion bus slots; The conversion base plate is further provided with a power supply unit for the heterogeneous computing system, the power supply of the conversion base plate, and a complex programmable logic device for managing and monitoring the conversion base plate.

9. A server, characterized in that, The server is provided with the heterogeneous computing system as described in any one of claims 1-8.

10. A data center, characterized in that, The data center includes a plurality of servers as described in claim 9.

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