High-power patch device

The TO-263-7L packaging of SiC chips with parallel connections and a heat sink addresses the size and inductance issues of traditional SiC devices, improving high-speed switching and reducing EMI noise.

CN223108892UActive Publication Date: 2025-07-15SHANDONG JINGDAO MICROELECTRONICS
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Patent Information

Application Number
CN202421479368.6
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-06-26
Publication Date
2025-07-15
Estimated Expiration
2034-06-26

AI Technical Summary

Technical Problem

Most of the existing silicon carbide power devices are plug-in structures, with large size and high overall package inductance, which limits the high-speed switching performance of silicon carbide MOSFETs.

Method used

The TO-263-7L package structure adopts a high-power chip device, including a metal frame, a SiC chip and independent pins. The pins are designed as G pole, KS pole and five S pole. They are arranged in parallel and connected with bonded wires, and combined with the back heat sink to form a z-shaped structure.

Benefits of technology

It achieves smaller device size, lower package impedance, lower conduction loss, reduce EMI noise, and improves the high-speed switching performance of silicon carbide MOSFETs.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model provides a high-power surface-mounted device, which relates to the field of semiconductor discrete devices and comprises a metal frame, a SiC chip and a plurality of pins, the SiC chip is arranged on a PAD surface of the metal frame in a die bonding manner, the pins are independent of the metal frame, and the SiC chip is plastically packaged in a plastic package body. The pins comprise a G-pole pin, a KS-pole pin and five S-pole pins which extend out of the plastic package body and are arranged in parallel, one ends of the five S-pole pins are gathered in the plastic package body and are respectively connected to a source electrode of the SiC chip through bonding wires, the KS-pole pin is connected to the source electrode of the SiC chip through bonding wires in the plastic package body, and the other ends of the five S-pole pins are connected to the source electrode of the SiC chip through bonding wires in the plastic package body. The G pole pin is connected to the grid electrode of the SiC chip through a bonding wire in the plastic package body; according to the utility model, the SiC chip is packaged in a surface-mounted manner, specifically, a TO-263-7L packaging structure is adopted, so that compared with the traditional plug-in packaging, the size is smaller, and the surface-mounted welding is simpler and more convenient; and five pins are connected in parallel to serve as a source electrode (S), so that the packaging impedance is lower, the conduction loss is lower under the condition of large current, and the overall packaging inductance is lower.
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Description

Technical Field

[0001] The utility model relates to the technical field of high-power devices of semiconductor discrete devices, and particularly relates to a high-power chip device. Background Art

[0002] As a wide-bandgap semiconductor material, silicon carbide (SiC) shows great potential in the field of power devices due to its superior physical properties. Compared with traditional silicon (Si) materials, SiC power devices have characteristics such as high voltage, high frequency, high temperature, and radiation resistance, which helps to improve the efficiency of power systems, reduce volume, and lower energy consumption. With the rapid development of new energy, electric vehicles, high-speed railways, smart grids and other fields, the market demand for SiC power devices is increasing day by day.

[0003] Existing SiC power devices are mostly in a plug-in structure, with problems such as large volume and high overall package inductance, which restricts the high-speed switching performance of SiC MOSFETs. Summary of the Utility Model

[0004] The utility model provides a high-power chip device for solving the above problems existing in the prior art.

[0005] The technical solution for solving the above technical problems of the utility model is as follows: A high-power chip device includes a metal frame, a SiC chip fixed on the PAD surface of the metal frame, and a plurality of pins independent of the metal frame. The SiC chip is encapsulated in a plastic package. It is characterized in that the pins include a G-pin, a KS-pin, and five S-pins arranged side by side and extending outside the plastic package. One ends of the five S-pins converge inside the plastic package and are respectively connected to the source electrode of the SiC chip through bonding wires. The KS-pin is connected to the source electrode of the SiC chip through a bonding wire inside the plastic package, and the G-pin is connected to the gate electrode of the SiC chip through a bonding wire inside the plastic package.

[0006] Further, the high-power chip device is in a TO-263-7L package structure.

[0007] Further, the G-pin, the KS-pin, and the five S-pins extend outside the plastic package in a z-shape.

[0008] Furthermore, the ends of the G-pin, the KS-pin, and the five S-pins are flush with the bottom surface of the plastic package.

[0009] Further, the metal frame leaks out at the back of the plastic package and serves as a heat sink.

[0010] Further, the G-pin is independent of the KS-pin and the five S-pins.

[0011] The beneficial effects of the present utility model are as follows: The present utility model adopts a surface mount package for the SiC chip, specifically a TO-263-7L package structure, which is smaller in volume than the traditional through-hole package and is more convenient for surface mount soldering. Moreover, 5 pins are connected in parallel as the source electrode (S), and the package impedance is lower. Under high-current conditions, the conduction loss is lower. At the same time, the KS pin, that is, the Kelvin source pin (Kelvin Source), is adopted to reduce the influence of the main circuit on the drive signal, and the heat sink on the back is used as the drain (D). The overall package inductance is lower, thereby reducing the oscillation of the main circuit and reducing the EMI noise, which is more conducive to giving full play to the advantages of the silicon carbide (SiC) MOSFET's high-speed switching. Brief Description of the Drawings

[0012] Figure 1 is a schematic structural diagram of the present utility model (excluding the plastic package);

[0013] Figure 2 is a schematic diagram of the external structure of the present utility model;

[0014] Figure 3 is a schematic structural diagram of the SiC chip of the present utility model;

[0015] In the figure: 1. Frame, 2. First bonding wire, 3. Second bonding wire, 4. G-pin, 5. KS-pin, 6. S-pin, 7. Third bonding wire, 8. SiC chip, 81. Drain, 82. Source, 83. Gate, 84. Substrate, 85. N-epitaxy. Detailed Embodiment

[0016] The principle and features of the present utility model will be described below. The examples given are only used to explain the present utility model and are not intended to limit the scope of the present utility model.

[0017] As shown in the attached drawings, the high-power chip device of this embodiment has a TO-263-7L package structure, which includes a metal frame 1, a SiC chip 8 fixed on the PAD surface of the metal frame 1 by a soft solder (such as solder paste), and a plurality of pins independent of the metal frame 1. The SiC chip 8 is encapsulated in a plastic package. The pins include a G-pin 4, a KS-pin 5 and five S-pins 6 arranged side by side and extending outside the plastic package. One ends of the five S-pins 6 converge inside the plastic package and are respectively connected to the source electrode of the SiC chip 8 through bonding wires. The KS-pin 5 is connected to the source electrode of the SiC chip 8 through a bonding wire inside the plastic package. The G-pin 4 is connected to the gate electrode of the SiC chip 8 through a bonding wire inside the plastic package. The SiC chip 8 is connected to the corresponding pins through ultrasonic bonding using bonding wire one 2, bonding wire two 3 and bonding wire three 7. Among them, bonding wire two 3 is connected to the G-pin 4, bonding wire one 2 is connected to the KS-pin 5, and bonding wire three 7 is connected to the S-pin 6 to complete the bonding wires. After the bonding wires are completed, it is necessary to encapsulate with epoxy resin. After encapsulation, it needs to be cured for a certain time to make the epoxy resin cured and stable. Using epoxy resin encapsulation has good insulation properties and protects the components from external influences. Among them, all the bonding wire areas of the pins will be encapsulated with epoxy resin. The metal frame 1 is exposed at the back of the plastic package as a back heat sink. The position of the back heat sink and the position where the pins are exposed outside will be tinned later.

[0018] The G-pin is independent of the KS-pin and the five S-pins. The G-pin, the KS-pin and the five S-pins extend outside the plastic package in a z-shape, and the ends of the G-pin, the KS-pin and the five S-pins are flush with the bottom surface of the plastic package.

[0019] The utility model is provided with five pins in parallel as the source electrode (S), with lower packaging impedance. Under high-current conditions, the conduction loss is lower. At the same time, the Kelvin Source is adopted to reduce the influence of the main circuit on the drive signal, and the back heat sink is used as the drain (D). The overall packaging inductance is lower, thereby reducing the oscillation of the main circuit and reducing the EMI noise. The product performance has more advantages and is conducive to giving full play to the advantages of the high-speed switching of silicon carbide (SiC) MOSFET. And the overall volume is smaller than that of the plug-in type, which is conducive to the miniaturization of electronic products.

Claims

1. A high-power chip device includes a metal frame, a SiC chip fixed on the PAD surface of the metal frame, and multiple pins independent of the metal frame. The SiC chip is encapsulated in a plastic package. It is characterized in that, The pins include a G - pole pin, a KS - pole pin, and five S - pole pins arranged in parallel and extending outside the plastic package. One ends of the five S - pole pins converge inside the plastic package and are respectively connected to the source electrode of the SiC chip through bonding wires. The KS - pole pin is connected to the source electrode of the SiC chip through a bonding wire inside the plastic package, and the G - pole pin is connected to the gate electrode of the SiC chip through a bonding wire inside the plastic package.

2. The high-power chip device according to claim 1, wherein, It is a TO - 263 - 7L package structure.

3. The high-power chip device according to claim 1 or 2, characterized in that The G - pole pin, the KS - pole pin, and the five S - pole pins are led out outside the plastic package in a zigzag shape.

4. The high-power chip device according to claim 3, wherein The ends of the G - pole pin, the KS - pole pin, and the five S - pole pins are flush with the bottom surface of the plastic package.

5. The high-power chip device according to claim 1, wherein The G - pole pin is independent of the KS - pole pin and the five S - pole pins.

6. The high-power chip device according to claim 1, characterized in that, The metal frame leaks out at the back of the plastic package and serves as a heat sink.