Solar cell and photovoltaic module
By using aluminum or copper electrodes with a transparent conductive oxide layer to separate and connect with doped semiconductor layers, the issue of high silver-based metalization costs and electrode burn-through is addressed, achieving cost-effective and efficient solar cell performance.
Patent Information
- Application Number
- CN202421841854.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2034-07-31
AI Technical Summary
The metallization cost of existing crystalline silicon batteries is high and there is a risk of replacing electrode materials burning through the doped layer, resulting in a decrease in battery efficiency.
Aluminum or copper electrodes are used instead of silver electrodes, and a transparent conductive layer is provided between the electrode and the doped semiconductor layer. The conductive layer is physically isolated from the doped semiconductor layer to avoid burning through while maintaining current transmission. In combination, the area of the electrode and the conductive layer are precisely controlled to reduce the amount of metal usage.
The metallization cost is reduced, the conversion efficiency and stability of the battery are improved, the problem of electrode burning through the doped layer is avoided, and an efficient and low-cost solar cell design is achieved.
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Figure CN223110434U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of solar cells, and in particular to a solar cell and a photovoltaic module. Background Art
[0002] With the rapid development of crystalline silicon cells, the efficiency improvement of cells such as TOPCon has achieved rapid development, but still faces the practical problem of metallization cost.
[0003] Currently, the main way to achieve metallization is to form a patterned electrode on the surface of the cell structure by screen printing, and the metal paste used is mainly composed of Ag component, which is obviously the key factor leading to high cost. If silver paste can be replaced by other metal materials, the metallization cost will be significantly reduced, but replacing the electrode material will have the risk of burning through the doped layer, thereby causing a decrease in cell efficiency. Summary of the Utility Model
[0004] In view of the above problems, embodiments of the present disclosure provide a solar cell and a photovoltaic module.
[0005] One aspect of the present disclosure provides a solar cell, including: a silicon substrate; a tunneling oxide layer disposed on a first side of the silicon substrate; a first doped semiconductor layer disposed on a side of the tunneling oxide layer away from the silicon substrate; a first passivation layer disposed on a side of the first doped semiconductor layer away from the silicon substrate; and a first electrode disposed on a side of the first passivation layer away from the silicon substrate. Wherein, the first electrode penetrates through the first passivation layer, a conductive layer is disposed between the first electrode and the first doped semiconductor layer, and a projected area of the conductive layer on the silicon substrate is smaller than a projected area of the first passivation layer on the silicon substrate. The first electrode is an aluminum electrode or a copper electrode. The material of the conductive layer is a transparent conductive oxide.
[0006] According to an embodiment of the present disclosure, the first doped semiconductor layer is an N-type doped semiconductor layer.
[0007] According to an embodiment of the present disclosure, the first electrode includes a plurality of sub-electrodes extending along a first direction and spaced apart along a second direction. And a metallization area of the first electrode is 3% - 10%.
[0008] According to an embodiment of the present disclosure, a width range of each sub-electrode is 20μm - 50μm. The conductive layer extends along the first direction and is spaced apart along the second direction. A width of the conductive layer is greater than or equal to a width of the sub-electrode and less than or equal to twice the width of the sub-electrode. Or, the width of the conductive layer is greater than or equal to the width of the sub-electrode and less than 50μm.
[0009] According to an embodiment of the present disclosure, a thickness range of the conductive layer is 10nm - 30nm, and a thickness range of the first doped semiconductor layer is 20nm - 150nm.
[0010] According to an embodiment of the present disclosure, the solar cell further includes: a second doped semiconductor layer disposed on the second side of the silicon substrate, where the second side is the opposite side of the first side. A second electrode in contact with the second doped semiconductor layer, and the second electrode is a silver electrode.
[0011] According to an embodiment of the present disclosure, the solar cell further includes: a first anti-reflection layer disposed on the side of the first passivation layer away from the silicon substrate. Wherein, the first electrode completely penetrates through the first anti-reflection layer.
[0012] According to an embodiment of the present disclosure, the solar cell further includes: a third doped semiconductor layer disposed on the side of the tunneling oxide layer away from the silicon substrate. The conductivity type of the third doped semiconductor layer is opposite to that of the first doped semiconductor layer. A third electrode disposed on the side of the first passivation layer away from the silicon substrate. A third passivation layer disposed on the second side of the silicon substrate, where the second side is the opposite side of the first side. Wherein, the third doped semiconductor layer is disposed at an interval non-contact with the first doped semiconductor layer. The third electrode penetrates through the first passivation layer, and a conductive layer is disposed between the third electrode and the third doped semiconductor layer, and the third electrode is electrically connected to the third doped semiconductor layer through the conductive layer.
[0013] According to an embodiment of the present disclosure, the silicon substrate is an n-type single crystal silicon or a p-type single crystal silicon.
[0014] Another aspect of the present disclosure provides a photovoltaic module, including: a plurality of solar cells according to any embodiment of the present disclosure. A packaging layer for covering the surfaces of the plurality of solar cells. A cover plate for covering the surface of the packaging layer facing away from the plurality of solar cells.
[0015] According to an embodiment of the present disclosure, low-cost aluminum or copper is selected as the electrode material, and by disposing a transparent conductive layer between the first electrode and the first doped semiconductor layer, the first electrode and the first doped semiconductor layer can be physically separated, while not affecting the current transmission between the first electrode and the first doped semiconductor layer, avoiding the first electrode burning through the first doped semiconductor layer; at the same time, the local setting of the transparent conductive layer can reduce the usage amount of the transparent conductive layer, and the first doped semiconductor layer not covered by the transparent conductive layer can obtain better surface passivation effect. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above content and other objects, features and advantages of the present disclosure will become clearer. In the drawings:
[0017] Figure 1 Schematically shows a partial structural diagram of a solar cell according to an embodiment of the present disclosure;
[0018] Figure 2 Schematically shows a structural diagram of a conductive layer mask according to an embodiment of the present disclosure;
[0019] Figure 3 Schematically shows the structural diagram of a topcon solar cell according to an embodiment of the present disclosure;
[0020] Figure 4 Schematically shows the structural diagram of a topcon solar cell according to another embodiment of the present disclosure;
[0021] Figure 5 Schematically shows the structural diagram of a back contact solar cell according to an embodiment of the present disclosure;
[0022] Figure 6 Schematically shows the flow chart of the preparation method of a solar cell according to an embodiment of the present disclosure.
[0023]
Description of the reference numerals
[0024] 1 - silicon substrate; 2 - tunneling oxide layer; 3 - first doped semiconductor layer; 4 - first passivation layer; 5 - first electrode; 6 - conductive layer; 7 - second doped semiconductor layer; 8 - second passivation layer; 9 - second antireflection layer; 10 - second electrode; 11 - first antireflection layer; 12 - third doped semiconductor layer; 13 - third electrode; 14 - third passivation layer; 15 - third antireflection layer. Detailed embodiments
[0025] To make the objectives, technical solutions and advantages of the present disclosure more clear and understandable, the present disclosure will be further described in detail below with reference to specific embodiments and the accompanying drawings.
[0026] It should be noted that in the description of the drawings or the specification, similar or identical parts are all denoted by the same reference numerals. The technical features in each of the embodiments exemplified in the specification can be freely combined to form a new solution on the premise of no conflict. In addition, each claim can be regarded as an independent embodiment, or the technical features in each claim can be combined to form a new embodiment. Moreover, in the drawings, the shape or thickness of the embodiments can be enlarged and simplified or conveniently marked. Furthermore, the elements or implementation manners not shown or described in the drawings are in the forms known to those of ordinary skill in the art. In addition, although this document may provide examples containing specific values of parameters, it should be understood that the parameters do not necessarily exactly equal the corresponding values, but may approximate the corresponding values within an acceptable error tolerance or design constraints.
[0027] Unless there are technical obstacles or contradictions, the above various embodiments of the present disclosure can be freely combined to form additional embodiments, and these additional embodiments are all within the protection scope of the present disclosure.
[0028] Although the present disclosure has been described in conjunction with the accompanying drawings, the embodiments disclosed in the drawings are intended to exemplarily illustrate the preferred embodiments of the present disclosure and should not be construed as a limitation on the present disclosure. The dimensional ratios in the drawings are merely illustrative and should not be construed as a limitation on the present disclosure.
[0029] Although some embodiments of the general concept of the present disclosure have been shown and described, those of ordinary skill in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.
[0030] Figure 1 A partial structural view of a solar cell according to an embodiment of the present disclosure is schematically shown.
[0031] According to an embodiment of the present disclosure, as Figure 1 shown, the present disclosure provides a solar cell, including: a silicon substrate 1. A tunneling oxide layer 2 provided on the first side of the silicon substrate 1. A first doped semiconductor layer 3 provided on the side of the tunneling oxide layer 2 away from the silicon substrate 1. A first passivation layer 4 provided on the side of the first doped semiconductor layer 3 away from the silicon substrate 1. And a first electrode 5 provided on the side of the first passivation layer 4 away from the silicon substrate 1. Wherein, the first electrode 5 passes through the first passivation layer 4, a conductive layer 6 is provided between the first electrode 5 and the first doped semiconductor layer 3, and the projected area of the conductive layer 6 on the silicon substrate 1 is smaller than the projected area of the first passivation layer 4 on the silicon substrate 1. The first electrode is an aluminum electrode or a copper electrode. The material of the conductive layer is a transparent conductive oxide.
[0032] In some embodiments, the solar cell of the present disclosure is, for example, a typical passivated contact solar cell structure.
[0033] For example, an n-type single crystal silicon or polycrystalline silicon wafer is used as the basis of the solar cell.
[0034] On the n-type side of the p-n junction, a very thin layer of silicon dioxide (SiO2) is formed on the silicon surface through a thermal oxidation process. The function of this oxide layer is to act as a tunneling layer, allowing electrons to flow from the n-type silicon to the first doped semiconductor layer through quantum tunneling effect.
[0035] A high-concentration n+-type doped layer is usually used, located above the tunneling oxide layer, and phosphorus (P) can be used as the dopant. This doped layer helps to form a good ohmic contact and reduce carrier recombination.
[0036] On the first doped semiconductor layer, a layer of passivation material such as Al2O3 (aluminum oxide) or SiN x (silicon nitride) is deposited. This layer of material can effectively passivate the silicon surface, reduce surface recombination, and improve the cell efficiency.
[0037] On top of the first passivation layer, the passivation layer is locally removed by laser ablation, and then aluminum or copper electrodes, their stacks, etc. are realized by screen printing. To prevent the aluminum paste or copper paste from burning through the first doped semiconductor layer, a thin conductive layer can be deposited in advance between the metal electrode and the first doped semiconductor layer.
[0038] A conductive layer is provided between the metal electrode and the first doped semiconductor layer. Its function is to ensure good electrical contact and prevent the metal from burning through the doped layer. The projected area of the conductive layer on the silicon substrate is smaller than the projected area of the first passivation layer on the silicon substrate, which means that the conductive layer only exists in the metallization area and does not cover the entire first doped semiconductor layer. This local setting of the transparent conductive layer can reduce the usage amount of the transparent conductive layer, and the first doped semiconductor layer not covered by the transparent conductive layer is covered by the first passivation layer, so that a better surface passivation effect can be obtained.
[0039] Through the combination of passivation contact and tunneling oxide layer, carrier recombination is reduced, the open-circuit voltage and fill factor are increased, thereby improving the conversion efficiency of the battery. Adding a conductive layer between the metal electrode and the doped layer can prevent the metal from penetrating into the doped layer during the high-temperature sintering process, ensuring the long-term stability and reliability of the battery. By precisely controlling the areas of the conductive layer and the electrode, the usage amount of metal materials can be reduced, thereby reducing the production cost.
[0040] According to an embodiment of the present disclosure, the first electrode is an aluminum electrode or a copper electrode, and the conductive layer is a transparent conductive oxide. The first doped semiconductor layer is an N-type doped semiconductor layer. In some embodiments, in combination with the above embodiments, a specific solar cell design is further described in detail, where the first electrode is an aluminum electrode and the material of the conductive layer is a transparent conductive oxide (TCO):
[0041] The silicon substrate is, for example, an n-type single-crystalline silicon wafer with a thickness of about 150 μm to 200 μm.
[0042] A silicon dioxide (SiO2) layer with a thickness of about 1.5 nm is deposited on the front surface of the n-type silicon.
[0043] An n+-type doped layer with a thickness of about 30 nm is deposited above the tunneling oxide layer, and phosphorus (P) is used as a dopant to provide good ohmic contact.
[0044] A layer of about 2 nm thick Al2O3 (aluminum oxide) is deposited as a passivation layer, which can be realized by atomic layer deposition (ALD) technology.
[0045] Between the aluminum electrode and the first doped semiconductor layer, a transparent conductive oxide (TCO) is used as the conductive layer, such as indium tin oxide (ITO) or aluminum-doped zinc oxide (AZO), with a thickness of about 20 nm. This TCO material not only provides good conductivity but also maintains high transparency, without affecting the photoelectric conversion efficiency of the battery.
[0046] Aluminum (Al) is used as the main electrode material, and an electrode pattern is formed on the first passivation layer through screen printing technology. To form good contact between the electrode and the first doped semiconductor layer, for example, the first passivation layer can be locally removed by laser ablation technology first, and then the aluminum electrode is deposited.
[0047] By introducing the TCO conductive layer, the problem of metal burning through the doped layer is avoided, while maintaining good electrical contact and transparency, which is beneficial to improving the overall photoelectric conversion efficiency of the battery. The aluminum electrode is relatively cheap, easy to process, and the local TCO layer can reduce the usage of TCO, thus reducing the production cost. The presence of the TCO layer can improve the stability between the electrode and the doped layer and extend the service life of the battery.
[0048] In particular, since aluminum is a P-type dopant, when the first doped semiconductor layer is an N-type doped layer, such as a phosphorus-doped polysilicon layer, the entry of aluminum elements into the N-type first doped semiconductor layer will weaken the field passivation effect of the N-type first doped semiconductor layer. Therefore, when there is a barrier of the TCO layer, aluminum elements cannot enter the N-type doped layer, thus avoiding the damage to the field passivation effect of the N-type first doped semiconductor layer.
[0049] Figure 2 The structural diagram of the conductive layer mask according to an embodiment of the present disclosure is schematically shown.
[0050] According to an embodiment of the present disclosure, the first electrode includes a plurality of sub-electrodes extending along a first direction and spaced apart along a second direction. And the metallization area of the first electrode is 3% - 10%.
[0051] In some embodiments, the silicon substrate, such as an n-type monocrystalline silicon wafer with a thickness of about 100 μm - 200 μm, is the core component of the battery, responsible for absorbing photons and generating electron-hole pairs.
[0052] An ultra-thin SiO2 layer with a thickness of about 1.5 nm is formed on the back of the silicon substrate. This oxide layer serves as a tunneling layer, allowing electrons to flow from the n-type silicon to the subsequent doped layer through the tunneling effect.
[0053] An n+-type doped layer with a thickness of about 30 nm is formed on the tunneling oxide layer, using phosphorus (P) as the dopant. This layer helps to form a low-resistance ohmic contact and a field passivation effect, facilitating the rapid transmission of electrons.
[0054] An Al2O3 layer, SiN layer or SiO2 layer with a thickness of about 2 nm is deposited on the first doped semiconductor layer, which plays a passivation role, reduces surface recombination, and improves the cell efficiency. x Located above the first doped semiconductor layer, ITO or AZO is used as the conductive layer with a thickness of about 30 nm. This layer of TCO material provides additional conductivity while maintaining high transparency.
[0055] The first electrode is made of, for example, aluminum paste, designed as a series of elongated stripes extending along the first direction (e.g., the width direction of the cell), and spaced along the second direction (e.g., the length direction of the cell), forming a grid-like sub-electrode structure. The corresponding conductive layer mask is as
[0056] shown, and the conductive layer can be deposited at the positions corresponding to each sub-electrode in Figure 2 . The width and spacing of each sub-electrode are carefully designed to balance the light-shielding loss and electron collection efficiency. Figure 2 The metallization area of the first electrode is controlled within 3% - 10%, which means that the area occupied by the electrode on the back of the cell can be increased compared to conventional solar cells, thereby maximizing the electron collection efficiency, improving the fill factor and open-circuit voltage of the cell, and ultimately enhancing the conversion efficiency. Aluminum, as a highly conductive metal, can form a relatively large electrode area when used as the electrode material without significantly increasing the internal resistance of the cell. In addition, aluminum has a relatively low price and good adhesion to silicon, making it suitable for large-scale industrial production.
[0057] This design of the passivated contact crystalline silicon solar cell achieves a balance of high efficiency, low cost, and reliability through a refined layer structure and optimized electrode layout. The application of aluminum paste makes the electrode design more flexible and can better meet the requirements in different scenarios, which is an important part of modern high-performance solar cell technology.
[0058] According to an embodiment of the present disclosure, the width range of each sub-electrode is 20 μm - 50 μm. The conductive layer extends along the first direction and is spaced along the second direction. The width of the conductive layer is greater than or equal to the width of the sub-electrode and less than or equal to twice the width of the sub-electrode. Or, the width of the conductive layer is greater than or equal to the width of the sub-electrode and less than 50 μm.
[0059] In some embodiments, for example, n-type monocrystalline silicon is used as the substrate with a thickness of about 150 μm, which is the core of the cell energy conversion.
[0060] A thin layer of silicon dioxide (SiO2) with a thickness of about 2 nm is formed on the back of the silicon substrate as an electron tunneling layer, allowing electrons to flow from the n-type silicon to the subsequent doped layer.
[0061]
[0062] The first doped semiconductor layer is an n+-type doped layer with a thickness of approximately 150 nm. Phosphorus (P) is used as the dopant to form a low-resistance ohmic contact, facilitating the rapid transmission of electrons.
[0063] An Al2O3 layer with a thickness of approximately 2 nm is deposited on the first doped semiconductor layer, which serves as contact passivation, reducing surface recombination and improving the cell efficiency.
[0064] Above the first passivation layer, a conductive layer is formed using ITO or AZO with a thickness of approximately 10 nm, providing additional conductivity while maintaining high transparency.
[0065] The width of the TCO conductive layer is designed to be greater than or equal to the width of the sub-electrodes but not exceeding 50 μm, ensuring good electrical connection while minimizing the occupation of the space on the back of the cell and guaranteeing the passivation effect of the first passivation layer on the first doped semiconductor layer.
[0066] The first electrode is made of aluminum paste and includes a series of sub-electrodes extending along the first direction. These sub-electrodes are spaced apart along the second direction, forming a grid-like structure. The width range of the sub-electrodes is 20 μm to 50 μm. Such a design can effectively collect electrons while controlling the shading loss and maintaining the high efficiency of the cell. The metallization area of the first electrode is controlled within 3% to 10%. The relatively high metallization area ensures good electron collection efficiency.
[0067] This designed solar cell utilizes the optimized layout of passivated contacts and back electrodes to achieve the goal of high photoelectric conversion efficiency. By reasonably selecting the materials of each layer and finely adjusting the interlayer structure, the cell performance can be effectively improved while maintaining cost-effectiveness and production feasibility. The use of aluminum paste and the precise design of the sub-electrodes are the key elements to achieve this goal.
[0068] According to an embodiment of the present disclosure, the thickness range of the conductive layer is 10 nm to 30 nm, and the thickness range of the first doped semiconductor layer is 20 nm to 150 nm.
[0069] In some embodiments, the silicon substrate, such as an n-type single-crystalline silicon wafer with a thickness of about 200 μm, is the core of the cell, responsible for absorbing photons and generating electron-hole pairs.
[0070] An ultrathin SiO2 layer with a thickness of approximately 1.7 nanometers is formed on the back of the silicon substrate, allowing electrons to flow from the n-type silicon to the subsequent doped layer through the tunneling effect.
[0071] The first doped semiconductor layer is, for example, an n+-type doped layer with a thickness ranging from 20 nm to 150 nm, and phosphorus (P) is used as the dopant. This doped layer provides a low-resistance ohmic contact for facilitating the rapid transport of electrons. Meanwhile, its relatively wide thickness range can optimize the performance of the battery to adapt to different working conditions.
[0072] An Al2O3 layer with a thickness of approximately 2 nm is deposited on the first doped semiconductor layer, which plays a role in contact passivation, reducing surface recombination and improving the battery efficiency.
[0073] Above the first passivation layer, ITO or AZO is used as the conductive layer with a thickness between 10 nm and 30 nm. This TCO material provides additional conductivity while maintaining high transparency. The optimization of its thickness range can further improve the performance of the battery, especially the matching with the sub-electrodes, ensuring good electrical contact and minimizing the light-shielding effect.
[0074] The first electrode is made of, for example, aluminum paste and includes a series of sub-electrodes extending along the first direction. The width of the sub-electrodes is, for example, 35 μm, and they are spaced apart along the second direction, forming a grid-like structure. The metallization area of the first electrode is controlled at about 6%, ensuring good electron collection efficiency and minimal light-shielding loss.
[0075] This designed solar cell utilizes contact passivation technology and the optimized layout of the back electrode, combined with the precise thickness control of the first doped semiconductor layer and the TCO conductive layer, to achieve the dual goals of high photoelectric conversion efficiency and cost-effectiveness. The use of aluminum paste and the precise design of the sub-electrodes are the key elements to achieve this goal, and they also demonstrate the latest progress in modern solar cell technology in terms of performance optimization.
[0076] Figure 3 The structural diagram of a topcon solar cell according to an embodiment of the present disclosure is schematically shown.
[0077] According to an embodiment of the present disclosure, as Figure 3 shown, the solar cell may further include: a second doped semiconductor layer 7 disposed on the second side of the silicon substrate 1, and the second side is the opposite side of the first side. A second electrode 10 in contact with the second doped semiconductor layer 7, and the second electrode 10 is a silver electrode.
[0078] In some embodiments, in combination with the above embodiments, the structure of a TOPCon (Tunnel Oxide Passivated Contact) solar cell is introduced in detail, which includes different layers disposed on both sides of the silicon substrate, as described below:
[0079] The silicon substrate is, for example, an n-type single-crystalline silicon wafer with a thickness of about 140 μm, which is responsible for absorbing photons and generating electron-hole pairs.
[0080] An ultrathin SiO2 layer is formed on the back side (the first side) of the silicon substrate, with a thickness of approximately 1.8 nm, allowing electrons to flow from the n-type silicon to the subsequent doped layer through the tunneling effect.
[0081] The first doped semiconductor layer is, for example, an n+-type doped polysilicon layer with a thickness of, for example, 85 nm. Phosphorus (P) is used as the dopant, providing a low-resistance ohmic contact for the rapid transmission of electrons.
[0082] SiN is deposited on the first doped semiconductor layer x with a thickness of approximately 2 nm, which serves as a surface passivation layer, reducing surface recombination and improving the cell efficiency.
[0083] Located above the first doped semiconductor layer, ITO or AZO is locally used as the conductive layer with a thickness of about 25 nm, providing additional conductivity while maintaining high transparency.
[0084] The first electrode is made of, for example, aluminum paste and includes a series of sub-electrodes extending in the first direction. The width of the sub-electrodes is, for example, 30 μm, and they are spaced along the second direction, forming a grid-like structure. The metallization area of the first electrode is controlled at 10%, ensuring good electron collection efficiency and minimal light shielding loss.
[0085] The second doped semiconductor layer is, for example, a p+-type doped layer, which is arranged on the front side of the silicon substrate. The thickness range can be between 20 nm and 150 nm. Boron (B) is used as the dopant to form a good ohmic contact.
[0086] A passivation layer is deposited on the second doped semiconductor layer, and Al2O3 or SiN can be used x with a thickness of approximately 70 nm, which serves to reduce surface recombination and reflection.
[0087] The second antireflection layer 9 is located above the second passivation layer 8 and can be SiN x or SiO2 with a thickness between 70 nm and 100 nm. Its main function is to reduce the reflection of incident light and increase the light absorption rate.
[0088] The front electrode can be made of silver paste and is designed as a thin wire shape to reduce the occlusion of incident light while ensuring good electrical contact and current collection.
[0089] This designed TOPCon solar cell realizes comprehensive optimization from the back and front by respectively arranging layers with different functions on both sides of the silicon substrate. The passivation contact technology on the back and the antireflection layer design on the front, combined with the carefully designed electrode layout, jointly improve the photoelectric conversion efficiency of the cell.
[0090] Figure 4 Schematically shows a structural diagram of a topcon solar cell according to another embodiment of the present disclosure.
[0091] According to an embodiment of the present disclosure, as Figure 4 shown, the solar cell further includes, for example: a first anti-reflection layer 11 disposed on a side of the first passivation layer 4 away from the silicon substrate 1. Among them, the first electrode 5 completely penetrates through the first anti-reflection layer 11.
[0092] In some embodiments, the structure of a TOPCon solar cell is described in further detail. This time, the focus is on the addition of the first anti-reflection layer and how the first electrode passes through this layer. The following is the detailed structure combining all the layers:
[0093] The silicon substrate is, for example, an n-type single-crystalline silicon wafer with a thickness of about 180 μm.
[0094] The tunneling oxide layer is a SiO2 layer with a thickness of about 1.5 nm, allowing electrons to flow from the n-type silicon to the subsequent doped layer through the tunneling effect.
[0095] The first doped semiconductor layer is an n+-type doped layer with a thickness of about 50 nm, using phosphorus (P) as a dopant to provide a low-resistance ohmic contact.
[0096] The first passivation layer is, for example, an Al2O3 layer with a thickness of about 2 nm, which plays a role in contact passivation and reduces surface recombination.
[0097] The first anti-reflection layer is located above the first passivation layer and can use SiN x or SiO2, with a thickness between 70 nm and 100 nm, aiming to reduce the amount of light reflected from the back surface and further improve the light absorption efficiency.
[0098] The first electrode is, for example, made of aluminum paste and includes a series of sub-electrodes extending in the first direction. The width of the sub-electrodes is, for example, 50 μm, and they are spaced apart in the second direction to form a grid-like structure. The metallization area of the first electrode is controlled at 8%, and it completely penetrates through the first anti-reflection layer to ensure good contact with the first doped semiconductor layer.
[0099] The second doped semiconductor layer is a p+-type doped layer, disposed on the front surface of the silicon substrate, with a thickness of, for example, 100 nm, using boron (B) as a dopant to form a good ohmic contact.
[0100] The second passivation layer is, for example, an Al2O3 layer with a thickness of about 70 nm, which plays a role in reducing surface recombination and reflection.
[0101] The second anti-reflection layer is located above the second passivation layer and can be a layer of SiN xOr SiO2, with a thickness between 70 nm and 100 nm, whose main function is to reduce the reflection of incident light and increase the light absorption rate.
[0102] The front electrode, usually made of silver paste, is designed as a thin line to reduce the occlusion of incident light while ensuring good electrical contact and current collection.
[0103] This designed TOPCon solar cell demonstrates the innovation and complexity of modern high-performance solar cell technology by adding a first anti-reflection layer on the back of the silicon substrate and optimizing the layout and contact method of the first electrode. The careful design of each layer is to maximize the light absorption and conversion efficiency while reducing internal losses, ensuring the high conversion efficiency and long-term reliability of the battery.
[0104] Figure 5 Schematically shows the structural diagram of a back-contact solar cell according to an embodiment of the present disclosure.
[0105] According to an embodiment of the present disclosure, as Figure 5 shown, the solar cell further includes, for example: a third doped semiconductor layer 12 disposed on the side of the tunneling oxide layer 2 away from the silicon substrate 1. A third electrode 13 disposed on the side of the first passivation layer 4 away from the silicon substrate 1. A third passivation layer 14 disposed on the second side of the silicon substrate 1, where the second side is the opposite side of the first side. Among them, the third doped semiconductor layer 12 is disposed at an interval non-contact with the first doped semiconductor layer 3. The third electrode 13 passes through the first passivation layer 4, and a conductive layer 6 is disposed between the third electrode 13 and the third doped semiconductor layer 12, and the third electrode 13 is electrically connected to the third doped semiconductor layer 12 through the conductive layer 6.
[0106] In some embodiments, in combination with the above embodiments, the structure of a back-contact (BC) solar cell is described in detail, which includes additional components such as a third doped semiconductor layer, a third electrode, a third passivation layer, and a third anti-reflection layer. The following is a detailed structural description of all layers:
[0107] The silicon substrate is, for example, an n-type monocrystalline silicon wafer with a thickness of about 150 μm, which is responsible for absorbing photons and generating electron-hole pairs.
[0108] The tunneling oxide layer is, for example, a SiO2 layer with a thickness of about 1.5 nm, which allows electrons to flow from the n-type silicon to the subsequent doped layer through the tunneling effect.
[0109] The first doped semiconductor layer is an n+-type doped layer with a thickness of, for example, 100 nm, and phosphorus (P) is used as the dopant to provide a low-resistance ohmic contact.
[0110] The third doped semiconductor layer is a p+-type doped layer, which is disposed at a non-contact interval from the first doped semiconductor layer. Its thickness is, for example, 100 nm, and boron (B) is used as the dopant to form another low-resistance ohmic contact. The first doped semiconductor layer and the third doped semiconductor layer are disposed on the back surface, corresponding to n+-type and p+-type doping respectively, to form two independent low-resistance ohmic contact regions. The first passivation layer passivates these two doped layers, reduces surface recombination, and improves the battery efficiency.
[0111] The first passivation layer is, for example, an Al2O3 layer with a thickness of about 2 nm, which plays a role in surface passivation, reduces surface recombination, and the first doped semiconductor layer and the third doped semiconductor layer are adjacent to the first passivation layer.
[0112] The first antireflection layer is located above the first passivation layer, and SiN x or SiO2 can be used, with a thickness between 70 nm and 100 nm, which reduces the amount of light reflected from the back surface and further improves the light absorption efficiency.
[0113] The third electrode and the first electrode are made of aluminum paste, including a series of sub-electrodes extending along the first direction. The width range of the sub-electrodes is 20 μm to 50 μm, and they are spaced along the second direction to form a grid-like structure. The sum of the metallization areas of the third electrode and the first electrode is controlled between 3% and 10%. The third electrode passes through the first passivation layer, and a conductive layer is provided between the third electrode and the third doped semiconductor layer to ensure good electrical contact. The third electrode contacts the third doped semiconductor layer by passing through the first passivation layer, and the intermediate conductive layer ensures good electrical contact, while avoiding the problem of metal burning through the doped layer, improving the long-term stability and reliability of the battery. And it can avoid damaging the field passivation effect of the N-type first doped semiconductor layer.
[0114] A conductive layer is also provided between the third electrode and the third doped semiconductor layer. Transparent conductive oxides (TCOs) such as ITO or AZO are used, with a thickness between 10 nm and 30 nm, which provides additional conductivity while maintaining high transparency.
[0115] A passivation layer is deposited on the front surface of the silicon substrate. For example, SiN x is used, with a thickness of about 70 nm, which plays a role in reducing surface recombination and reflection.
[0116] The third antireflection layer 15 is located above the third passivation layer 14 and can be a layer of SiN x or SiO2, with a thickness between 70 nm and 100 nm. Its main function is to reduce the reflection of incident light and increase the light absorption rate.
[0117] Antireflection layers are provided on the front and back surfaces of the battery respectively to minimize light reflection, increase light absorption, and improve the photoelectric conversion efficiency of the battery.
[0118] This design of back-contact (BC) solar cells demonstrates a high level of integration and complexity of modern high-performance solar cell technology by setting up two independent doping, passivation, and electrode systems on the back of the silicon substrate, as well as antireflection layers on both the front and back. The careful design of each layer is to maximize the light absorption and conversion efficiency, while reducing internal losses, ensuring high conversion efficiency and long-term reliability of the cell. The cells with this structure can provide higher output power and more stable performance in practical applications and are suitable for various solar power generation systems.
[0119] According to an embodiment of the present disclosure, the silicon substrate is an n-type single-crystalline silicon or a p-type single-crystalline silicon.
[0120] In some embodiments, when using a p-type single-crystalline silicon as the silicon substrate for a TOPCon solar cell, the structure and function of the entire cell will be adjusted accordingly to adapt to the properties of p-type silicon. The following is a description of the structure of a TOPCon solar cell based on p-type single-crystalline silicon:
[0121] The silicon substrate is, for example, a p-type single-crystalline silicon wafer with a thickness between 150 μm and 200 μm, responsible for absorbing photons and generating electron-hole pairs.
[0122] The tunneling oxide layer is a SiO2 layer with a thickness of approximately 1.5 nm, allowing holes (but not electrons) to flow from the p-type silicon to the subsequent doping layer through the tunneling effect.
[0123] The first doped semiconductor layer is a p+-type doped layer with a thickness range of 20 nm to 150 nm, using boron (B) as a dopant, providing a low-resistance ohmic contact for the rapid transport of holes.
[0124] The first passivation layer is, for example, an Al2O3 layer with a thickness of approximately 2 nm, playing a role in surface passivation, reducing surface recombination, and improving the cell efficiency.
[0125] The first antireflection layer is located above the first passivation layer and can be a layer of SiN x or SiO2 with a thickness between 70 nm and 100 nm. Its main function is to reduce the reflection of incident light and increase the light absorption rate.
[0126] The first electrode is the back electrode, which can be made of aluminum paste or copper paste, including a series of sub-electrodes extending along the first direction. The width range of the sub-electrodes is 20 μm to 50 μm, and they are spaced along the second direction to form a grid-like structure, ensuring good hole collection efficiency and minimum shading loss.
[0127] The second doped semiconductor layer is an n+-type doped layer, which is disposed on the front surface of the silicon substrate. The thickness range is, for example, between 20 nm and 150 nm. Phosphorus (P) is used as the dopant to form a good ohmic contact.
[0128] A second passivation layer is deposited on the second doped semiconductor layer. SiN can be used. x The thickness is about 70 nm, which plays a role in reducing surface recombination and reflection.
[0129] The second antireflection layer 9 is located above the second passivation layer 8 and can be a layer of SiN x or SiO2. The thickness is between 70 nm and 100 nm, which reduces the amount of light reflected from the back surface and further improves the light absorption efficiency.
[0130] The second electrode is the front electrode, which can be made of silver paste and is designed to be in a thin line shape to reduce the blockage of incident light and ensure good electrical contact and current collection.
[0131] For the TOPCon solar cell using a p-type single-crystalline silicon as the substrate, through respectively disposing layers with different functions on the front and back surfaces of the silicon substrate, comprehensive optimization is achieved. The contact passivation technology and the antireflection layer design, combined with the p+-type doped layer and the first electrode layout on the back surface, jointly improve the photoelectric conversion efficiency of the cell. By precisely controlling the functions and material selections of each layer, the efficiency and stability of the cell can be further improved, which is applicable to various photovoltaic applications.
[0132] Figure 6 Schematically shows a flowchart of a method for manufacturing a solar cell according to an embodiment of the present disclosure.
[0133] In some embodiments, for the solar cell in the above embodiments, as Figure 6 shown, its manufacturing method, for example, may include the following steps:
[0134] (1) Provide an N-type single-crystalline silicon wafer, perform boron diffusion on the front surface to form a P+ layer and a relatively thick boron-silicon glass layer (100 - 150 nm), and the measured sheet resistance is about 300 Ω.
[0135] (2) By cleaning the P+ layer on the back surface and the edge of the N-type single-crystalline silicon wafer, retain the P+ layer and the relatively thick BSG (Back Surface Grading) on the front surface as a mask for subsequent processes.
[0136] (3) Preparation of the back passivation contact layer. First, obtain SiO x (1.5 - 2 nm) / n-poly layer (20 - 150 nm) on the back surface of the above silicon wafer through an LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) device. If prepared by LPCVD, further obtain the n-poly layer (i.e., the first doped semiconductor layer) through phosphorus diffusion. If using a PECVD device to prepare the n-poly layer, annealing is required afterwards to form an oxide layer with a thickness of 20 - 40 nm on its surface. The sheet resistance after diffusion is, for example, 30 - 60 ohm / sq.
[0137] (4) For the above silicon wafer, remove the front BSG through pickling with a chain device, and then enter a tank device to remove the poly on the front curvature of the silicon wafer with hot alkali and dry it.
[0138] (5) Grow aluminum oxide on the front of the above silicon wafer.
[0139] (6) For the above silicon wafer, deposit a layer of TCO with a thickness of 10 - 30 nm in a local area on the back using a TCO mask.
[0140] (7) Form a silicon nitride film on the front and back of the above silicon wafer.
[0141] (8) Print electrodes on the front and back, and after sintering, light injection, and LECO (Laser Enhanced Contact Optimization), the battery can be obtained. Among them, aluminum paste and copper paste are used for the back electrode.
[0142] The solar cell of this embodiment adopts a passivation contact structure. On the back, a metal contact area structure is formed by using the aluminum paste or copper paste solution, effectively reducing the single consumption of silver. At the same time, the poly layer is not affected by the burning through of the paste, so the poly layer can be significantly thinned, reducing the current loss caused by optical parasitic absorption.
[0143] Another aspect of the present disclosure provides a photovoltaic module, including: a plurality of solar cells as in any embodiment of the present disclosure; an encapsulation layer for covering the surfaces of the plurality of solar cells; a cover plate for covering the surface of the encapsulation layer facing away from the plurality of solar cells.
[0144] In some embodiments, for example, construct a photovoltaic module of a TOPCon solar cell based on an n-type silicon substrate. The following is a specific example of a photovoltaic module:
[0145] The cell string is formed by connecting a plurality of TOPCon solar cells of the n-type monocrystalline silicon substrate of the above-mentioned embodiments in series. Each cell is connected in series through connecting components such as welding strips or conductive adhesives to form a cell string, ensuring a continuous current path.
[0146] The encapsulation layer covers both sides of the battery string, and EVA (ethylene-vinyl acetate copolymer) or POE (polyolefin elastomer) can be used as the encapsulation material. The encapsulation layer not only provides physical protection, but also plays a role in waterproofing, dustproofing, and anti-ultraviolet aging. At the same time, it has a certain light transmittance, allowing sunlight to fully irradiate the battery surface.
[0147] The cover is located above the encapsulation layer and faces the sun. Tempered glass can be used as the material. The cover provides additional physical protection to prevent the external environment from damaging the battery string and encapsulation layer, while ensuring that the surface of the component is clean and flat, so that rain can slide off naturally and reduce dust accumulation.
[0148] This photovoltaic module based on TOPCon solar cells on n-type silicon substrates demonstrates the advancement and practicality of modern solar power generation systems through carefully designed cell strings, encapsulation layers and cover plates. Each module is composed of multiple high-efficiency battery cells. Through encapsulation and protection measures, the stable operation and high power generation efficiency of the module under various environmental conditions are ensured, which is an indispensable key component in the field of photovoltaic power generation.
[0149] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present disclosure. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to a specific order or hierarchy.
[0150] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. In addition, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual sizes, proportions, and actual positional relationships.
[0151] In the foregoing detailed description, various features are combined in a single embodiment to simplify the present disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the present disclosure is in a state less than the full features of the individual disclosed embodiments. Accordingly, the appended claims are hereby expressly incorporated into the detailed description, where each claim stands alone as a separate preferred embodiment of the present disclosure.
[0152] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined. Regarding the term "comprising" used in the specification or claims, the manner in which this word encompasses is similar to the term "including", as explained when "including," is used as a transitional word in the claims. Any use of the term "or" in the claims or the specification is intended to mean "non-exclusive or".
[0153] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present disclosure. It should be understood that the above description is only for the specific embodiments of the present disclosure and is not used to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure should be included within the protection scope of the present disclosure.
Claims
1. A solar cell, characterized in that, Comprising: A silicon substrate; A tunneling oxide layer disposed on the first side of the silicon substrate; A first doped semiconductor layer disposed on the side of the tunneling oxide layer away from the silicon substrate; A first passivation layer disposed on the side of the first doped semiconductor layer away from the silicon substrate; And A first electrode disposed on the side of the first passivation layer away from the silicon substrate; Wherein, the first electrode penetrates through the first passivation layer, a conductive layer is disposed between the first electrode and the first doped semiconductor layer, and the projected area of the conductive layer on the silicon substrate is smaller than the projected area of the first passivation layer on the silicon substrate; the first electrode is an aluminum electrode or a copper electrode; the material of the conductive layer is a transparent conductive oxide.
2. The solar cell according to claim 1, wherein The first doped semiconductor layer is an N-type doped semiconductor layer.
3. The solar cell according to claim 1, characterized in that, The first electrode includes a plurality of sub-electrodes extending along a first direction and spaced apart along a second direction; and The metallization area of the first electrode is 3% - 10%.
4. The solar cell according to claim 3, characterized in that, The width range of each sub-electrode is 20μm - 50μm; the conductive layer extends along the first direction and is spaced apart along the second direction; The width of the conductive layer is greater than or equal to the width of the sub-electrode and less than or equal to twice the width of the sub-electrode; or, the width of the conductive layer is greater than or equal to the width of the sub-electrode and less than 50μm.
5. The solar cell according to any one of claims 1 to 4, characterized in that, The thickness range of the conductive layer is 10nm - 30nm, and the thickness range of the first doped semiconductor layer is 20nm - 150nm.
6. The solar cell according to any one of claims 1 to 4, characterized in that, Further comprising: A second doped semiconductor layer disposed on the second side of the silicon substrate, the second side being the opposite side of the first side; A second electrode in contact with the second doped semiconductor layer, the second electrode being a silver electrode.
7. The solar cell according to any one of claims 1 to 4, characterized in that, Further comprising: A first antireflection layer disposed on the side of the first passivation layer away from the silicon substrate; Wherein, the first electrode completely penetrates through the first antireflection layer.
8. The solar cell according to any one of claims 1 to 4, characterized in that, Further comprising: A third doped semiconductor layer disposed on the side of the tunneling oxide layer away from the silicon substrate, the conductivity type of the third doped semiconductor layer being opposite to that of the first doped semiconductor layer; A third electrode disposed on the side of the first passivation layer away from the silicon substrate; A third passivation layer disposed on the second side of the silicon substrate, the second side being the opposite side of the first side; Wherein, the third doped semiconductor layer is disposed at an interval non-contact with the first doped semiconductor layer; The third electrode penetrates through the first passivation layer, and the conductive layer is disposed between the third electrode and the third doped semiconductor layer, and the third electrode is electrically connected to the third doped semiconductor layer through the conductive layer.
9. The solar cell according to claim 1, wherein The silicon substrate is an n-type single crystal silicon or a p-type single crystal silicon.
10. A photovoltaic module, characterized in that, Comprising: A plurality of solar cells as described in any one of claims 1 - 9; An encapsulation layer for covering the surfaces of the plurality of solar cells; A cover plate for covering the surface of the encapsulation layer facing away from the plurality of solar cells.