Photovoltaic cell and photovoltaic module

Abstract

The photovoltaic cell sheet comprises a silicon substrate, the silicon substrate comprises a light receiving surface and a backlight surface which are oppositely arranged, a metal area of the backlight surface is provided with a first tunneling passivation contact structure, the metal area and a non-metal area of the backlight surface are provided with second passivation structures, and the first tunneling passivation contact structure and the second passivation structure are arranged on the non-metal area of the backlight surface. The second passivation structures on the metal region are stacked on the first tunneling passivation contact structure, the second passivation structures stacked on the metal region and the non-metal region in the direction perpendicular to the backlight surface of the silicon substrate are equal in thickness, and the thickness of the stacked structure on the metal region is larger than that of the stacked structure on the non-metal region. According to the utility model, the tunneling passivation contact structure on the back non-metal area is removed or thinned, so that the passivation effect can be considered, parasitic absorption can be reduced, and the cell efficiency and the double-sided rate can be remarkably improved while the process window is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of photovoltaic cells, and particularly relates to a photovoltaic cell and a photovoltaic module. Background Art

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of photovoltaic cells in the domestic and international photovoltaic markets are constantly increasing. Industry manufacturers are focusing on the research and development of high-efficiency cells. TOPCon (Tunnel Oxide Passivated Contact) cells can improve the surface passivation performance of the cells, reduce the metal contact recombination current, and effectively increase the open-circuit voltage and short-circuit current of the cells by sequentially preparing an ultra-thin tunneling oxide layer and a doped polysilicon layer on the back of the silicon substrate. In recent years, the market share of TOPCon cells has risen rapidly and has gradually surpassed PERC cells to become the mainstream technology of photovoltaic cells.

[0003] The back of the TOPCon cell adopts a tunneling oxide layer and a doped polysilicon layer to form a tunneling passivation contact structure, and the cell efficiency has a significant gain. The thicker the thickness of the doped polysilicon on the back, the larger the window for resisting metal paste burn-through, but the higher the parasitic absorption. Therefore, one of the efficiency improvement solutions for TOPCon cells is the back Poly finger structure, which reduces or completely removes the thickness of the doped polysilicon in the non-metal area and reduces the parasitic absorption in the long wavelength band on the back. Therefore, it is necessary to control the thickness of the polysilicon in the metal area and the non-metal area.

[0004] If the doped polysilicon in the back metal area is too thin, the paste will penetrate the doped polysilicon during sintering, destroying the underlying tunneling oxide layer and resulting in poor passivation effect and low cell efficiency; if the doped polysilicon in the back non-metal area is too thick, the parasitic absorption is high and the cell efficiency is low; if the doped polysilicon in the non-metal area is too thin, the field passivation effect is poor and the cell efficiency is low. Currently, the thickness of the doped polysilicon layer on the back of mass-produced TOPCon cells is generally between 100 nm and 150 nm, and it is difficult to further reduce the thickness mainly due to the paste sintering window.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a photovoltaic cell and a photovoltaic module. Summary of the Utility Model

[0006] The purpose of the utility model is to provide a photovoltaic cell and a photovoltaic module, which can balance the passivation effect and reduce the parasitic absorption, and significantly improve the cell efficiency and bifaciality while improving the process window.

[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the utility model is as follows:

[0008] A photovoltaic cell, the photovoltaic cell comprising a silicon substrate, the silicon substrate comprising a light-receiving surface and a backlight surface disposed opposite to each other, a first tunneling passivation contact structure being provided on a metal region of the backlight surface, a second passivation structure being provided on the metal region and the non-metal region of the backlight surface, the second passivation structure on the metal region being stacked on top of the first tunneling passivation contact structure, wherein the thicknesses of the second passivation structures stacked in a direction perpendicular to the backlight surface of the silicon substrate on the metal region and the non-metal region are equal, and the thickness of the stacked structure on the metal region is greater than the thickness of the stacked structure on the non-metal region.

[0009] In one embodiment, the thickness of the stacked structure on the metal region is 0.01 μm to 8 μm greater than the thickness of the stacked structure on the non-metal region.

[0010] In one embodiment, the second passivation structure on the non-metal region is in contact with the backlight surface of the silicon substrate, the first tunneling passivation contact structure on the metal region includes a tunneling layer and a second doped layer stacked in sequence, a second electrode is provided on the metal region, and the second electrode is in contact with the second doped layer.

[0011] In one embodiment, the thickness of the stacked structure on the metal region is 0.05 μm to 8 μm or 3 μm to 6 μm greater than the thickness of the stacked structure on the non-metal region.

[0012] In one embodiment, the tunneling layer is any one or a combination of an oxide layer, a silicon oxynitride layer; and / or,

[0013] the thickness of the tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or,

[0014] the second doped layer is a doped polysilicon layer with a thickness of 1 nm to 150 nm or 50 nm to 100 nm; and / or,

[0015] the doping type of the second doped layer is the same as the doping type of the silicon substrate, and the surface doping concentration is 2E20 cm -3 ~3E21 cm -3 or 5E20 cm -3 ~2E21 cm -3 .

[0016] In one embodiment, the silicon substrate is recessed in the non-metal region.

[0017] In one embodiment, both the metal region and the non-metal region on the backlight surface of the silicon substrate are polished surfaces after pyramid-structured texture polishing, and the base size of the pyramid on the metal region is smaller than the base size of the pyramid on the non-metal region.

[0018] In one embodiment, the size of the tower base on the metal region is 3 μm to 20 μm, and the size of the tower base on the non-metal region is 3 μm to 50 μm; or,

[0019] the size of the tower base on the metal region is 8 μm to 15 μm, and the size of the tower base on the non-metal region is 15 μm to 30 μm.

[0020] In one embodiment, a second tunneling passivation contact structure is provided on the non-metal region, and the second passivation structure on the non-metal region is stacked on the second tunneling passivation contact structure, and the thickness of the second tunneling passivation contact structure is less than the thickness of the first tunneling passivation contact structure.

[0021] In one embodiment, the first tunneling passivation contact structure includes a tunneling layer stacked on the metal region and at least one doping layer, the second tunneling passivation contact structure includes a tunneling layer stacked on the metal region and at least one doping layer, and the total thickness of the doping layers on the metal region is greater than the total thickness of the doping layers on the non-metal region.

[0022] In one embodiment,

[0023] both the first tunneling passivation contact structure and the second tunneling passivation contact structure include a tunneling layer, an M1-layer second doping layer and an M1-layer barrier layer alternately stacked on the tunneling layer, and a third doping layer stacked on the outermost barrier layer. The thickness of the third doping layer in the second tunneling passivation contact structure is less than the thickness of the third doping layer in the first tunneling passivation contact structure, where M1 is a positive integer; or,

[0024] the first tunneling passivation contact structure includes a tunneling layer, an M2-layer second doping layer and an M2-layer barrier layer alternately stacked on the tunneling layer, and a third doping layer stacked on the outermost barrier layer. The second tunneling passivation contact structure includes a tunneling layer, an M2-layer second doping layer and an M2-1-layer barrier layer alternately stacked on the tunneling layer, where M2 is a positive integer.

[0025] In one embodiment, the height difference between the surfaces of the second passivation structure facing away from the silicon substrate on the metal region and the non-metal region is 0.01 μm to 0.153 μm or 0.048 μm to 0.102 μm.

[0026] In one embodiment, the tunneling layer is any one or a combination of silicon oxide layer, silicon oxynitride layer; and / or,

[0027] the thickness of the tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or,

[0028] the barrier layer is any one or a combination of silicon oxide layer, silicon carbide layer; and / or,

[0029] The thickness of the blocking layer is 0.5 nm to 3 nm or 1.5 nm to 2 nm; and / or,

[0030] The doping type of the second doping layer is the same as that of the silicon substrate, and the surface doping concentration is 1E20 cm -3 ~9E20 cm -3 or 3E20 cm -3 ~5E20 cm -3 ; and / or,

[0031] The doping type of the third doping layer is the same as that of the silicon substrate, and the surface doping concentration is 2E20 cm -3 ~3E21 cm -3 or 5E20 cm -3 ~2E21 cm -3 ; and / or,

[0032] The second doping layer is a doped polysilicon layer with a thickness of 1 nm to 100 nm or 1 nm to 50 nm; and / or,

[0033] The third doping layer is a doped polysilicon layer with a thickness of 1 nm to 150 nm or 50 nm to 100 nm; and / or,

[0034] The total thickness of the second doping layer and the third doping layer on the metal region is 50 nm to 150 nm or 60 nm to 100 nm.

[0035] In one embodiment, the metal region includes a plurality of first sub-regions that are parallel and equally spaced apart, and the non-metal region includes a plurality of second sub-regions that are parallel and equally spaced apart. The first sub-regions and the second sub-regions are alternately distributed, and the width of the first sub-region is 20 μm to 600 μm, and the width of the second sub-region is 100 μm to 800 μm.

[0036] In one embodiment, the second passivation structure includes one or a combination of multiple layers of silicon oxide layer, aluminum oxide layer, silicon nitride layer, and silicon oxynitride layer.

[0037] In one embodiment, the second passivation structure includes a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer stacked in sequence. Among them, the thickness of the silicon oxide layer is 0.1 nm to 3 nm, the thickness of the aluminum oxide layer is 3 nm to 10 nm or 4 nm to 8 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm or 70 nm to 90 nm; or,

[0038] The second passivation structure includes a silicon oxide layer and a silicon nitride layer stacked in sequence. Among them, the thickness of the silicon oxide layer is 1 nm to 30 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm or 70 nm to 90 nm.

[0039] In one embodiment, a first doping layer and a first electrode in contact with the first doping layer are provided on the light-receiving surface of the silicon substrate.

[0040] In one embodiment, the doping type of the first doping layer is opposite to that of the silicon substrate, and the surface doping concentration is 1E18 cm -3 ~5E19 cm -3 , and the thickness is 10 nm to 100 nm; and / or,

[0041] A first passivation structure is stacked on the first doping layer. The first passivation structure includes a stacked aluminum oxide layer and a silicon nitride layer in sequence. Among them, the thickness of the aluminum oxide layer is 3 nm to 10 nm or 4 nm to 8 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm or 70 nm to 90 nm.

[0042] The technical solution provided by another embodiment of the present utility model is as follows:

[0043] A photovoltaic module, which includes the above-mentioned photovoltaic cell.

[0044] Compared with the prior art, the present utility model has the following beneficial effects:

[0045] By removing or thinning the tunneling passivation contact structure on the back non-metal region, the present utility model can take into account the passivation effect and reduce parasitic absorption, significantly improve the cell efficiency and bifaciality while increasing the process window;

[0046] The chemical etching process can further polish the silicon substrate on the non-metal region, thereby increasing the height difference between the metal region and the non-metal region, and forming a larger-sized tower base on the non-metal region, thereby further improving the cell efficiency;

[0047] By introducing a battery back barrier layer, the change in the doping concentration of the doping layer can be effectively improved during the laser process, avoiding the damage of the tunneling layer, further improving the passivation effect. At the same time, the barrier layer has a certain blocking ability against the piercing of the back paste, which helps to reduce the total thickness of the back doping layer and improve the open-circuit voltage (Voc) of the battery. Description of the Drawings

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0049] Figure 1It is a schematic structural diagram of the photovoltaic cell in Embodiment 1 of the present utility model;

[0050] Figure 2 It is Figure 1 a partial structural diagram of the M position in

[0051] Figure 3 a schematic plan view of the backlight surface of the silicon substrate in Embodiment 1 of the present utility model;

[0052] Figure 4 a schematic plan view of the backlight surface and the second electrode in Embodiment 1 of the present utility model;

[0053] Figures 5a - 5j a process flow chart for preparing the photovoltaic cell in Embodiment 1 of the present utility model;

[0054] Figure 6 It is a schematic structural diagram of the photovoltaic cell in Embodiment 2 of the present utility model;

[0055] Figure 7 It is Figure 6 a partial structural diagram of the N position in

[0056] Figure 8 a schematic plan view of the backlight surface of the silicon substrate in Embodiment 3 of the present utility model;

[0057] Figure 9 It is Figure 8 a partial structural diagram of the A position in

[0058] Figures 10a - 10j a process flow chart for preparing the photovoltaic cell in Embodiment 3 of the present utility model;

[0059] Figure 11 It is a schematic structural diagram of the photovoltaic cell in Embodiment 4 of the present utility model;

[0060] Figure 12 It is Figure 11 a partial structural diagram of the B position in

[0061] Figure 13 It is a schematic structural diagram of the photovoltaic cell in Embodiment 5 of the present utility model;

[0062] Figure 14 It is Figure 13 a partial structural diagram of the C position in

[0063] Figure 15 It is a schematic structural diagram of the photovoltaic cell in Embodiment 6 of the present utility model;

[0064] Figure 16 It is Figure 15 a partial structural diagram of the D position in

[0065] Figure 17 SEM image of the pyramid-textured surface in Embodiment 1 of the present invention;

[0066] Figure 18 SEM image of the metal region on the backlight side of the silicon substrate in Embodiment 1 of the present invention;

[0067] Figure 19 SEM image of the non-metal region on the backlight side of the silicon substrate in Embodiment 1 of the present invention. Detailed implementation manners

[0068] In order to enable those skilled in the art to better understand the technical solutions in the present utility model, the technical solutions in the embodiments of the present utility model will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.

[0069] In the present utility model, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or simply indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or simply indicates that the first feature has a lower horizontal height than the second feature.

[0070] The present utility model discloses a photovoltaic cell. The photovoltaic cell includes a silicon substrate, the silicon substrate includes a light-receiving surface and a backlight surface arranged opposite to each other. A first tunneling passivation contact structure is provided on the metal region, and a second passivation structure is provided on the metal region and the non-metal region. The second passivation structure on the metal region is stacked on top of the first tunneling passivation contact structure. Among them, the thicknesses of the second passivation structures stacked in the direction perpendicular to the backlight surface of the silicon substrate on the metal region and the non-metal region are equal, and the thickness of the stacked structure on the metal region is greater than the thickness of the stacked structure on the non-metal region.

[0071] The present utility model also discloses a photovoltaic module, including the above-mentioned photovoltaic cell.

[0072] By removing or thinning the tunneling passivation contact structure on the back non-metal region of the present utility model, the passivation effect can be balanced while reducing parasitic absorption, significantly improving the cell efficiency and bifaciality while increasing the process window.

[0073] The present utility model will be further described below in conjunction with specific examples.

[0074] Embodiment 1:

[0075] Refer Figure 1 、 Figure 2 The structure diagram of the photovoltaic cell in this embodiment is shown. The photovoltaic cell is a TOPCon cell, including a silicon substrate 10. The silicon substrate 10 includes a light-receiving surface S1 and a backlight surface S2 arranged oppositely. The backlight surface S2 includes a metal region S21 and a non-metal region S22. The light-receiving surface S1 is the front of the silicon substrate 10, and the backlight surface S2 is the back of the silicon substrate 10.

[0076] The silicon substrate 10 in this embodiment is an N-type silicon substrate, with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0077] Further, a pyramid-shaped texture surface is formed on the light-receiving surface S1 of the silicon substrate 10 by alkaline texturing. The pyramid structure is in the shape of a frustum, such as a triangular frustum, a quadrangular frustum, etc. The pyramid size is defined as the average value of the width of the bottom of the frustum. For example, taking a quadrangular frustum as an example, the bottom is roughly square, and the pyramid size is the side length of this square.

[0078] In this embodiment, the pyramid size ranges from 0.5 μm to 3 μm. Refer Figure 17 The SEM image of the pyramid-shaped texture surface in this embodiment is shown. The three marked pyramid sizes are 2.67 μm, 2.60 μm, and 2.75 μm respectively, and the average value of all pyramid sizes is about 2.7 μm.

[0079] Both the metal region S21 and the non-metal region S22 of the backlight surface S2 are polished surfaces after polishing the pyramid-shaped texture surface. Among them, in this embodiment, the silicon substrate 10 is recessed on the non-metal region S22, and the base size of the pyramid on the metal region S21 is smaller than the base size of the pyramid on the non-metal region S22. During the alkaline polishing process, the pyramid-shaped texture surface on the back of the silicon substrate is polished to form a base, and the base is the pedestal left after polishing the pyramid-shaped texture surface. The shape of the base can be triangular, quadrilateral, etc. The base size is defined as the average value of the width of the base pattern. Taking a square base as an example, the base size is the average value of the side length of the square.

[0080] Among them, the base size formed during the alkaline polishing process will be larger than the pyramid size. The deeper the etching depth, the larger the base size. In this embodiment, the base size on the metal region S21 is 3 μm to 20 μm, preferably 8 μm to 15 μm, and the base size on the non-metal region S22 is 3 μm to 50 μm, preferably 15 μm to 30 μm.

[0081] Refer Figure 18The SEM image of the metal region S21 in this embodiment is shown. The marked tower base sizes in the figure are 11.37μm, 11.52μm, 11.44μm, 11.53μm, and 11.13μm respectively. The average size of the tower base on the metal region S21 is about 11.4μm. Refer Figure 19 The SEM image of the non-metal region S22 in this embodiment is shown. The etching depth of the non-metal region S22 is relatively deep, and the formed tower base size is relatively large. As shown in the figure, the marked tower base sizes are 20.30μm, 20.23μm, and 19.29μm respectively. The average size of the tower base on the non-metal region S22 is about 20μm.

[0082] In this embodiment, a first doped layer 11 is formed on the light-receiving surface S1 of the silicon substrate 10 by a diffusion process or a PECVD process. Exemplarily, the first doped layer 11 is a P-type doped layer (i.e., P+ emitter) formed by a boron doping process, and the doping concentration is 1E18cm -3 ~5E19cm -3 , the sheet resistance is 100Ω / sq~500Ω / sq, preferably 200Ω / sq~400Ω / sq.

[0083] Refer Figure 1 And in combination with Figure 2 As shown, a first tunneling passivation contact structure is provided on the metal region S21 of the backlight surface S2 of the silicon substrate 10 in this embodiment. The first tunneling passivation contact structure includes a tunneling layer 12 and a second doped layer 13 stacked in sequence.

[0084] Among them, the tunneling layer 12 is a silicon oxide (SiO X ) layer, a silicon oxynitride (SiO X N Y ) layer, or a combination of one or two of them. Preferably, it is a silicon oxide layer, with a thickness of 0.5nm~3nm, preferably 1.5nm~2.5nm; the second doped layer 13 is a phosphorus-doped polysilicon layer, and the doping concentration is 2E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 , and the thickness is 1nm~150nm, preferably 50nm~100nm.

[0085] Since the silicon substrate 10 in this embodiment is recessed on the non-metal region S22, there is a height difference between the metal region S21 and the non-metal region S22. Further, a tunneling layer 12 and a second doping layer 13 are stacked on the metal region S21. Therefore, the height difference H between the surface of the second doping layer 13 away from the silicon substrate and the backlight surface in the non-metal region S22 is the sum of the recessed depth of the non-metal region S22 and the thicknesses of the tunneling layer 12 and the second doping layer 13, and its value is 0.05 μm to 8 μm, preferably 3 μm to 6 μm. For example, in this embodiment, the sum of the thicknesses of the tunneling layer 12 and the second doping layer 13 is about 100 nm (0.1 μm), the height difference H is about 4 μm, and the recessed depth of the non-metal region S22 is about 3.9 μm.

[0086] In addition, a first passivation structure and a second passivation structure are respectively stacked on the light-receiving surface S1 and the backlight surface S2 of the silicon substrate in this embodiment.

[0087] Specifically, the first passivation structure is stacked on the first doping layer 11 and includes a silicon oxide (SiO X ) layer 21 and a silicon nitride (SiN X ) layer 31 stacked in sequence. Among them, the thickness of the silicon oxide layer 21 is 3 nm to 10 nm, preferably 4 nm to 8 nm, and the thickness of the silicon nitride layer 31 is 60 nm to 100 nm, preferably 70 nm to 90 nm;

[0088] The second passivation structure is stacked on the surface of the non-metal region S22 and the second doping layer 13 and includes one or a combination of multiple layers of a silicon oxide (SiO X ) layer, an aluminum oxide (AlO X ) layer, and a silicon nitride (SiO X ) layer. For example, in this embodiment, the second passivation structure includes a silicon oxide (SiO X ) layer 22 and a silicon nitride (SiO X ) layer 32 stacked in sequence. Among them, the thickness of the silicon oxide layer is 1 nm to 30 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0089] In the present utility model, the thicknesses of the second passivation structures stacked on the metal region S21 and the non-metal region S22 along the direction perpendicular to the backlight surface of the silicon substrate are equal (without considering the second passivation structures on the sidewalls of the first tunneling passivation contact structure). Therefore, the height difference between the surface of the second passivation structure facing away from the silicon substrate on the metal region S21 and the non-metal region S22 is also H, that is, 0.01 μm to 8 μm.

[0090] In another embodiment of the utility model, the second passivation structure includes a silicon oxide layer, an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the silicon oxide layer is 0.1nm~3nm, the thickness of the aluminum oxide layer is 3nm~10nm, preferably 4nm~8nm, and the thickness of the silicon nitride layer is 60nm~100nm, preferably 70nm~90nm.

[0091] In addition, the first electrode 41 in this embodiment is located on the light-receiving surface S1 of the silicon substrate 10 and contacts the first doping layer 11, and the second electrode 42 is located on the backlight surface S2 of the silicon substrate 10, specifically in the metal area S21 in the backlight surface S2, and contacts the second doping layer 13.

[0092] Ginseng Figure 3 As shown, the metal region S21 in this embodiment includes a plurality of first sub-regions 101 that are parallel and equally spaced, and the non-metal region S22 includes a plurality of second sub-regions 102 that are parallel and equally spaced, and the first sub-regions 101 and the second sub-regions 102 are staggered. The width of the first sub-region 101 is smaller than the width of the second sub-region 102, for example, the ratio of the widths of the two can be 1:(5-20), preferably, the width of the metal region S21 is 20μm-600μm, and the area of the metal region S21 accounts for about 10% of the area of the entire backlight surface S2.

[0093] Combination Figure 4 As shown, the second electrode 42 is a gate line electrode, which at least includes a plurality of parallel thin gate lines 421, and the width of the first sub-region 101 is greater than or equal to the width of the thin gate lines 421. Optionally, the second electrode 42 may also include a plurality of main gate lines (not shown) perpendicular to the thin gate lines 421.

[0094] Taking the 210TOPCon battery as an example, the battery size is 203.396±15mm, there are 230 fine grid lines 421, the width is 15μm to 100μm, and the spacing between adjacent fine grid lines is 0.907±0.015mm. The spacing between adjacent first sub-regions 101 is equal to the spacing between adjacent fine grid lines. A fine grid line 421 is distributed on each first sub-region 101, and the width of the first sub-region 101 is greater than the width of the fine grid line 421. The width of the first sub-region is 50μm to 150μm, such as the width of the fine grid line is 40μm, and the width of the first sub-region is 80μm.

[0095] The method for preparing the photovoltaic cell in this embodiment specifically includes the following steps:

[0096] 1. Double-sided velveting

[0097] Ginseng Figure 5aAs shown, a silicon substrate 10 is provided. The silicon substrate includes a light-receiving surface S1 and a backlight surface S2 which are oppositely arranged. The backlight surface S2 includes a metal region S21 and a non-metal region S22. The light-receiving surface S1 is the front surface of the silicon substrate 10, the backlight surface S2 is the back surface of the silicon substrate 10, the metal region S21 is the back metal region, and the non-metal region S22 is the back non-metal region.

[0098] In this embodiment, the silicon substrate 10 is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0099] Refer Figure 5b As shown, in this embodiment, the light-receiving surface S1 and the backlight surface S2 of the silicon substrate 10 are formed with a pyramidal texture by an alkaline texturing process, and the pyramid size is 0.5 μm to 3 μm.

[0100] 2. Boron diffusion

[0101] Refer Figure 5c As shown, a first doped layer (i.e., P+ emitter) 11 doped with P-type is formed on the light-receiving surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, diffusion is carried out by a boron source deposition and propulsion method in a high-temperature furnace tube. After diffusion, the doping concentration of the first doped layer is 1E18 cm -3 ~5E19 cm -3 , the sheet resistance is 100 Ω / sq to 500 Ω / sq, preferably 200 Ω / sq to 400 Ω / sq. In the boron diffusion process, a BSG (not shown) is formed on the backlight surface S2 of the silicon substrate.

[0102] In other embodiments, the first doped layer 11 can also be prepared by a PECVD process. First, a boron-doped amorphous silicon layer with a thickness of 10 nm to 100 nm is deposited on the light-receiving surface S1 by the PECVD process, and then a P-type doped polysilicon layer is formed after high-temperature oxidation annealing.

[0103] 3. Backside polishing

[0104] Refer Figure 5d As shown, the silicon substrate after boron diffusion is first passed through a single-sided chain equipment, the backside silicon oxide is removed by a hydrofluoric acid solution, and then the backside is subjected to alkaline polishing to remove the edge junction and backside plating (BSG), and finally cleaning is carried out.

[0105] During the alkaline polishing process, the pyramidal texture on the backside of the silicon substrate is polished to form a pedestal. The pedestal is the base left after polishing the pyramidal texture. In this embodiment, the pedestal size on the backside of the silicon substrate after alkaline polishing is 3 μm to 20 μm, preferably 8 μm to 15 μm.

[0106] 4. Preparation of backside tunneling passivation contact structure

[0107] As shown Figure 5e in FIG. 2, a tunneling layer 12, a second doping layer 13, and a mask layer 15 are sequentially stacked on the backlight surface S2.

[0108] Exemplarily, in this embodiment, a silicon oxide tunneling layer is first deposited on the back surface by PECVD process, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm;

[0109] Then, a phosphorus-doped amorphous silicon layer is deposited by PECVD process, with a doping concentration of 2E20 cm -3 ~3E21 cm -3 , preferably 5E20 cm -3 ~2E21 cm -3 , and a thickness of 1 nm to 150 nm, preferably 50 nm to 100 nm;

[0110] Finally, a mask layer 15 is deposited. The mask layer is any one or a combination of silicon oxide (SiO X ) layer, silicon oxynitride (SiO X N Y ) layer, and silicon nitride (SiN X ) layer, with a thickness of 1 nm to 100 nm, preferably 5 nm to 30 nm.

[0111] 5. Annealing

[0112] The silicon substrate with the tunneling passivation contact structure deposited on the back surface is placed in a high-temperature annealing furnace for high-temperature annealing. The annealing temperature is 850 °C to 950 °C, preferably 890 °C to 920 °C. During the annealing process, phosphorus is activated, thereby converting the doped amorphous silicon layer into a doped polycrystalline silicon layer.

[0113] 6. Laser patterning

[0114] As shown Figure 5f in FIG. 3, a laser process is used to pattern the mask layer 15 on the non-metal region (non-metal region) S22.

[0115] The energy required for laser patterning is affected by the thickness of the mask layer. In this embodiment, the laser can be a green picosecond laser or a violet picosecond laser. The laser power is 0.3 W to 25 W, preferably 0.3 W to 5 W. The laser frequency is 100 kHz to 1000 kHz, preferably 300 kHz to 600 kHz. The laser scanning rate is 10000 mm / s to 100000 mm / s, preferably 10000 mm / s to 60000 mm / s. The number of laser processing times is 1 to 100 times, preferably 1 to 10 times.

[0116] 7. Wet etching

[0117] Reference Figure 5g As shown, the second doping layer 13, the tunneling layer 12 and part of the silicon substrate 10 on the non-metal region S22 are removed by a wet etching process, and the tunneling layer 12 and the second doping layer 13 on the metal region S21 are retained.

[0118] First, hydrofluoric acid is used to remove the front and edge PSG.

[0119] Then, an alkali etching process is used to remove the front and edge overplating, as well as the tunneling layer 12, the second doping layer 13 and part of the silicon substrate 10 on the non-metal region S22. The etching solution consists of sodium hydroxide / potassium hydroxide + additive + pure water, the etching temperature is 50°C to 90°C, preferably 60°C to 80°C, the etching time is 100 s to 500 s, preferably 200 s to 300 s, and the pedestal size on the non-metal region of the silicon substrate after alkali etching is 3 μm to 50 μm, preferably 15 μm to 30 μm.

[0120] Finally, hydrofluoric acid is used to remove the front BSG and the mask layer 15 on the back metal region S21, and RCA cleaning is performed.

[0121] After the wet etching process, the height difference H between the surface of the second doping layer 13 away from the silicon substrate and the backlight surface in the non-metal region S22 is 0.05 μm to 8 μm, preferably 3 μm to 6 μm.

[0122] 8. Preparation of the first passivation structure

[0123] Reference Figure 5h As shown, first, an alumina layer 21 with a thickness of 3 nm to 10 nm, preferably 4 nm to 8 nm, is deposited on the light-receiving surface by an ALD process, and then a silicon nitride layer 31 with a thickness of 60 nm to 100 nm, preferably 70 nm to 90 nm, is deposited on the surface of the alumina by a PECVD process.

[0124] 9. Preparation of the second passivation structure

[0125] Reference Figure 5i As shown, first, a silicon oxide layer 22 and a silicon nitride layer 32 are deposited on the non-metal region and the surface of the second doping layer by a PECVD process. The thickness of the silicon oxide layer 22 is 0.1 nm to 3 nm, and the thickness of the silicon nitride layer 32 is 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0126] In other embodiments, it is also possible to first deposit a silicon oxide layer and an aluminum oxide layer on the non-metal region S22 and the surface of the second doping layer 13 by ALD process. During the deposition of the silicon oxide layer, H2O is introduced, the deposition temperature is 180°C to 300°C, and the thickness is 0.1nm to 3nm. During the deposition of the aluminum oxide layer, TMA and H2O are introduced, the deposition temperature is 180°C to 300°C, and the thickness is 3nm to 10nm, preferably 4nm to 8nm. Then, a silicon nitride layer is deposited on the surface of the aluminum oxide by PECVD process, and the thickness is 60nm to 100nm, preferably 70nm to 90nm.

[0127] It should be understood that in this embodiment, when the second passivation structure is prepared on the surface of the non-metal region S22 and the second doping layer 13, the second passivation structure will be formed synchronously on the side walls of the tunneling layer 12 and the second doping layer 13 during the deposition process. The thickness of the second passivation structure on the side walls (about 90nm) is much smaller than the width of the tunneling layer 12 and the second doping layer 13 (20μm to 600μm).

[0128] 10. Printing metal electrodes

[0129] As shown in Figure 5j , the first electrode 41 and the second electrode 42 are printed on the front and back surfaces respectively by screen printing process, and then sintering and optical injection or electrical injection treatment are carried out to form an ohmic contact.

[0130] The first electrode 41 and the second electrode 42 are grid line electrodes in the prior art, and usually include main grid lines and fine grid lines. It is worth noting that since the fine grid lines in the second electrode 42 need to be printed on the metal region, the width of the first sub-region needs to be greater than the width of the fine grid lines in the second electrode 42, so that the alignment of the fine grid lines can be achieved.

[0131] By the above steps, the TOPCon battery can be prepared, and finally the battery wafers are tested, sorted and stored in the warehouse.

[0132] Embodiment 2:

[0133] As shown in Figure 6 , Figure 7 , the structure diagram of the photovoltaic cell wafer in this embodiment is shown. The structure and preparation process of the photovoltaic cell wafer in this embodiment are substantially the same as those in the embodiment, except that:

[0134] In this embodiment, the metal region S21 and the non-metal region S22 on the backlight surface S2 of the silicon substrate 10 are flush with each other, and the tower base sizes of both regions are 3 μm to 20 μm, preferably 8 μm to 15 μm. Thus, the height difference between the surface of the second doping layer 13 away from the silicon substrate and the backlight surface in the non-metal region S22 is the height difference between the side surface of the second passivation structure away from the silicon substrate on the metal region S21 and the non-metal region S22, that is, the sum of the thicknesses of the tunneling layer 12 and the second doping layer 13, and its value is preferably 0.05 μm to 0.1 μm.

[0135] Correspondingly, in the preparation method of the photovoltaic cell in this embodiment, in the alkali etching process of the wet etching process, by controlling the process parameters, only the second doping layer 13 on the non-metal region S22 is removed, and the silicon substrate 10 is not removed. In addition, when the mask layer is removed by hydrofluoric acid, the tunneling layer 12 on the non-metal region S22 is removed synchronously.

[0136] Embodiment 3:

[0137] Refer Figure 8 、 Figure 9 As shown, it is a schematic structural diagram of the photovoltaic cell in this embodiment. The photovoltaic cell is a TOPCon cell. Among them, the structure of the silicon substrate 10 and its light-receiving surface S1 (i.e., the front surface) is exactly the same as that in the embodiment, and will not be elaborated here.

[0138] Different from Embodiment 1, in this embodiment, a first tunneling passivation contact structure and a second tunneling passivation contact structure are respectively provided on the metal region S21 and the non-metal region S22 on the backlight surface S2 of the silicon substrate 10.

[0139] The first tunneling passivation contact structure on the metal region S21 includes a tunneling layer 12, a layer of second doping layer 131, a layer of barrier layer 14, and a third doping layer 132 stacked in sequence. Specifically, the tunneling layer 12 is a layer of silicon oxide (SiO X ) or a layer of silicon oxynitride (SiO X N Y ) or a combination of one or two of them, preferably a silicon oxide layer, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm; the barrier layer 14 is a layer of silicon oxide (SiO X ) or a layer of silicon carbide, or a combination of one or two of them, preferably a layer of silicon oxide (SiO X ), with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2 nm.

[0140] In this embodiment, the doping types of the second doping layer 131 and the third doping layer 132 are the same as that of the silicon substrate. Preferably, the surface doping concentration of the third doping layer 132 is greater than that of the second doping layer 131. At the same time, the thickness of the third doping layer 132 is greater than that of the second doping layer 131, and the total thickness of the second doping layer 131 and the third doping layer 132 is 50 nm to 150 nm, preferably 60 nm to 100 nm.

[0141] Exemplarily, in this embodiment, the second doping layer 131 is a phosphorus-doped polysilicon layer with a surface doping concentration of 1E20 cm -3 ~9E20 cm -3 , preferably 3E20 cm -3 ~5E20 cm -3 , and the thickness is 1 nm to 100 nm, preferably 1 nm to 50 nm; the third doping layer 132 is a phosphorus-doped polysilicon layer with a surface doping concentration of 2E20 cm -3 ~3E21 cm -3 , preferably 5E20 cm -3 ~2E21 cm -3 , and the thickness is 1 nm to 150 nm, preferably 50 nm to 100 nm.

[0142] The second tunneling passivation contact structure above the non-metal region S22 includes a tunneling layer 12 and a second doping layer 131 stacked in sequence. The tunneling layer 12 and the second doping layer 131 are exactly the same as the tunneling layer 12 and the second doping layer 131 on the metal region S21, and will not be elaborated here.

[0143] In this embodiment, a first passivation structure and a second passivation structure are respectively stacked on the light-receiving surface S1 and the backlight surface S2 of the silicon substrate 10. The first passivation structure and the second passivation structure are exactly the same as those in Embodiment 1, and will not be elaborated here.

[0144] In addition, the first electrode 41 in this embodiment is located on the light-receiving surface S1 of the silicon substrate 10 and is in contact with the first doping layer 11. The second electrode 42 is located on the backlight surface S2 of the silicon substrate 10, specifically in the metal region S21 of the backlight surface S2, and is in contact with the third doping layer 132.

[0145] Since in this embodiment, the metal region S21 and the non-metal region S22 are respectively provided with a first tunneling passivation contact structure and a second tunneling passivation contact structure, and the heights of the two tunneling passivation contact structures are different, the height difference H between the metal region S21 and the non-metal region S22 (the surface of the third doping layer 132 away from the silicon substrate on the metal region S21 and the surface of the second doping layer 131 away from the silicon substrate on the non-metal region S22) is the height difference of the surface of the second passivation structure away from the silicon substrate on the metal region S21 and the non-metal region S22, that is, the sum of the thicknesses of the third doping layer 132 and the blocking layer 14, and its value is 0.01 μm to 0.153 μm, that is, 10 nm to 153 nm, preferably 0.048 μm to 0.102 μm, that is, 48 nm to 102 nm. In this embodiment, when the thickness of the blocking layer 14 is 2 nm and the thickness of the third doping layer 132 is 98 nm, the height difference H is 100 nm.

[0146] In this embodiment, the preparation method of the photovoltaic cell sheet specifically includes the following steps:

[0147] 1. Double-sided texturing

[0148] Refer Figure 10a As shown, a silicon substrate 10 is provided. The silicon substrate includes a light-receiving surface S1 and a backlight surface S2 arranged oppositely. The backlight surface S2 includes a metal region S21 and a non-metal region S22. The light-receiving surface S1 is the front surface of the silicon substrate 10, and the backlight surface S2 is the back surface of the silicon substrate 10.

[0149] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0150] Refer Figure 10b As shown, in this embodiment, the light-receiving surface S1 and the backlight surface S2 of the silicon substrate 10 are formed with a pyramid-structured suede surface through an alkali texturing process, and the pyramid size is 0.5 μm to 3 μm.

[0151] 2. Boron diffusion

[0152] Refer Figure 10c As shown, a P-type doped first doping layer (i.e., P+ emitter) 11 is formed on the light-receiving surface S1 of the silicon substrate 10 through a boron diffusion process. Specifically, the diffusion is carried out in a high-temperature furnace tube by using a boron source deposition and propulsion method. After diffusion, the doping concentration of the first doping layer is 1E18 cm -3 ~5E19 cm -3 , and the sheet resistance is 100 Ω / sq to 500 Ω / sq, preferably 200 Ω / sq to 400 Ω / sq. In the boron diffusion process, a BSG (not shown) is formed on the backlight surface S2 of the silicon substrate.

[0153] In other embodiments, the first doping layer 11 can also be prepared by PECVD process. First, a boron-doped amorphous silicon layer with a thickness of 10 nm to 100 nm is deposited on the light-receiving surface S1 by PECVD process, and then a P-type doped polysilicon layer is formed after high-temperature oxidation annealing.

[0154] 3. Backside polishing

[0155] As Figure 10d shown, the silicon substrate after boron diffusion is first passed through a single-sided chain equipment, the backside silicon oxide is removed by hydrofluoric acid solution, then the backside is polished with alkali to remove the edge junction and backside plating (BSG), and finally it is cleaned.

[0156] During the alkali polishing process, the pyramid-shaped texture on the backside of the silicon substrate is polished to form a pedestal, which is the pedestal left after polishing the pyramid-shaped texture. In this embodiment, the size of the pedestal on the backside of the silicon substrate after alkali polishing is 3 μm to 20 μm, preferably 8 μm to 15 μm.

[0157] 4. Preparation of backside tunneling passivation contact structure

[0158] As Figure 10e shown, a tunneling layer 12, a second doping layer 131, a barrier layer 14, a third doping layer 132 and a mask layer 15 are sequentially stacked on the backlight surface S2.

[0159] Exemplarily, in this embodiment, a silicon oxide tunneling layer with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm, is deposited on the backside by PECVD process;

[0160] Then a phosphorus-doped amorphous silicon layer is deposited by PECVD process, with a surface doping concentration of 1E20 cm -3 ~9E20 cm -3 , preferably 3E20 cm -3 ~5E20 cm -3 , and a thickness of 1 nm to 100 nm, preferably 1 nm to 50 nm;

[0161] Subsequently, a silicon oxide barrier layer with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2 nm, is deposited by PECVD process;

[0162] Then a phosphorus-doped amorphous silicon layer is deposited by PECVD process, with a surface doping concentration of 2E20 cm -3 ~3E21 cm -3 , preferably 5E20 cm -3 ~2E21 cm -3 , and a thickness of 1 nm to 150 nm, preferably 50 nm to 100 nm;

[0163] Finally, deposit a mask layer, which is any one or a combination of multiple layers of silicon oxide (SiO X ), silicon oxynitride (SiO X N Y ), and silicon nitride (SiN X ). The thickness is 1 nm to 100 nm, preferably 5 nm to 30 nm.

[0164] 5. Annealing

[0165] Place the silicon substrate with the tunneling passivation contact structure deposited on the back surface in a high-temperature annealing furnace for high-temperature annealing. The annealing temperature is 850 °C to 950 °C, preferably 890 °C to 920 °C. During the annealing process, phosphorus is activated, thereby converting the doped amorphous silicon layer into a doped polycrystalline silicon layer.

[0166] 6. Laser opening of the mask

[0167] As shown in the reference Figure 10f , use a laser process to perform pattern opening of the mask layer 15 on the non-metal region S22.

[0168] The energy required for laser opening of the mask is affected by the thickness of the mask layer. In this embodiment, the laser can be a green picosecond laser or a violet picosecond laser. The laser power is 0.3 W to 25 W, preferably 0.3 W to 5 W. The laser frequency is 100 kHz to 1000 kHz, preferably 300 kHz to 600 kHz. The laser scanning rate is 10,000 mm / s to 100,000 mm / s, preferably 10,000 mm / s to 60,000 mm / s. The number of laser processing times is 1 to 100 times, preferably 1 to 10 times.

[0169] 7. Wet etching

[0170] As shown in the reference Figure 10g , use a wet etching process to remove the third doped layer 132 and the barrier layer 14 on the non-metal region S22, and retain the third doped layer 132 and the barrier layer 14 on the metal region S21.

[0171] First, use hydrofluoric acid to remove the front surface and the edge PSG;

[0172] Then, use an alkali etching process to remove the front surface and the edge plating, as well as the third doped layer 132 on the non-metal region S22. The etching solution composition is sodium hydroxide / potassium hydroxide + additive + pure water;

[0173] Finally, use hydrofluoric acid to remove the front surface BSG and the mask layer on the back metal region S21 and the barrier layer 14 on the non-metal region S22, and perform RCA cleaning.

[0174] After the wet etching process, the height difference H between the surface of the third doping layer 132 away from the silicon substrate in the metal region S21 and the surface of the second doping layer 131 away from the silicon substrate in the non-metal region S22 is 0.01 μm to 0.153 μm, that is, 10 nm to 153 nm.

[0175] 8. Preparation of the first passivation structure

[0176] As shown in Figure 10h , first, an aluminum oxide layer 21 with a thickness of 3 nm to 10 nm, preferably 4 nm to 8 nm, is deposited on the light-receiving surface by ALD process, and then a silicon nitride layer 31 with a thickness of 60 nm to 100 nm, preferably 70 nm to 90 nm, is deposited on the surface of the aluminum oxide by PECVD process.

[0177] 9. Preparation of the second passivation structure

[0178] As shown in Figure 10i , first, a silicon oxide layer 22 and a silicon nitride layer 32 are deposited on the surfaces of the metal region S21 and the non-metal region S22 by PECVD process. The thickness of the silicon oxide layer 22 is 0.1 nm to 3 nm, and the thickness of the silicon nitride layer 32 is 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0179] In other embodiments, a silicon oxide layer and an aluminum oxide layer can also be deposited on the surfaces of the metal region S21 and the non-metal region S22 by ALD process. During the deposition of the silicon oxide layer, H2O is introduced, the deposition temperature is 180 °C to 300 °C, and the thickness is 0.1 nm to 3 nm. During the deposition of the aluminum oxide layer, TMA and H2O are introduced, the deposition temperature is 180 °C to 300 °C, and the thickness is 3 nm to 10 nm, preferably 4 nm to 8 nm. Then, a silicon nitride layer with a thickness of 60 nm to 100 nm, preferably 70 nm to 90 nm, is deposited on the surface of the aluminum oxide by PECVD process.

[0180] It should be understood that in this embodiment, when the second passivation structure is prepared on the surfaces of the metal region S21 and the non-metal region S22, the second passivation structure will be formed synchronously on the sidewalls of the first tunneling passivation contact structure. The thickness of the second passivation structure on the sidewalls (about 90 nm) is much smaller than the width of the first tunneling passivation contact structure (20 μm to 600 μm).

[0181] 10. Printing metal electrodes

[0182] As shown in Figure 10j , the first electrode 41 and the second electrode 42 are printed on the front and back surfaces respectively by screen printing process, and then sintering and optical injection or electrical injection treatment are carried out to form ohmic contacts.

[0183] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, usually including main gate lines and fine gate lines. It should be noted that since the fine gate lines in the second electrode 42 need to be printed on the metal area, the width of the first sub-region needs to be greater than the width of the fine gate lines in the second electrode 42, so that the alignment of the fine gate lines can be achieved.

[0184] Through the above steps, the TOPCon battery can be prepared, and finally the battery wafers are tested, sorted and stored in the warehouse.

[0185] Example 4:

[0186] Refer Figure 11 And in combination with Figure 12 As shown, the photovoltaic cell wafer in this embodiment is substantially the same as that in Example 3. The difference is that on the non-metal area S22 of the backlight surface S2 of the silicon substrate 10 in this embodiment, a tunneling layer 12, a second doping layer 131 and a blocking layer 14, and a third doping layer 132' are sequentially stacked. The tunneling layer 12, the second doping layer 131, and the blocking layer 14 on the non-metal area S22 are exactly the same as those on the metal area S21. The thickness of the third doping layer 132' is less than the thickness of the third doping layer 132.

[0187] The preparation method of the photovoltaic cell wafer in this embodiment is also substantially the same as that in Example 3. The difference is that the 7th wet etching step is different. In this embodiment, an alkaline etching process is used to remove part of the third doping layer on the non-metal area S22 and the mask layer on the metal area S21, and the third doping layer 132 on the metal area S21 is retained. By controlling the parameters of the alkaline etching process, the third doping layer on the non-metal area S22 is thinned instead of being completely removed.

[0188] In this embodiment, since part of the third doping layer 132' on the non-metal area S22 is retained, when the pickling process is carried out, the acid solution will not corrode the blocking layer 14 on the non-metal area S22. Therefore, the blocking layer 14 and part of the third doping layer 132' are retained on the non-metal area.

[0189] Corresponding to the thickness range of the blocking layer 14 and the third doping layer 132 in Example 3, the height difference H between the metal area S21 and the non-metal area S22 is the height difference between the third doping layers 132 and 132', and its value is less than the thickness of the third doping layer 132, which is 0.01 μm to 0.149 μm, that is, 10 nm to 149 nm, preferably 0.05 μm to 0.09 μm, that is, 50 nm to 90 nm.

[0190] Exemplarily, in this embodiment, the thickness of the barrier layer 14 on the metal region S21 is about 2 nm, the thickness of the third doped layer 132 is 100 nm, and the thickness of the remaining side third doped layer 132' on the non-metal region S22 is about 40 nm. Then, the height difference between the metal region S21 and the non-metal region S22 is about 60 nm (i.e., 0.06 μm).

[0191] Example 5:

[0192] Refer Figure 13 and combine with Figure 14 As shown, the photovoltaic cell in this embodiment is substantially the same as that in Example 3, except that in this embodiment, an alternating stack of a second doped layer 131 and a barrier layer 14 is provided on the tunneling layer 11 of the backlight surface S2 of the silicon substrate 10.

[0193] Specifically, in this embodiment, a tunneling layer 12, a second doped layer 131, a barrier layer 14, a second doped layer 131, a barrier layer 14, and a third doped layer 132 are sequentially stacked on the metal region S21 of the backlight surface S2 of the silicon substrate 10. On the non-metal region S22 of the backlight surface S2 of the silicon substrate 10, a tunneling layer 12, a second doped layer 131, a barrier layer 14, and a second doped layer 131 are sequentially stacked.

[0194] The preparation method of the photovoltaic cell in this embodiment is also substantially the same as that in Example 3, except that the wet etching step in the 7th step is different. In this embodiment, the third doped layer 132 on the non-metal region S22 is removed by alkali etching, and the outermost barrier layer 14 on the non-metal region S22 and the mask layer on the metal region S21 are removed by an acid solution.

[0195] Similar to Example 3, in this embodiment, the height difference H between the metal region S21 and the non-metal region S22 depends on the thickness ranges of the third doped layer 132 and the outermost barrier layer 14, which will not be elaborated here.

[0196] Example 6:

[0197] Refer Figure 15 and combine with Figure 16 As shown, the photovoltaic cell in this embodiment is substantially the same as that in Example 5, except that in this embodiment, a tunneling layer 12, a second doped layer 131, a barrier layer 14, a second doped layer 131, a barrier layer 14, and a third doped layer 132' are sequentially stacked on the non-metal region S22 of the backlight surface S2 of the silicon substrate 10, and the thickness of the third doped layer 132' is less than the thickness of the third doped layer 132 on the metal region S21.

[0198] The preparation method of the photovoltaic cell in this embodiment is also roughly the same as that in Embodiment 5, except that the wet etching step in the 7th step is different. In this embodiment, an alkali etching process is used to remove part of the third doping layer on the non-metal region S22 and the mask layer on the metal region S21, and the third doping layer 132 on the metal region S21 is retained. By controlling the parameters of the alkali etching process, the third doping layer on the non-metal region S22 is thinned instead of being completely removed.

[0199] In this embodiment, since part of the third doping layer 132' on the non-metal region S22 is retained, when the pickling process is carried out, the acid solution will not corrode the barrier layer 14 on the non-metal region S22. Therefore, the barrier layer 14 and part of the third doping layer 132' are retained on the non-metal region.

[0200] Similar to Embodiment 4, the height difference H between the metal region S21 and the non-metal region S22 in this embodiment depends on the thickness ranges of the third doping layer 132 and the outermost barrier layer 14, which will not be elaborated here.

[0201] It should be understood that the number of the second doping layer and the barrier layer is not limited to the number in the above embodiments, where:

[0202] For the solution of thinning the outermost third doping layer in the non-metal region, both the metal region and the non-metal region include a tunneling layer, an M1-layer second doping layer and an M1-layer barrier layer alternately stacked on the tunneling layer, and a third doping layer stacked on the outermost barrier layer, where M1 is a positive integer;

[0203] For the solution of removing the outermost third doping layer in the non-metal region, the metal region includes a tunneling layer, an M2-layer second doping layer and an M2-layer barrier layer alternately stacked on the tunneling layer, and a third doping layer stacked on the outermost barrier layer, and the non-metal region includes a tunneling layer, an M2-1-layer second doping layer and an M2-1-layer barrier layer alternately stacked on the tunneling layer, where M2 is a positive integer.

[0204] Examples of other embodiments with different numbers of the second doping layer and the barrier layer will not be elaborated one by one here.

[0205] Based on the existing TOPCon cell structure, the present utility model deposits a tunneling passivation contact structure and a mask layer on the back, then performs patterning and film opening on the non-metal region through a laser process, and then removes or thins the tunneling passivation contact structure on the non-metal region through a wet etching process, providing a new solution idea for improving the efficiency of TOPCon cells.

[0206] The main deposition methods of polycrystalline silicon are LPCVD and PECVD. Considering production capacity and the cost of quartz components, PECVD is more suitable for mass production. However, compared with LPCVD, the mask on the outer layer of PE Poly requires higher energy to be opened. The laser process can remove the mask in the non-metal area and the polycrystalline silicon below it. However, as the laser power increases, the degree to which the back mask is opened changes from completely unable to be opened → the mask structure becomes loose → the mask is completely vaporized → the mask + part of the polycrystalline silicon is vaporized. When the power increases to a certain level, it will damage the silicon substrate, thereby reducing the battery efficiency.

[0207] The present utility model removes the mask layer on the back non-metal area through the laser process, and then removes or thins the tunneling passivation contact structure on the back non-metal area through the chemical etching process, which can ensure that the silicon substrate is not damaged, and the tunneling passivation contact structure on the metal area is not affected. It can balance the passivation effect and reduce parasitic absorption, and significantly improve the battery efficiency and bifaciality while increasing the process window;

[0208] In Example 1, the chemical etching process can further polish the silicon substrate in the non-metal area, thereby increasing the height difference between the metal area and the non-metal area, and forming a larger-sized tower base in the non-metal area, thereby further improving the battery efficiency;

[0209] In Examples 3 - 6, through the introduction of the battery back barrier layer, the change in the doping concentration of the doping layer can be effectively improved during the laser process, avoiding the damage of the tunneling layer, and further improving the passivation effect. At the same time, the barrier layer has a certain blocking ability against the penetration of the back paste, which helps to reduce the total thickness of the back doping layer and improve the open-circuit voltage (Voc) of the battery.

[0210] After testing, compared with directly removing the second doping layer and the tunneling layer on the non-metal area by laser, the efficiency of the photovoltaic cell in the present utility model can be increased by more than 0.15%.

[0211] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present utility model. Any reference signs in the claims should not be regarded as limiting the claimed rights.

[0212] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment contains only one independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A photovoltaic cell, characterized in that, The photovoltaic cell includes a silicon substrate, the silicon substrate includes a light-receiving surface and a backlight surface which are oppositely arranged, a first tunneling passivation contact structure is provided on the metal area of the backlight surface, and a second passivation structure is provided on the metal area and the non-metal area of the backlight surface. The second passivation structure on the metal area is stacked on the first tunneling passivation contact structure. Among them, the thicknesses of the second passivation structures stacked in the direction perpendicular to the backlight surface of the silicon substrate on the metal area and the non-metal area are equal, and the thickness of the stacked structure on the metal area is greater than the thickness of the stacked structure on the non-metal area.

2. The photovoltaic cell according to claim 1, wherein, The thickness of the stacked structure on the metal area is 0.01 μm to 8 μm greater than the thickness of the stacked structure on the non-metal area.

3. The photovoltaic cell according to claim 1, wherein, The second passivation structure on the non-metal area is in contact with the backlight surface of the silicon substrate. The first tunneling passivation contact structure on the metal area includes a tunneling layer and a second doping layer stacked in sequence. A second electrode is provided on the metal area, and the second electrode is in contact with the second doping layer.

4. The photovoltaic cell according to claim 2, wherein The thickness of the stacked structure on the metal area is 0.05 μm to 8 μm or 3 μm to 6 μm greater than the thickness of the stacked structure on the non-metal area.

5. The photovoltaic cell according to claim 3, characterized in that The tunneling layer is any one or a combination of silicon oxide layer, silicon oxynitride layer; and / or, The thickness of the tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or, The second doping layer is a doped polysilicon layer with a thickness of 1 nm to 150 nm or 50 nm to 100 nm; and / or, The doping type of the second doping layer is the same as that of the silicon substrate, and the surface doping concentration is 2E20 cm -3 ~3E21 cm -3 or 5E20 cm -3 ~2E21 cm -3 .

6. The photovoltaic cell according to claim 1 or 3, characterized in that, The silicon substrate is recessed in the non-metal area.

7. The photovoltaic cell according to claim 6, wherein Both the metal area and the non-metal area on the backlight surface of the silicon substrate are polished surfaces after pyramidal texture polishing, and the base size of the pyramid on the metal area is smaller than the base size of the pyramid on the non-metal area.

8. The photovoltaic cell according to claim 6, wherein The base size of the pyramid on the metal area is 3 μm to 20 μm, and the base size of the pyramid on the non-metal area is 3 μm to 50 μm; or, The base size of the pyramid on the metal area is 8 μm to 15 μm, and the base size of the pyramid on the non-metal area is 15 μm to 30 μm.

9. The photovoltaic cell according to claim 1, characterized in that, A second tunneling passivation contact structure is provided on the non-metal area. The second passivation structure on the non-metal area is stacked on the second tunneling passivation contact structure, and the thickness of the second tunneling passivation contact structure is smaller than the thickness of the first tunneling passivation contact structure.

10. The photovoltaic cell according to claim 9, characterized in that, The first tunneling passivation contact structure includes a tunneling layer stacked on the metal area and at least one doping layer. The second tunneling passivation contact structure includes a tunneling layer stacked on the metal area and at least one doping layer, and the total thickness of the doping layers on the metal area is greater than the total thickness of the doping layers on the non-metal area.

11. The photovoltaic cell according to claim 10, characterized in that, Both the first tunneling passivation contact structure and the second tunneling passivation contact structure include a tunneling layer, an M1-layer second doping layer and an M1-layer blocking layer alternately stacked on the tunneling layer, and a third doping layer stacked on the outermost blocking layer. The thickness of the third doping layer in the second tunneling passivation contact structure is smaller than the thickness of the third doping layer in the first tunneling passivation contact structure, and M1 is a positive integer; or, The first tunneling passivation contact structure includes a tunneling layer, an M2-layer second doping layer and an M2-layer barrier layer alternately stacked on the tunneling layer, and a third doping layer stacked on the outermost barrier layer. The second tunneling passivation contact structure includes a tunneling layer, an M2-layer second doping layer and an M2-1-layer barrier layer alternately stacked on the tunneling layer, where M2 is a positive integer.

12. The photovoltaic cell according to claim 9, wherein, The height difference between the surfaces of the second passivation structure facing away from the silicon substrate in the metal region and the non-metal region is 0.01 μm to 0.153 μm or 0.048 μm to 0.102 μm.

13. The photovoltaic cell according to claim 11, characterized in that, The tunneling layer is any one or a combination of silicon oxide layer, silicon oxynitride layer; and / or, The thickness of the tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or, The barrier layer is any one or a combination of silicon oxide layer, silicon carbide layer; and / or, The thickness of the barrier layer is 0.5 nm to 3 nm or 1.5 nm to 2 nm; and / or, The doping type of the second doping layer is the same as that of the silicon substrate, and the surface doping concentration is 1E20 cm -3 ~9E20 cm -3 or 3E20 cm -3 ~5E20 cm -3 ; and / or, The doping type of the third doping layer is the same as that of the silicon substrate, and the surface doping concentration is 2E20 cm -3 ~3E21 cm -3 or 5E20 cm -3 ~2E21 cm -3 ; and / or, The second doping layer is a doped polysilicon layer with a thickness of 1 nm to 100 nm or 1 nm to 50 nm; and / or, The third doping layer is a doped polysilicon layer with a thickness of 1 nm to 150 nm or 50 nm to 100 nm; and / or, The total thickness of the second doping layer and the third doping layer in the metal region is 50 nm to 150 nm or 60 nm to 100 nm.

14. The photovoltaic cell according to claim 3 or 9, characterized in that, The metal region includes a plurality of first sub-regions that are parallel and equally spaced, and the non-metal region includes a plurality of second sub-regions that are parallel and equally spaced. The first sub-regions and the second sub-regions are alternately distributed, and the width of the first sub-region is 20 μm to 600 μm, and the width of the second sub-region is 100 μm to 800 μm.

15. The photovoltaic cell according to claim 1, characterized in that, The second passivation structure includes one or a combination of layers of silicon oxide layer, aluminum oxide layer, silicon nitride layer and silicon oxynitride layer.

16. The photovoltaic cell according to claim 15, characterized in that, The second passivation structure includes a silicon oxide layer, an aluminum oxide layer and a silicon nitride layer stacked in sequence. Among them, the thickness of the silicon oxide layer is 0.1 nm to 3 nm, the thickness of the aluminum oxide layer is 3 nm to 10 nm or 4 nm to 8 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm or 70 nm to 90 nm; or, The second passivation structure includes a silicon oxide layer and a silicon nitride layer stacked in sequence. Among them, the thickness of the silicon oxide layer is 1 nm to 30 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm or 70 nm to 90 nm.

17. The photovoltaic cell according to claim 1, characterized in that, A first doping layer and a first electrode in contact with the first doping layer are provided on the light-receiving surface of the silicon substrate.

18. The photovoltaic cell according to claim 17, wherein, The doping type of the first doping layer is opposite to that of the silicon substrate, and the surface doping concentration is 1E18 cm -3 ~5E19 cm -3 , and the thickness is 10 nm to 100 nm; and / or, A first passivation structure is stacked on the first doping layer. The first passivation structure includes an aluminum oxide layer and a silicon nitride layer stacked in sequence. Among them, the thickness of the aluminum oxide layer is 3 nm to 10 nm or 4 nm to 8 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm or 70 nm to 90 nm.

19. A photovoltaic module, characterized in that, The photovoltaic module includes a plurality of photovoltaic cells according to any one of claims 1 to 18.

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