Power-off reset circuit and electronic equipment

Abstract

The utility model provides a power-off reset circuit and an electronic device, and relates to the technical field of circuits, the power-off reset circuit comprises a button access unit, a manual reset chip and a reset control unit, the button access unit is connected with a manual reset pin of the manual reset chip, and a reset pin of the manual reset chip is connected with the reset control unit; and the key access unit is connected with a target key. According to the power-off reset circuit, the power supply unit and the power utilization access end can be forcibly disconnected and then automatically connected by pressing the target key for a long time, the main control chip of the electronic equipment applying the power-off reset circuit is forcibly powered off and then powered on, and the main control chip of the electronic equipment can be successfully reset in a crash state. According to the power-off reset circuit, the shell of the electronic equipment does not need to be disassembled, the power supply unit does not need to be plugged, and the operability of resetting the main control chip of the electronic equipment can be greatly improved.

Description

Technical Field

[0001] The utility model relates to the technical field of circuits, in particular to a power-off reset circuit and an electronic device. Background Art

[0002] At present, for the problem of the main control chip of an electronic device crashing in some abnormal working states, a general reset circuit controls the reset pin of the main control chip to control the system reset. However, some main control chips with relatively simple functions do not have a reset pin. Therefore, it is impossible to control the main control chip to reset by controlling the reset pin of the main control chip, and then the main control chip cannot return to the normal state from the crashed state.

[0003] In view of the above situation, when the main control chip enters the abnormal crashed state, only the shell of the electronic device can be disassembled, the battery of the electronic device can be unplugged and then reinserted, and then the shell can be installed, and the electronic device can be powered on again through the power-on button to make the main control chip enter the normal working state again.

[0004] However, once the shell of the electronic device is disassembled, not only the structural stability of the shell of the electronic device will be affected, but also the process of disassembling and assembling the shell and unplugging and plugging the battery is very time-consuming and laborious. At the same time, if the user operates improperly when unplugging and plugging the battery, the electronic device may be damaged, and even the battery may be short-circuited to cause a fire. Content of the Utility Model

[0005] The utility model provides a power-off reset circuit and an electronic device to solve the defects existing in the related technology.

[0006] The utility model provides a power-off reset circuit, including: a key access unit, a manual reset chip and a reset control unit. The key access unit is connected to the manual reset pin of the manual reset chip, and the reset pin of the manual reset chip is connected to the reset control unit;

[0007] The key access unit is connected to a target key and accesses a high level when the target key is pressed. The key access unit is configured to output a low level when accessing the high level;

[0008] The manual reset chip is configured to output a low level pulse signal at the reset pin when the manual reset pin accesses a low level for a preset duration;

[0009] The reset control unit is configured to switch the power supply unit and the power consumption access end from the connected state to the disconnected state when accessing the low level pulse signal.

[0010] According to the power-off reset circuit provided by the utility model, the key access unit includes a first triode and a first resistor;

[0011] The base of the first triode is connected to the output terminal of the target button through the first resistor;

[0012] The collector of the first triode is connected to the electrical signal output terminal and the manual reset pin;

[0013] The emitter of the first triode is grounded.

[0014] According to a power-off reset circuit provided by the present invention, the button access unit further includes a second resistor and a third resistor;

[0015] The base of the first triode is grounded through the second resistor;

[0016] The collector of the first triode is connected to the manual reset pin and is connected to the power supply unit through the third resistor.

[0017] According to a power-off reset circuit provided by the present invention, the reset control unit includes a second triode, a fourth resistor, a fifth resistor, a sixth resistor and a switch unit;

[0018] The base of the second triode is connected to the reset pin through the fifth resistor and is connected to the power supply unit through the fifth resistor and the sixth resistor;

[0019] The emitter of the second triode is connected to the power supply unit;

[0020] The collector of the second triode is connected to the first input terminal of the switch unit and is grounded through the fourth resistor;

[0021] The second input terminal of the switch unit is connected to the power supply unit, and the output terminal of the switch unit is connected to the power consumption access terminal;

[0022] The switch unit is configured such that when the first input terminal is at a low level, the second input terminal is connected to the output terminal, and when the first input terminal is at a high level, the second input terminal is disconnected from the output terminal.

[0023] According to a power-off reset circuit provided by the present invention, the switch unit is a PMOS transistor;

[0024] The first input terminal of the switch unit is the gate of the PMOS transistor;

[0025] The second input terminal of the switch unit is the drain of the PMOS transistor;

[0026] The output terminal of the switch unit is the source of the PMOS transistor.

[0027] According to a power-off reset circuit provided by the present utility model, it further includes a first capacitor, and a power supply pin of the manual reset chip is grounded through the first capacitor.

[0028] According to a power-off reset circuit provided by the present utility model, the reset control unit further includes a second capacitor, a third capacitor, and a fourth capacitor;

[0029] An output end of the switch unit is respectively grounded through the second capacitor and the third capacitor connected in parallel;

[0030] A second input end of the switch unit is grounded through the fourth capacitor.

[0031] According to a power-off reset circuit provided by the present utility model, the power supply pin of the manual reset chip is connected to the power supply unit.

[0032] The present utility model also provides an electronic device, including a target button, a power connection end, a power supply unit, and the above-mentioned power-off reset circuit.

[0033] According to an electronic device provided by the present utility model, the target button is a power-on / off button of the electronic device.

[0034] The power-off reset circuit and the electronic device provided by the present utility model. The power-off reset circuit can forcibly disconnect the power supply unit and the power connection end and then realize automatic connection by long-pressing the target button. After forcibly powering off and then powering on the main control chip of the electronic device applying the power-off reset circuit, the main control chip of the electronic device can be successfully reset in a dead state. The power-off reset circuit neither needs to disassemble the shell of the electronic device nor needs to plug and unplug the power supply unit, which can greatly improve the operability of resetting the main control chip of the electronic device. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the present utility model or related technologies, the following will briefly introduce the drawings required for use in the embodiments or related technology descriptions. Obviously, the following drawings are some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 is one of the structural schematic diagrams of the power-off reset circuit provided by the present utility model.

[0037] Figure 2 is another structural schematic diagram of the power-off reset circuit provided by the present utility model.

[0038] Figure 3 is the structural schematic diagram of the electronic device provided by the present utility model. Detailed implementation manners

[0039] To make the objectives, technical solutions and advantages of the present utility model clearer, the technical solutions in the present utility model will be clearly and completely described below with reference to the accompanying drawings in the present utility model. Apparently, the described embodiments are some but not all of the embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present utility model without making creative efforts belong to the scope of protection of the present utility model.

[0040] In the prior art, the scheme of disassembling the housing and unplugging the battery when performing a power-off reset on an electronic device will affect the structural stability of the housing of the electronic device, and the process of disassembling and assembling the housing and plugging and unplugging the battery is also very time-consuming and laborious. When plugging and unplugging the battery, the electronic device may be damaged due to improper user operation, and even the battery may be short-circuited to cause a fire. Therefore, an embodiment of the present utility model provides a power-off reset circuit, which can be configured in an electronic device to perform a power-off reset on the electronic device, and is particularly applicable to an electronic device whose main control chip lacks a reset pin.

[0041] Figure 1 The following is a schematic structural diagram of a power-off reset circuit provided in an embodiment of the present utility model, as Figure 1 shown. The power-off reset circuit includes a key access unit 1, a manual reset chip U1, and a reset control unit 2. The key access unit 1 is connected to the manual reset (MR) pin of the manual reset chip U1, and the reset (RESET) pin of the manual reset chip U1 is connected to the reset control unit 2.

[0042] The key access unit 1 is connected to a target key and accesses a high level when the target key is pressed. The key access unit 1 is configured to output a low level when accessing a high level.

[0043] The manual reset chip U1 is configured to output a low-level pulse signal at the RESET pin when the MR pin accesses a low level for a preset duration.

[0044] The reset control unit 2 is configured to switch the power supply unit and the power consumption access end from a connected state to a disconnected state when accessing a low-level pulse signal.

[0045] Specifically, the key access unit 1 of the power-off reset circuit can be connected to the target key. By pressing the target key, an input signal of the power-off reset circuit is generated. If the power-off reset circuit is configured in an electronic device, the target key can be an existing key on the electronic device, such as the power-on / off key of the electronic device. The target key can also be a newly added key on the electronic device, such as a reset key. Here, the electronic device can be an intelligent device such as a learning machine or a dictionary pen, or other electronic devices that have a power-off reset requirement and whose main control chip does not have a reset pin.

[0046] When the user presses the target key, a high-level input signal POWKEY is generated. When the user does not press the target key, a low-level input signal POWKEY is generated.

[0047] The key access unit 1 is connected to the MR pin of the manual reset chip U1. The key access unit is configured to output a low level when a high level is accessed and output a high level when a low level is accessed. Thus, when the user presses the target key, the MR pin is at a low level, and when the user does not press the target key, the MR pin is at a high level.

[0048] The manual reset chip U1 is configured to output a low-level pulse signal at the RESET pin when the MR pin is accessed with a low level for a preset duration. Among them, the low level of the preset duration can be obtained by the user pressing the target key for a preset duration. Both the preset duration and the duration of the low-level pulse signal can be determined according to the specific model of the manual reset chip U1. For example, if the model of the manual reset chip U1 is UM821, the preset duration can be 6.7 s, and the duration of the low-level pulse signal can be 240 ms.

[0049] The RESET pin of the manual reset chip U1 is connected to the reset control unit 2. The reset control unit 2 is configured to switch the power supply unit and the power consumption access end from the connected state to the disconnected state when a low-level pulse signal is accessed.

[0050] It can be understood that the premise for the power-off reset circuit to work is that the power supply unit and the power consumption access end are in the connected state. At this time, the power supply unit supplies power to the electronic device by connecting to the power consumption access end. Among them, the power supply unit can be a battery, and the power consumption access end can be the port where the battery supplies power to the electronic device. The voltage of the power supply unit can be expressed as VBAT, and the voltage of the power consumption access end can be expressed as VBAT_IN.

[0051] The working content of the power-off reset circuit is to switch the power supply unit and the power consumption access end from the connected state to the disconnected state. At this time, since the power supply unit is disconnected from the power consumption access end, the power supply unit cannot supply power to the electronic device.

[0052] However, the disconnection state of the power supply unit and the power consumption access terminal can only last for the duration of the low-level pulse signal. After the power supply unit and the power consumption access terminal are switched to the disconnection state by the reset control unit 2, as the low-level pulse signal changes back to the high level, the power supply unit and the power consumption access terminal are automatically switched back to the connection state. At this time, the power supply unit powers the electronic device by reconnecting with the power consumption access terminal, thereby realizing power-off reset and automatic switching from power-on to power-off and then to power-on, enabling the main control chip of the electronic device to be forced to power off and then power on again when powered on.

[0053] The power-off reset circuit provided in the embodiment of the present invention includes: a key access unit, a manual reset chip, and a reset control unit. The key access unit is connected to the manual reset pin of the manual reset chip, and the reset pin of the manual reset chip is connected to the reset control unit; the key access unit is connected to the target key and accesses a high level when the target key is pressed, and the key access unit is configured to output a low level when accessing a high level; the manual reset chip is configured to output a low-level pulse signal at the reset pin when the manual reset pin accesses a low level for a preset duration; the reset control unit is configured to switch the power supply unit and the power consumption access terminal from the connected state to the disconnected state when accessing the low-level pulse signal. This power-off reset circuit can forcibly disconnect the power supply unit and the power consumption access terminal and then automatically reconnect by long-pressing the target key. After forcibly powering off and then powering on the main control chip of the electronic device applying this power-off reset circuit, the main control chip of the electronic device can be successfully reset in a dead state. This power-off reset circuit neither requires opening the shell of the electronic device nor unplugging the power supply unit, which can greatly improve the operability of resetting the main control chip of the electronic device.

[0054] On the basis of the above embodiment, as Figure 2 shown, the key access unit 1 may include a first triode Q1 and a first resistor R1. The base b of the first triode Q1 is connected to the output terminal of the target key through the first resistor R1 for receiving an input signal; the collector c of the first triode Q1 is connected to the electrical signal output terminal and the MR pin of the manual reset chip U1; the emitter e of the first triode Q1 is grounded.

[0055] Specifically, when the user presses the target key, the input signal POWKEY is high level, VBAT is high level, the first triode Q1 conducts, the collector c of the first triode Q1 is low level, and the MR pin of the manual reset chip U1 is low level.

[0056] When the user does not press the target key, the input signal POWKEY is low level, VBAT is high level, the first triode Q1 is turned off, the collector c of the first triode Q1 is high level, and the MR pin of the manual reset chip U1 is high level.

[0057] Among them, the first triode Q1 can be an NPN triode. The first resistor R1 is a current-limiting resistor, and its resistance value can be set as needed. For example, the resistance value of the first resistor R1 can be 1 kΩ.

[0058] In the embodiment of the present utility model, by using the first triode, the structure of the key access unit can be simplified, and the complexity of the key access unit can be reduced.

[0059] On the basis of the above embodiment, as Figure 2 shown, the key access unit 1 further includes a second resistor R2 and a third resistor R3;

[0060] The base b of the first triode Q1 is grounded through the second resistor R2;

[0061] The collector c of the first triode Q1 is connected to the MR pin of the manual reset chip U1 and is connected to the power supply unit through the third resistor R3.

[0062] Specifically, the resistance values of the second resistor R2 and the third resistor R3 can both be set as needed. For example, the resistance values of the second resistor R2 and the third resistor R3 can both be 10 kΩ. Among them, the second resistor R2 is a pull-down resistor, so that the base b of the first triode Q1 is at a low level when the target key is not pressed, and the first triode Q1 is not turned on. The third resistor R3 is a pull-up resistor, so that the collector c of the first triode Q1 is at a high level when the target key is not pressed.

[0063] In the embodiment of the present utility model, by introducing the second resistor and the third resistor, the key access unit can be in a steady state of outputting a high level when the target key is not pressed.

[0064] On the basis of the above embodiment, as Figure 2 shown, the reset control unit 2 includes a second triode Q2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a switch unit Q3;

[0065] The base b of the second triode Q2 is connected to the RESET pin of the manual reset chip U1 through the fifth resistor R5 and is connected to the power supply unit through the fifth resistor R5 and the sixth resistor R6;

[0066] The emitter e of the second triode Q2 is connected to the power supply unit;

[0067] The collector c of the second triode Q2 is connected to the first input terminal 31 of the switch unit Q3 and is grounded through the fourth resistor R4;

[0068] The second input terminal 32 of the switch unit Q3 is connected to the power supply unit, and the output terminal 33 of the switch unit Q3 is connected to the power consumption access terminal;

[0069] The switch unit Q3 is configured such that when the first input terminal 31 is at a low level, the second input terminal 32 is connected to the output terminal 33, and when the first input terminal 31 is at a high level, the second input terminal 32 is disconnected from the output terminal 33.

[0070] Specifically, in the embodiment of the present utility model, the second triode Q2 can be a PNP triode.

[0071] When the user does not press the target button, both the base b and the emitter e of the second triode Q2 are at a high level, the second triode Q2 is turned off, and the collector c of the second triode Q2 is at a low level. The first input terminal 31 of the switch unit Q3 is at a low level, the second input terminal 32 of the switch unit Q3 is connected to the output terminal 33, and the power supply unit supplies power to the electronic device.

[0072] When the user presses and immediately releases the target button, both the base b and the emitter e of the second triode Q2 are at a high level, the second triode Q2 is turned off, and the collector c of the second triode Q2 is at a low level. The first input terminal 31 of the switch unit Q3 is at a low level, the second input terminal 32 of the switch unit Q3 is connected to the output terminal 33, and the power supply unit supplies power to the electronic device.

[0073] When the user presses the target button and holds it for a preset duration, the RESET pin of the manual reset chip U1 is a low-level pulse signal. The second triode Q2 changes from off to on and then to off. The first input terminal 31 of the switch unit Q3 changes from low level to high level and then to low level. The second input terminal 32 of the switch unit Q3 is connected to the output terminal 33, then disconnected, and then connected again. The power supply unit changes from the power supply state to the power-off state and then to the power supply state, realizing the restart of the electronic device, and further realizing the power-off reset of the main control device of the electronic device.

[0074] The resistance value of the fourth resistor R4 can be set as needed. For example, it can be set to 10 kΩ. The fifth resistor R5 is a current-limiting resistor, and its resistance value can be set as needed. For example, it can be set to 1 kΩ. The sixth resistor R6 is a pull-up resistor, which makes the base b of the second triode Q2 at a high level when the MR pin of the manual reset chip U1 is at a high level or an instantaneous low level. The resistance value of the sixth resistor R6 can be set as needed. For example, it can be set to 10 kΩ.

[0075] In the embodiment of the present utility model, by combining the second triode with the switch unit, the power-off reset function can be quickly realized, and the structure is simple, which can reduce the cost of power-off reset.

[0076] Based on the above embodiments, the switching unit Q3 can be a PMOS transistor; the first input terminal 31 of the switching unit Q3 can be the gate (G) of the PMOS transistor; the second input terminal 32 of the switching unit Q3 can be the source (S) of the PMOS transistor; the output terminal 33 of the switching unit Q3 can be the drain (D) of the PMOS transistor.

[0077] Based on the above embodiments, as Figure 2 shown, the power supply pin VCC of the manual reset chip U1 is connected to the power supply unit, so that the manual reset chip U1 can always be in the working state when the power supply unit has sufficient power.

[0078] Based on the above embodiments, as Figure 2 shown, the power supply pin VCC of the manual reset chip U1 is also grounded through the first capacitor C1. The first capacitor C1 can be a filter capacitor, and its capacitance value can be set as needed. For example, it can be 100 nF.

[0079] Based on the above embodiments, as Figure 2 shown, the output terminal 33 of the switching unit Q3 can be grounded through the second capacitor C2 and the third capacitor C3 connected in parallel. Both the second capacitor C2 and the third capacitor C3 can be filter capacitors, and their capacitance values can be set as needed. For example, the capacitance value of the second capacitor C2 can be 10 μF, and the capacitance value of the third capacitor C3 can be 100 nF.

[0080] Based on the above embodiments, as Figure 2 shown, the second input terminal 32 of the switching unit Q3 can be grounded through the fourth capacitor C4. The fourth capacitor C4 can be a filter capacitor, and its capacitance value can be set as needed. For example, the capacitance value of the fourth capacitor C4 can be 10 μF.

[0081] In summary, in the power-off reset circuit provided in the embodiment of the present invention, when the user does not press the target button, the input signal is at a low level, the first triode Q1 is turned off, the MR pin of the reset chip U1 is at a high level, the base b and the emitter e of the second triode Q2 are both at a high level, the second triode Q2 is turned off, the gate of the PMOS transistor is at a low level, the PMOS transistor is turned on, and the power supply unit supplies power.

[0082] When the user presses and then immediately releases the target button, the input signal is at a high level, the first triode Q1 is turned on, the MR pin of the reset chip U1 is at an instantaneous low level, the base b and the emitter e of the second triode Q2 are both at a high level, the second triode Q2 is turned off, the gate of the PMOS transistor is at a low level, the PMOS transistor is turned on, and the power supply unit supplies power.

[0083] When the user presses the target button and holds it for a preset duration, the input signal is at a high level, the first triode Q1 conducts, the MR pin of the reset chip U1 is at a low level for the preset duration, the RESET pin outputs a low-level pulse signal and then outputs a high level, the second triode Q2 turns on, then turns off, and then turns on again, the gate of the PMOS transistor goes from a low level to a high level and then to a low level, the PMOS transistor turns on, then turns off, and then turns on again, and the power supply unit goes from a power supply state to a power-off state and then to a power supply state, realizing the restart of the electronic device and causing the main control chip of the electronic device to be powered off and reset.

[0084] As Figure 3 shown, on the basis of the above embodiments, an electronic device is further provided in the embodiments of the present invention. The electronic device includes a target button 41, a power connection end 42, a power supply unit 43, and the power-off reset circuit 44 provided in each of the above embodiments. Due to the introduction of the power-off reset circuit, the electronic device can be restarted by the user long-pressing the target button 41 for a preset duration, so that the main control chip of the electronic device can be powered off and reset.

[0085] On the basis of the above embodiments, for the electronic device in the embodiments of the present invention, the target button can be the power-on / off button of the electronic device. In this way, the electronic device can be restarted by the user long-pressing the power-on / off button of the electronic device for a preset duration, so that the main control chip of the electronic device can be powered off and reset. It is not necessary to additionally add a button to the electronic device, reducing the restart cost of the electronic device.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power-off reset circuit, characterized in that, Comprising: A key access unit, a manual reset chip, and a reset control unit. The key access unit is connected to the manual reset pin of the manual reset chip, and the reset pin of the manual reset chip is connected to the reset control unit; The key access unit is connected to a target key and accesses a high level when the target key is pressed. The key access unit is configured to output a low level when accessing a high level; The manual reset chip is configured to output a low level pulse signal at the reset pin when the manual reset pin accesses a low level for a preset duration; The reset control unit is configured to switch the power supply unit and the power consumption access end from a connected state to a disconnected state when accessing a low level pulse signal.

2. The power-off reset circuit according to claim 1, wherein The key access unit includes a first triode and a first resistor; The base of the first triode is connected to the output end of the target key through the first resistor; The collector of the first triode is connected to the signal output end and the manual reset pin; The emitter of the first triode is grounded.

3. The power-off reset circuit according to claim 2, wherein The key access unit further includes a second resistor and a third resistor; The base of the first triode is grounded through the second resistor; The collector of the first triode is connected to the manual reset pin and is connected to the power supply unit through the third resistor.

4. The power-off reset circuit according to claim 1, characterized in that, The reset control unit includes a second triode, a fourth resistor, a fifth resistor, a sixth resistor, and a switch unit; The base of the second triode is connected to the reset pin through the fifth resistor and is connected to the power supply unit through the fifth resistor and the sixth resistor; The emitter of the second triode is connected to the power supply unit; The collector of the second triode is connected to the first input end of the switch unit and is grounded through the fourth resistor; The second input end of the switch unit is connected to the power supply unit, and the output end of the switch unit is connected to the power consumption access end; The switch unit is configured to connect the second input end to the output end when the first input end is at a low level and disconnect the second input end from the output end when the first input end is at a high level.

5. The power-off reset circuit according to claim 4, characterized in that The switch unit is a PMOS transistor; The first input end of the switch unit is the gate of the PMOS transistor; The second input end of the switch unit is the drain of the PMOS transistor; The output end of the switch unit is the source of the PMOS transistor.

6. The power-off reset circuit according to claim 1, characterized in that, It further includes a first capacitor. The power supply pin of the manual reset chip is grounded through the first capacitor.

7. The power-off reset circuit according to claim 4, wherein, The reset control unit further includes a second capacitor, a third capacitor, and a fourth capacitor; The output end of the switch unit is grounded respectively through the second capacitor and the third capacitor connected in parallel; The second input end of the switch unit is grounded through the fourth capacitor.

8. The power-off reset circuit according to any one of claims 1-7, characterized in that The power supply pin of the manual reset chip is connected to the power supply unit.

9. An electronic device, characterized in that, Comprising a target key, a power consumption access end, a power supply unit, and a power-off reset circuit according to any one of claims 1-8.

10. The electronic device according to claim 9, wherein The target key is the power-on / off key of the electronic device.

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