Test switching device

Abstract

A test switching device comprises: a USB hub module having a plurality of USB interfaces; a plurality of PCIe slots, each including a plurality of channels grouped into channel groups; the plurality of interface switching modules are respectively connected with the channel group of one PCIe slot and one USB interface, and are used for signal conversion; the plurality of switch modules are used for controlling the power supply states of the corresponding interface switching modules; and the control switching module is connected with the host system and the switch module and is used for controlling the state of the switch module according to the received test instruction so as to selectively control the power supply of the interface switching module. The PCIe interface storage device has the technical effects that the simulation hot plug function of the PCIe interface storage device is realized, and the test flexibility and efficiency are improved; parallel testing of a plurality of storage devices is supported; various PCIe and USB standards are compatible; testing equipment requirements and plugging requirements are simplified; accurate management of the testing process is achieved, and the system reliability and the testing quality are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of storage device testing, and particularly relates to a test adapter device for testing multiple storage devices. Background Art

[0002] With the development of computer technology, solid-state drives with a high-speed serial computer expansion bus standard (PCIe) interface have been widely used in various electronic devices. However, solid-state drives with a PCIe interface usually do not support the hot-plug function, which brings difficulties to the test verification on the production line. Existing test methods often require functional verification of the solid-state drive while the test computer is powered on, and the external interfaces of the test computer generally do not have PCIe slots. In addition, due to the limitation of the transmission bandwidth, it is currently difficult to verify multiple solid-state drives simultaneously, which seriously affects the test efficiency.

[0003] Therefore, there is an urgent need for a test adapter device that can support the hot plug of solid-state drives with a PCIe interface and can simultaneously test multiple storage devices in parallel to improve the test efficiency and resource utilization rate. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a test adapter device for testing multiple storage devices to solve the technical problems in the prior art that it is difficult to hot plug storage devices with a PCIe interface and it is difficult to test multiple storage devices in parallel.

[0005] One or more embodiments of the present utility model provide a test adapter device applicable to testing multiple storage devices. The test adapter device includes: a USB hub module electrically connected to a host USB interface of a host system, the USB hub module including a plurality of USB interfaces; a plurality of PCIe slots supporting the Peripheral Component Interconnect Express (PCIe) standard for electrically connecting the multiple storage devices to be tested, wherein each PCIe slot includes a plurality of channels, and the plurality of channels of each PCIe slot are grouped into a plurality of channel groups; a plurality of interface conversion modules, wherein a first interface of each interface conversion module is electrically connected to a channel group of a PCIe slot, and a second interface is electrically connected to a USB interface, and each interface conversion module is used for signal conversion between a channel group in the PCIe slot and the USB interface; a plurality of switch modules respectively electrically connected to the plurality of interface conversion modules for controlling the power supply states of the corresponding interface conversion modules; and a control switching module electrically connected to the host system and the plurality of switch modules for controlling the switch states of each switch module. Wherein, the control switching module sends control signals to control the switch states of the plurality of switch modules respectively according to the test instructions received from the host system, and selectively controls the power supply states of the plurality of interface conversion modules respectively to enable a plurality of target channel groups of the plurality of PCIe slots corresponding to the test requirements, and then performs a test operation on the multiple storage devices to be tested electrically connected to the plurality of PCIe slots.

[0006] In one or more embodiments of the present utility model, the control switching module includes: a plurality of control signal output terminals electrically connected to the plurality of switch modules for respectively transmitting a plurality of control signals to the plurality of switch modules to control different switch states of the plurality of switch modules, wherein each control signal includes a first level or a second level.

[0007] In one or more embodiments of the present utility model, the control switching module includes: one or more inverters configured between an output terminal of the control switching module for outputting the control signal and the plurality of switch modules for converting the input control signal into an inverse control signal, so that some of the plurality of switch modules receive the inverse control signal, thereby simultaneously controlling different switch states of the plurality of switch modules through a single control signal.

[0008] In one or more embodiments of the present utility model, the signals received by the channel groups with the same number of each of the plurality of PCIe slots are the same.

[0009] In one or more embodiments of the present utility model, the test adapter device further includes: a power input module, externally connected to an external power source, for supplying power to the plurality of interface adapter modules, wherein the power input module is electrically connected to the plurality of interface adapter modules respectively through the plurality of switch modules.

[0010] In one or more embodiments of the present utility model, each switch module includes: a first switch tube; a second switch tube; a power input terminal for connecting to the power input module; and a power output terminal for connecting to the corresponding interface adapter module, wherein a first node of the first switch tube is connected to the power input terminal, a second node of the first switch tube is connected to the power output terminal, a second node of the second switch tube is connected to a control terminal of the first switch tube, a first node of the second switch tube is grounded, and the control terminal of the second switch tube is used to receive the control signal or the anti-control signal output by the control switching module.

[0011] In one or more embodiments of the present utility model, the first switch tube is a PMOS transistor, wherein the first node of the first switch tube is the source of the PMOS transistor, the second node of the first switch tube is the drain of the PMOS transistor, and the control terminal of the first switch tube is the gate of the PMOS transistor; and the second switch tube is an NMOS transistor, wherein the first node of the second switch tube is the source of the NMOS transistor, the second node of the second switch tube is the drain of the NMOS transistor, and the control terminal of the second switch tube is the gate of the NMOS transistor.

[0012] In one or more embodiments of the present utility model, the switch module further includes: a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor, wherein the drain of the NMOS transistor is connected to the power input terminal through the first resistor, the drain of the NMOS transistor is connected to the gate of the PMOS transistor through the second resistor, a first end of the first capacitor is connected between the source of the PMOS transistor and the power input terminal, and a second end of the first capacitor is grounded, a first end of the second capacitor is connected between the drain of the PMOS transistor and the power output terminal, and a second end of the second capacitor is grounded, a first end of the third resistor is connected between the drain of the PMOS transistor and the power output terminal, and a second end of the third resistor is grounded.

[0013] In one or more embodiments of the present utility model, the USB hub module further includes: an upstream interface for connecting to the host USB interface; a hub control module for managing data flow; and a high-speed routing module for distributing data from the hub control module to corresponding USB interfaces according to instructions of the hub control module.

[0014] In one or more embodiments of the present utility model, the total number of the multiple channels grouped into the same channel group is a first number, and the first number is the maximum number of the multiple channels that can be supported without exceeding the maximum supported bandwidth of each USB interface.

[0015] Based on the above, the present utility model provides a test adapter device for testing multiple storage devices. Through a combined design of an innovative interface conversion module (such as a PCIe-to-USB module), a control switching module, and a switch module, the following beneficial effects are achieved. Simulated hot plug function: The simulated hot plug of the PCIe interface storage device is realized through power control, improving test flexibility and efficiency while reducing hardware loss; Parallel test capability: Support for simultaneously testing multiple storage devices, significantly improving test efficiency; Flexible resource allocation: Adopting a channel grouping method, flexible resource allocation and management are realized according to the bandwidth characteristics of USB interfaces and PCIe channels; Strong compatibility: Support for multiple PCIe and USB standards, adapting to storage devices of different specifications and generations; Precise control: Through the control switching module and the switch module, precise control of each PCIe-to-USB module is realized, improving system reliability and test flexibility.

[0016] To make the above features and advantages of the present utility model more obvious and understandable, specific embodiments are hereinafter given and detailed descriptions are made in conjunction with the accompanying drawings as follows. Description of the Drawings

[0017] Figure 1 It is a block diagram of a test system shown according to an embodiment of the present utility model;

[0018] Figure 2 It is a block diagram of a test adapter device shown according to an embodiment of the present utility model;

[0019] Figure 3 It is another block diagram of a test adapter device shown according to an embodiment of the present utility model;

[0020] Figure 4 It is a block diagram of a test adapter device shown according to another embodiment of the present utility model;

[0021] Figure 5 It is a circuit schematic diagram of a switch module shown according to an embodiment of the present utility model;

[0022] Figure 6 A block diagram of a host system according to an embodiment of the present utility model;

[0023] Figure 7 A block diagram of a USB hub module according to an embodiment of the present utility model.

[0024] Explanation of reference numerals in the drawings

[0025] 10: Test system

[0026] 100: Test adapter device

[0027] 110: Control switching module

[0028] 111(1), 111(2): Inverters

[0029] 120: USB hub module

[0030] 121: Upstream port interface

[0031] 122: Hub control module

[0032] 123: High-speed routing module

[0033] 124(1) to 124(4): USB interfaces

[0034] 130(1) to 130(4): Switch modules

[0035] 131: NMOS transistor

[0036] 132: PMOS transistor

[0037] 140(1) to 140(4): Interface adapter module / PCIe to USB module

[0038] 150(1) to 150(2): PCIe slots

[0039] 151(1) to 151(4): Channel groups

[0040] 160: Power input module

[0041] 200: Host system

[0042] 210: Processor

[0043] 220: Host memory

[0044] 230: Host USB interface

[0045] 300(1), 300(2): Storage devices

[0046] C1, C2: Capacitors

[0047] R1, R2, R3: Resistors

[0048] S1, S2: Sources

[0049] D1, D2: Drains

[0050] G1, G2: Gates

[0051] TD: Test Data

[0052] CC1: Test Instruction

[0053] CS, CS1~CS4: Control Signals

[0054] Vin: Power Input Terminal

[0055] Vout: Power Output Terminal Detailed Implementation Manner

[0056] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts. The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only with reference to the directions of the additional accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0057] Figure 1 It is a block diagram of a test system shown according to an embodiment of the present invention.

[0058] Please refer to Figure 1 , in an embodiment, as Figure 1 shown, the present invention provides a test system 10 for testing a plurality of storage devices. The test system 10 includes a host system 200, a test adapter device 100, and a plurality of storage devices 300 (e.g., storage devices 300(1) to 300(2)).

[0059] The host system 200 is used to control the entire test process, send test instructions and receive and transmit test data to analyze the test results. The host system 200 can be a computer or a dedicated test control device, in which test control software is installed to manage the test process, analyze the test data and generate a test report.

[0060] The test transfer device 100 is the core part of the present utility model. It is connected between the host system 200 and multiple storage devices 300 for performing actual test operations. The test transfer device 100 includes various modules, such as a Universal Serial Bus (USB) hub module, multiple Peripheral Component Interconnect Express (PCIe) slots, multiple interface transfer modules, multiple switch modules, and a control switching module, etc. The test transfer device 100 receives test instructions from the host system 200 and controls the test process of the storage device 300 and the switching of channels according to the instructions. In this embodiment, the interface transfer module is, for example, a PCIe to USB module.

[0061] The storage devices 300(1), 300(2), etc. represent multiple storage devices to be tested, usually solid state drives with PCIe interfaces. These storage devices are connected to the system through the PCIe slots in the test transfer device 100. Figure 1 Two storage devices are exemplarily shown in the figure, but actually the system can support testing of a larger number of storage devices simultaneously.

[0062] For example, in an embodiment, the operation process of the test system 10 is as follows:

[0063] (1). The host system 200 sends a test instruction to the test transfer device 100.

[0064] (2). The control switching module in the test transfer device 100 receives and parses the test instruction.

[0065] (3). The control switching module generates a control signal according to the instruction and controls the power supply state of the corresponding interface transfer module through the switch module.

[0066] (4). The enabled interface transfer module (PCIe to USB module) starts to work and converts the PCIe signal into a USB signal.

[0067] (5). The converted signal is transmitted back to the host system 200 through the USB hub module.

[0068] (6). The host system 200 receives the test data and performs analysis and processing.

[0069] (7). During the test process, different storage devices 300 or channel groups can be switched for testing according to needs.

[0070] (8). After the test is completed, the host system 200 generates a test report.

[0071] This system architecture design allows for parallel testing of multiple storage devices 300 simultaneously, greatly improving the testing efficiency. At the same time, due to the adoption of the PCIe-to-USB technical solution, the PCIe interface storage devices that originally did not support hot plugging can achieve hot plugging functions similar to USB devices, facilitating device replacement and management during the testing process.

[0072] Figure 2 The block diagram of the test adapter device shown according to the embodiment of the present utility model.

[0073] In one embodiment, as Figure 2 shown, the present utility model provides a test adapter device 100 for testing multiple storage devices. The test adapter device 100 includes a USB hub module 120, multiple PCIe slots 150(1) - 150(2), multiple interface conversion modules (also referred to as PCIe-to-USB modules) 140(1) - 140(4), multiple switch modules 130(1) - 130(4), a control switching module 110, and a power input module 160.

[0074] The USB hub module 120 is electrically connected to the host USB interface of the host system 200 to establish a data channel for transmitting and receiving test data TD. The USB hub module 120 includes multiple USB interfaces, which are respectively used to connect to multiple interface conversion modules 140(1) - 140(4).

[0075] The test adapter device 100 includes multiple PCIe slots 150(1), 150(2) for electrically connecting multiple storage devices 300(1), 300(2) to be tested. Each PCIe slot includes multiple channels, and these channels are grouped into multiple channel groups (for example, a PCIe slot has four channels, and a channel group can have two channels). Specifically, the PCIe slot 150(1) includes channel groups 151(1) and 151(2), and the PCIe slot 150(2) includes channel groups 151(3) and 151(4).

[0076] Among the multiple interface conversion modules 140(1), 140(2), 140(3), 140(4), the first interface of each interface conversion module 140 is electrically connected to a channel group 151 of a PCIe slot 150, and the second interface is electrically connected to a USB interface of the USB hub module 120. Each interface conversion module 140 is used for signal conversion between a channel group in the PCIe slot and the USB interface, such as converting the PCIe signal from the one channel group 151 into a USB signal and inputting the USB signal to the corresponding USB interface of the USB hub module 120.

[0077] A plurality of switch modules 130(1), 130(2), 130(3), 130(4) are electrically connected to a plurality of interface adapter modules 140(1), 140(2), 140(3), 140(4) respectively, for controlling the power supply states of the corresponding interface adapter modules 140. The test adapter device 100 further includes a power input module 160, which is externally connected to an external power supply for providing power to the plurality of interface adapter modules 140(1) - 140(4), wherein the power input module 160 is electrically connected to the plurality of interface adapter modules 140(1) - 140(4) respectively through the plurality of switch modules 130(1) - 130(4).

[0078] The control switching module 110 is electrically connected to the host system 200 and the plurality of switch modules 130(1) - 130(4), for controlling signals to control the on / off states of each switch module 130. The control switching module 110 generates and sends a control signal corresponding to the test instruction CC1 according to the test instruction CC1 received from the host system 200 to control the on / off states of the plurality of switch modules 130(1) - 130(4) respectively, so as to selectively control the power supply states of the plurality of interface adapter modules 140 respectively, such that the target channel group of the target PCIe slot meeting the test requirements can send and convert test data through the powered interface adapter module, and further perform a test operation on the target storage device electrically connected to the powered PCIe slot.

[0079] In an embodiment, the connection relationships and interactions among the modules are as follows:

[0080] The host system 200 is connected to the USB hub module 120 and the control switching module 110 through the host USB interface, for receiving and transmitting test data and analyzing test results. Meanwhile, the host system 200 sends the test instruction CC1 to the control switching module 110.

[0081] The control switching module 110 is connected to the plurality of switch modules 130(1) - 130(4), for controlling the on / off states of each switch module 130.

[0082] The USB hub module 120 is connected to the four interface adapter modules 140(1) - 140(4) respectively, for transmitting the converted USB signals to the host system 200.

[0083] Each of the switch modules 130(1) - 130(4) is connected to the corresponding interface adapter module 140(1) - 140(4) respectively, for controlling its power supply state.

[0084] The interface transfer modules 140(1) and 140(2) are respectively connected to the channel groups 151(1) and 151(2) of the PCIe slot 150(1); the interface transfer modules 140(3) and 140(4) are respectively connected to the channel groups 151(3) and 151(4) of the PCIe slot 150(2).

[0085] The PCIe slots 150(1) and 150(2) are respectively connected to the storage devices 300(1) and 300(2), and are used for actual data transmission and test operations on the connected storage devices.

[0086] The power input module 160 is connected to all the switch modules 130(1) - 130(4), and provides power for the interface transfer modules 140(1) - 140(4).

[0087] In an embodiment, the host system 200 first sends a test instruction CC1 to the control switching module 110. After parsing the instruction, the control switching module 110 generates corresponding control signals and sends them to the switch modules 130(1) - 130(4). The switch modules change their states according to the control signals, thereby controlling the power supply of the corresponding interface transfer modules 140(1) - 140(4). The enabled interface transfer modules convert the PCIe signals received from the storage devices 300(1) or 300(2) from the PCIe slots 150(1) or 150(2) into USB signals, and then transmit them to the host system 200 through the USB hub module 120 for processing and analysis.

[0088] This design allows for flexible control of the test states of different channel groups, enables parallel testing of multiple storage devices, and at the same time realizes the hot plug function of PCIe interface storage devices through the PCIe - to - USB conversion, greatly improving the test efficiency and system flexibility.

[0089] Figure 3 It is another block diagram of the test transfer device shown in the embodiments according to the present utility model.

[0090] Please refer to Figure 3 , continuing the example of Figure 2 , Figure 3 which highlights the connection relationship and interaction between the control switching module 110 and the switch modules 130(1)-(4). In an embodiment, the control switching module includes a plurality of control signal output terminals, electrically connected to the plurality of switch modules, for respectively transmitting a plurality of control signals to the plurality of switch modules to control different switch states of the plurality of switch modules, wherein each control signal includes a first level or a second level.

[0091] More specifically, the control switching module 110 includes multiple control signal output terminals, which are electrically connected to the switch modules 130(1), 130(2), 130(3), and 130(4) respectively. Each control signal output terminal is used to transmit the control signals CS1, CS2, CS3, and CS4 to the corresponding switch modules 130(1), 130(2), 130(3), and 130(4) to control the on / off state of the switch module.

[0092] In actual operation, the control switching module 110 sends the control signals CS1, CS2, CS3, and CS4 to the switch modules 130(1), 130(2), 130(3), and 130(4) respectively through the control signal output terminals according to the test instructions received from the host system 200. These control signals can be high-level signals (also called, the first level) or low-level signals (also called, the second level), and are used to control the conduction or disconnection state of the corresponding switch module. For example, when CS1 outputs a high-level signal, the switch module 130(1) conducts, allowing the power supply to flow from the power input module 160 to the interface transfer module 140(1); when CS1 outputs a low-level signal, the switch module 130(1) disconnects, cutting off the power supply to the interface transfer module 140(1).

[0093] This design allows the control switching module 110 to flexibly control the working state of each interface transfer module 140, thereby realizing the selective testing of different channel groups. For example, the interface transfer modules 140(1) and 140(3) can be enabled simultaneously to perform parallel testing on some channels of the storage devices 300(1) and 300(2), while keeping the interface transfer modules 140(2) and 140(4) in the off state.

[0094] It is worth mentioning that in one embodiment, in order to save the configuration quantity of the control signal output terminals, the control switching module further includes one or more inverters, which are configured between the output terminals of the control switching module for outputting the control signals and the multiple switch modules, and are used to convert the input control signals into anti-control signals, so that some of the multiple switch modules receive the anti-control signals, thereby simultaneously controlling different on / off states of the multiple switch modules through a single control signal.

[0095] Figure 4 It is a block diagram of a test transfer device shown in another embodiment according to the present invention.

[0096] Please refer to Figure 4 , continuing the example of Figure 2 , Figure 4Highlights the connection relationship and interaction between the control switching module 110 and the switch modules 130(1)-(4) after adding the inverter 111. In this embodiment, the control switching module 110 includes two inverters 111(1) and 111(2), which are configured between the control signal output end of the control switching module 110 and multiple switch modules 130.

[0097] The inverter 111(1) is configured between the control signal output end and the switch module 130(1), and is used to convert the control signal CS output from the control signal output end into an inverse control signal (for example, when the control signal CS is the first level, the inverse control signal CS1 is the second level). The inverter 111(2) is configured between the control signal output end CS3 and the switch module 130(3), and is also used to convert the input control signal into an inverse control signal (for example, when the control signal CS is the first level, the inverse control signal CS3 is the second level). The control signal output ends CS2 and CS4 are directly connected to the switch modules 130(2) and 130(4) without passing through an inverter (for example, when the control signal CS is the first level, the control signals CS2 and CS4 remain at the first level).

[0098] This configuration enables the control switching module 110 to simultaneously control the different switch states of multiple switch modules 130(1)-130(4) through a single control signal. For example, when the control switching module 110 outputs the first level through the control signal CS:

[0099] The switch modules 130(2) and 130(4) directly receive the control signals CS2 and CS4 of the first level and enter the conducting state.

[0100] The switch modules 130(1) and 130(3) receive the control signals CS1 and CS3 of the second level through the inverters 111(1) and 111(2) and enter the off state.

[0101] Conversely, when the control signal CS outputs the second level, the switch modules 130(1) and 130(3) will conduct, while 130(2) and 130(4) will be off.

[0102] In other words, through the configuration of the inverter, the signals received by the switch modules corresponding to the channel groups with the same sequential numbers of the multiple PCIe slots are the same. For example, the channel group 151(1) is the first channel group of the PCIe slot 150(1), and the channel group 151(3) is the first channel group of the PCIe slot 150(2). The channel groups 151(1) and 151(3) with the same sequential number (both are the first channel group) respectively correspond to the switch modules 130(1) and 130(3), and the switch modules 130(1) and 130(3) receive control signals of the same level.

[0103] This design greatly simplifies the control logic, allowing the control switching module 110 to use fewer control signal output ports to achieve flexible control of multiple switch modules and corresponding channel groups.

[0104] The switch module 130 is a key component in the test adapter device 100 for controlling the power supply state of the interface adapter module 140. The following uses Figure 5 to elaborate on its details.

[0105] Figure 5 It is a circuit schematic diagram of the switch module shown according to the embodiments of the present invention.

[0106] Please refer to Figure 5 In one embodiment, as Figure 5 shown, the switch module 130 includes:

[0107] A power input terminal Vin for receiving power from the power input module 160;

[0108] A power output terminal Vout for outputting power to the corresponding interface adapter module 140;

[0109] A control terminal for receiving control signals CS1 - CS4 from the control switching module 110;

[0110] An N-type metal oxide semiconductor (NMOS) transistor (also called, the first switching transistor) 131;

[0111] A P-type metal oxide semiconductor (PMOS) transistor (also called, the second switching transistor) 132;

[0112] Resistors R1 (also called, the first resistor), R2 (also called, the second resistor), R3 (also called, the third resistor); and

[0113] Capacitors C1 (also called, the first capacitor), C2 (also called, the second capacitor).

[0114] The source (also called, the first node) S1 of the NMOS transistor 131 is grounded, the drain (also called, the second node) D1 is connected to the gate (also called, the control terminal) G2 of the PMOS transistor 132 through the resistor R2, the gate (also called, the control terminal) G1 of the NMOS is connected to the control terminal, and the control terminal is used to receive the control signals CS1, CS2, CS3 or CS4. The source S2 of the PMOS transistor 132 is connected to the power input terminal Vin, and the drain D2 is connected to the power output terminal Vout.

[0115] One end of resistor R1 is connected to the power input terminal Vin, and the other end is connected to the drain D1 of NMOS transistor 131 and one end of resistor R2. The other end of resistor R2 is connected to the gate G2 of PMOS transistor 132. The first end of capacitor C1 is further connected between the source S2 of the PMOS transistor 132 and the power input terminal Vin, and the second end of the capacitor C1 is grounded. Wherein, the first end of capacitor C2 is further connected between the drain D2 of the PMOS transistor 132 and the power output terminal Vout, and the second end of the capacitor C2 is grounded. Wherein, the first end of resistor R3 is further connected between the drain D2 of the PMOS transistor 132 and the power output terminal Vout, and the second end of the resistor R3 is grounded.

[0116] Assume that there is a power input at the Vin terminal. Different levels of control signals CS1 to CS4 will result in different operating states of NMOS transistor 131 and PMOS transistor 132:

[0117] (1) When the control signals CS1 to CS4 are at a high level (also known as the first level):

[0118] The NMOS transistor 131 is turned on, and the voltage at its drain D1 decreases and approaches the ground potential.

[0119] The voltage at the gate G2 of the PMOS transistor 132 decreases, far lower than the voltage of its source S2 (Vin), causing the PMOS to turn on.

[0120] Current flows from the power input terminal Vin through the PMOS transistor 132 to the power output terminal Vout to supply power to the corresponding interface transfer module 140.

[0121] (2) When the control signals CS1 to CS4 are at a low level (also known as the second level):

[0122] The NMOS transistor 131 is turned off and does not conduct.

[0123] Since there is a power input at Vin, through resistor R1, the voltage at the gate G2 of the PMOS transistor 132 increases and approaches the Vin voltage, causing the PMOS to turn off.

[0124] The current between the power input terminal Vin and the power output terminal Vout is cut off, and the corresponding interface transfer module 140 stops being powered.

[0125] This design allows the control switching module 110 to precisely control the power supply state of each interface transfer module 140 by changing the levels of the control signals CS1 to CS4. In this embodiment, resistors R1 and R2 form a voltage divider circuit to ensure that the gate voltage of the PMOS transistor 132 is within an appropriate range. Resistor R3 serves as a pull-down resistor to ensure that the Vout terminal does not float when the PMOS is turned off. Capacitors C1 and C2 are used for filtering to reduce power supply ripple and improve circuit stability.

[0126] Figure 6 A block diagram of the host system as shown in the embodiments of the present invention.

[0127] Please refer to Figure 6 , the host system 200 is the core control unit of the entire test system, responsible for managing and controlling the test process. In one embodiment, the host system 200 includes: a processor 210 for executing test control programs and data processing; a host memory 220 for storing test programs, test data, and test results; and a host USB interface 230 for data communication and control with the test transfer device 100.

[0128] The host USB interface 230 includes two main connection ports:

[0129] The first port: for bidirectional data transfer with the USB hub module 120. Through this first port, the host system 200 can send test data TD to the storage device 300 to be tested and analyze and generate test results accordingly.

[0130] The second port: specifically for communication with the control switching module 110. Through this second port, the host system 200 can send a test instruction CC1 to the control switching module 110.

[0131] The processor 210 is electrically connected to the host memory 220 and the host USB interface 230. The processor 210 can execute various code modules stored in the host memory 220, including but not limited to:

[0132] An instruction receiving module for receiving an integrated instruction containing information about the target storage device (the storage device to be tested this time) and test item information;

[0133] A configuration analysis module for determining the corresponding PCIe slot and its corresponding channel group according to the target storage device information, and determining the required bandwidth requirements according to the test item information;

[0134] A resource allocation module for determining the number of interface transfer modules 140 to be enabled and the corresponding switch modules 130 based on the analysis results of the configuration analysis module;

[0135] A control signal generation module, which is used to generate a control signal according to the determination result of the resource allocation module, and send the control signal to the corresponding switch module 130 through the control switching module 110;

[0136] A data processing module, which is used to send the test data TD to the enabled interface transfer module 140 through the USB hub module 120, and receive and analyze the response test data TD from the target storage device 300;

[0137] A test result analysis module, which is used to generate a test result report according to the analysis result based on the response data.

[0138] In actual operation, the processor 210 sends the test data TD and the corresponding instructions to the USB hub module 120 through the first port of the host USB interface 230 according to the test program stored in the host memory 220. At the same time, the processor 210 sends the test instruction CC1 to the control switching module 110 through the second port to manage the switch states of the switch modules 130(1) to 130(4) in the test transfer device 100, so as to enable the corresponding channel group for testing. The processor 210 is also responsible for receiving the test data TD returned from the test transfer device 100, analyzing and processing it, and storing the analysis result in the host memory 220.

[0139] For example, assume the format of the test instruction CC1 is as follows:

[0140] CC1 = {operation type, target storage device, target channel group, test mode}

[0141] Where:

[0142] Operation type: can be "enable" or "disable"; Target storage device: specifies the storage device to be tested, such as "storage device 300(1)" or "storage device 300(2)"; Target channel group: specifies the channel group to be tested, such as "channel group 151(1)" or "channel group 151(2)", etc.; Test mode: specifies the specific test mode, such as "read performance test" or "write durability test", etc.

[0143] Example test instruction:

[0144] CC1 = {enable, storage devices 300(1), 300(3), channel groups 151(1), 151(3), write performance test}

[0145] After receiving this test instruction, the control switching module 110 will perform the following processing:

[0146] Parse the test instruction CC1 to determine that it is necessary to enable the interface transfer module corresponding to channel groups 151(1) and 151(3) of storage devices 300(1) and 300(2).

[0147] Search the system configuration to determine that the channel group 151(1) corresponds to interface transfer modules 140(1) and 140(3), which are powered by switch modules 130(1) and 130(3).

[0148] Generate corresponding control signals:

[0149] CS1 = high level (used to enable switch module 130(1));

[0150] CS2 = low level (to keep switch module 130(2) off);

[0151] CS3 = high level (used to enable switch module 130(3));

[0152] CS4 = low level (to keep switch module 130(4) off).

[0153] Send the generated control signals CS1~CS4 to the corresponding switch modules 130(1)~130(4).

[0154] After receiving the high-level CS1 and CS3 signals, switch modules 130(1) and 130(3) conduct, allowing power to flow from the power input module 160 to interface transfer modules 140(1) and 140(3).

[0155] After being powered, interface transfer modules 140(1) and 140(3) start to work, enabling channel groups 151(1) and 151(3) to interact with the host system 200 for test data TD, thereby performing the specified write performance test.

[0156] At the same time, since CS2 and CS4 are at low level, switch modules 130(2) and 130(4) remain disconnected, and the corresponding interface transfer modules 140(2) and 140(4) do not work, and the corresponding channel groups 151(2) and 151(4) do not participate in this test either.

[0157] In this way, the control switching module 110 can flexibly control the working states of different channel groups according to the test instruction CC1 of the host system 200, achieving the purpose of accurately testing specific channels of the specified storage device. This design not only improves the flexibility and accuracy of the test, but also optimizes the energy efficiency of the system by selectively enabling the required hardware resources.

[0158] Figure 7It is a block diagram of a USB hub module shown in an embodiment of the present utility model.

[0159] In one embodiment, as Figure 7 shown, the USB hub module 120 is a key component in the test adapter device 100, and is used to implement data communication between the host system 200 and multiple interface adapter modules 140.

[0160] The USB hub module 120 includes:

[0161] An upstream interface 121: used to connect to the host USB interface 230 of the host system 200. Through this interface, the USB hub module 120 can perform two-way data communication with the host system 200.

[0162] A hub control module 122: responsible for managing the data flow of the entire USB hub module 120. It receives instructions and data from the upstream interface 121 and decides how to allocate this data to each downstream USB interface.

[0163] A high-speed routing module 123: routes data to the specified downstream USB interface efficiently according to the instructions of the hub control module 122. This module ensures the high speed and accuracy of data transmission.

[0164] Multiple USB interfaces 124(1), 124(2), 124(3), 124(4): These are downstream interfaces, which are respectively connected to the corresponding interface adapter modules 140(1), 140(2), 140(3), 140(4). Each USB interface is responsible for data exchange with an interface adapter module.

[0165] In one embodiment, the working process of the USB hub module 120 is as follows:

[0166] The host system 200 sends test data and instructions corresponding to the test data (such as a write instruction to write the test data to a specific physical address) to the upstream interface 121 through the host USB interface 230.

[0167] The upstream interface 121 passes the received data to the hub control module 122.

[0168] The hub control module 122 parses the instructions to determine the target interface adapter module of the data.

[0169] The hub control module 122 instructs the high-speed routing module 123 to forward the data to the corresponding USB interface 124.

[0170] The high-speed routing module 123 efficiently distributes the data to the designated USB interface 124 ( 1 ), 124 ( 2 ), 124 ( 3 ) or 124 ( 4 ) according to the instruction.

[0171] Each USB interface 124 transmits data to a corresponding interface adapter module 140 .

[0172] When the interface adapter module 140 has data to return, the process is performed in reverse order, and the data is finally transmitted back to the host system 200 .

[0173] This design enables the USB hub module 120 to efficiently manage the data flows of multiple interface adapter modules 140, and realizes parallel communication between the host system 200 and multiple storage devices 300. Through the coordinated work of the hub control module 122 and the high-speed routing module 123, the system can flexibly allocate bandwidth resources and optimize data transmission efficiency.

[0174] In addition, the structural design of the USB hub module 120 also provides a basis for the expansibility of the system. By adding more USB interfaces 124 , the system can be easily expanded to support more interface adapter modules 140 , thereby testing more storage devices 300 .

[0175] In one embodiment, the interface adapter module 140 of the present invention uses a high-performance chip that supports the latest PCIe standard and USB standard. In one embodiment, the interface adapter module 140 uses an ASMedia ASM2464 chip that supports PCIe 4.0 and USB 3.2Gen 2x2 standards.

[0176] The ASM2464 chip has the following features:

[0177] PCIe interface: Supports PCIe 4.0x4 channels, backward compatible with PCIe 3.0, 2.0 and 1.1 standards. The PCIe 4.0 standard provides a transfer rate of 16GT / s per channel, and four channels can provide a total bandwidth of up to 64GT / s.

[0178] USB interface: Supports USB 3.2Gen 2x2 standard, providing a transfer rate of up to 20Gbps. It is also backward compatible with USB 3.2Gen 2, USB 3.2Gen 1, USB 2.0 and USB 1.1 standards.

[0179] Protocol conversion: Able to efficiently convert PCIe protocol to USB protocol and vice versa to ensure the integrity and correctness of data transmission.

[0180] Low latency: Using advanced data processing algorithms to minimize delays during protocol conversion.

[0181] Power consumption management: Supports advanced power management functions and can dynamically adjust power consumption according to the workload.

[0182] In this embodiment, the interface adapter module 140 is configured as follows:

[0183] PCIe side: Connected to two channels (such as channel group 151(1) or 151(2)) of the PCIe slot 150. Each channel provides a bandwidth of 8 Gbps, and the total bandwidth of the channel group is 16 Gbps.

[0184] USB side: The output is in accordance with the USB 3.2 standard, providing a bandwidth of 20 Gbps, and is connected to a USB interface 124 of the USB hub module 120. That is to say, the USB side can support the data transmission requirements of one channel group of the PCIe slot 150 (20 Gbps > 16 Gbps).

[0185] This configuration makes full use of the performance of the ASM2464 chip and also matches the overall design of the test adapter device 100. By using a chip that supports the latest standard, the present utility model ensures that the test adapter device 100 can meet the test requirements of high-performance storage devices for a period of time in the current and future.

[0186] At the same time, since the ASM2464 chip supports downward compatibility with earlier versions of the PCIe and USB standards, the test adapter device 100 can also test storage devices using older standards. This flexibility enables this test adapter device to adapt to various storage devices with different specifications and generations, greatly expanding its application scope. In addition, the high-performance characteristics of the ASM2464 chip also ensure that when performing parallel testing of multiple devices, the interface adapter module 140 will not become the bottleneck of the system. This plays a key role in improving the overall test efficiency, especially when testing high-performance PCIe 3.0 SSDs.

[0187] In another embodiment of the present utility model, the interface adapter module 140 can not only adopt the ASMedia ASM2464 chip, but also select other chips that support PCIe and USB protocol conversion according to specific requirements.

[0188] In one embodiment, in the test adapter device 100 of the present utility model, the channels of the PCIe slot 150 are grouped into multiple channel groups 151. This grouping method is determined based on the highest supported bandwidth of the USB interface 124 and the highest supported bandwidth of the PCIe channels to ensure the efficiency of data transmission and the optimal utilization of system resources.

[0189] Specifically, the total number of multiple channels grouped into the same channel group 151 needs to meet the following condition: the total number of channels × the highest supported bandwidth of each channel ≤ the highest supported bandwidth of the corresponding USB interface.

[0190] This design ensures that the interface conversion module 140 will not exceed the bandwidth limit of the USB interface 124 during protocol conversion, thus avoiding data transmission bottlenecks. Specifically, the total number of the multiple channels grouped into the same channel group is the first quantity, and the first quantity is the maximum number of the multiple channels that can be supported without exceeding the limit of the highest supported bandwidth of each USB interface.

[0191] The following uses a specific example to illustrate this grouping method:

[0192] Suppose the test adapter device 100 has the following specifications:

[0193] The PCIe slot 150 supports the PCIe Gen3 x4 standard, and the highest supported bandwidth of each lane is 8 Gbps.

[0194] The USB interface 124 of the USB hub module 120 supports the USB 3.2 standard, and the highest supported bandwidth is 20 Gbps.

[0195] The upstream interface 121 of the USB hub module 120 connecting to the host system 200 supports the USB 4.0 standard, and the bandwidth is 40 Gbps.

[0196] In this case, the channel grouping can be carried out in the following manner:

[0197] Each channel group 151 can contain 2 PCIe channels:

[0198] 2 channels × 8 Gbps = 16 Gbps < 20 Gbps (the highest bandwidth of the USB 3.2 interface)

[0199] Channel grouping example:

[0200] Channel group 151(1): contains channel lane0 and channel lane1 of the PCIe slot 150(1)

[0201] Channel group 151(2): contains channel lane2 and channel lane3 of the PCIe slot 150(1)

[0202] Channel group 151(3): contains channel lane0 and channel lane1 of the PCIe slot 150(2)

[0203] Channel group 151(4): contains channel lane2 and channel lane3 of the PCIe slot 150(2)

[0204] This grouping method allows the test transfer device 100 to verify two PCIe Gen3 x4 solid-state drives (e.g., storage devices 300(1) to 300(2)) simultaneously. For example, when it is necessary to test two solid-state drives simultaneously, the following arrangement (testing specific channels of the storage device) can be made:

[0205] The first group: lane0 and lane1 of the first solid-state drive (e.g., storage device 300(1)) and lane0 and lane1 of the second solid-state drive (e.g., storage device 300(2))

[0206] The second group: lane2 and lane3 of the first solid-state drive and lane2 and lane3 of the second solid-state drive

[0207] By controlling each switch module 130 through the control signal sent by the control switching module 110, different interface transfer modules 140 can be selectively enabled or disabled, thereby controlling which group of channels is verified. Each interface transfer module 140 corresponds to two channels (a channel group), enabling the control switching module 110 to flexibly control which group of channels is verified.

[0208] This design makes full use of the bandwidth capacity of the USB hub module 120. Although the upstream interface 121 (or the host USB interface 230) supports the USB 4.0 standard of 40 Gbps, in fact, only the performance of 4 lanes can be fully utilized (4 × 8 Gbps = 32 Gbps). This configuration not only optimizes the utilization of system resources but also provides flexible test configuration options, allowing the combination of different channels of multiple solid-state drives to be tested simultaneously, greatly improving the test efficiency and flexibility.

[0209] Based on the above, the technical effects of the present utility model are mainly reflected in the following aspects:

[0210] (1) Realize the simulated hot-plug function of the PCIe interface storage device:

[0211] Through the combined design of innovative power control and the USB hub module 120, the present utility model has successfully achieved the simulated hot plug operation of a PCIe interface storage device. Although it is not physically hot pluggable, this design ingeniously solves the problem that PCIe solid-state drives do not support hot plugging in traditional testing methods. Specifically, the present utility model manages the power supply state of the interface transfer module 140 by controlling the switching module 110 and the switch module 130, thereby achieving electrical isolation and reconnection of the PCIe interface storage device. This method enables the test system to simulate the effect of hot plugging without physically removing the storage device. This innovative design brings the following advantages: (a) Improved test flexibility: Testers can, through software control, "disconnect" or "connect" the storage device under test without shutting down or restarting the test system. (b) Increased test efficiency: It reduces the time and labor costs of physical plugging and unplugging operations, accelerating the test process. (c) Reduced hardware wear: It reduces the physical wear of the PCIe interface and the storage device caused by frequent physical plugging and unplugging. (d) Precise control: Through software-controlled simulated hot plugging, more precise timing control and simulation of more complex test scenarios can be achieved.

[0212] (2) Support parallel testing of multiple storage devices:

[0213] The design of the present utility model allows multiple storage devices with PCIe interfaces to be connected and tested simultaneously. Through the cooperation of the USB hub module 120 and multiple interface transfer modules 140, the system can simultaneously process the data streams of multiple storage devices, significantly improving test efficiency. This feature solves the problem in the prior art that it is difficult to verify multiple solid-state drives simultaneously.

[0214] (3) Flexible bandwidth allocation and channel management:

[0215] The present utility model adopts an innovative channel grouping method, which can flexibly allocate resources according to the bandwidth of the USB interface and the bandwidth of the PCIe channels. This design allows the system to flexibly switch between testing the partial performance of multiple devices and testing the comprehensive performance of a small number of devices, making full use of the system's bandwidth resources and improving resource utilization.

[0216] (4) Strong adaptability and compatibility with multiple standards:

[0217] The present utility model supports the latest PCIe and USB standards while maintaining backward compatibility. This enables the test adapter to adapt to storage devices of different specifications and generations, enhancing the versatility and long-term use value of the system.

[0218] (5) Simplify the requirements for test equipment:

[0219] Through the conversion of PCIe to USB, the present utility model enables ordinary computers without PCIe slots to also test PCIe interface storage devices. This greatly reduces the hardware requirements of the test equipment and makes the test process more convenient and economical.

[0220] (6) Precise control and management:

[0221] Through the design of the control switching module 110 and the switch module 130, the present utility model realizes precise control of each interface conversion module 140. This design not only improves the reliability of the system but also provides more flexibility and controllability for the test process.

[0222] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present utility model and are not intended to limit them; although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present utility model.

Claims

1. A test adapter device, applicable to testing multiple storage devices, characterized in that, Comprising: A USB hub module electrically connected to the host USB interface of the host system, the USB hub module including a plurality of USB interfaces; A plurality of PCIe slots for electrically connecting a plurality of storage devices to be tested, wherein each PCIe slot includes a plurality of channels, and the plurality of channels of each PCIe slot are grouped into a plurality of channel groups; A plurality of interface conversion modules, wherein a first interface of each interface conversion module is electrically connected to a channel group of a PCIe slot, and a second interface is electrically connected to a USB interface, and each interface conversion module is used for signal conversion between a channel group in the PCIe slot and the USB interface; A plurality of switch modules respectively electrically connected to the plurality of interface conversion modules for controlling the power supply state of the corresponding interface conversion; And A control switching module electrically connected to the plurality of switch modules for controlling the switch state of each switch module to enable a corresponding target channel group of the plurality of PCIe slots.

2. The test adapter device according to claim 1, characterized in that, The control switching module includes: A plurality of control signal output terminals electrically connected to the plurality of switch modules for respectively transmitting a plurality of control signals to the plurality of switch modules to control different switch states of the plurality of switch modules, wherein each control signal includes a first level or a second level.

3. The test adapter device according to claim 1, characterized in that The control switching module includes: One or more inverters configured between the output terminal of the control switching module for outputting a control signal and the plurality of switch modules for converting the input control signal into an anti-control signal, so that some of the plurality of switch modules receive the anti-control signal, thereby simultaneously controlling different switch states of the plurality of switch modules through a single control signal.

4. The test adapter device according to claim 3, wherein The control signals received by the switch modules corresponding to the channel groups with the same sequential number of each of the plurality of PCIe slots are the same.

5. The test adapter device according to claim 1, characterized in that The test adapter device further includes: a power input module externally connected to an external power supply for supplying power to the plurality of interface conversion modules, wherein the power input module is respectively electrically connected to the plurality of interface conversion modules through the plurality of switch modules.

6. The test adapter device according to claim 5, wherein, Each switch module includes: A first switching tube; A second switching tube; A power input terminal for accessing the power input module; and A power output terminal for accessing the corresponding interface conversion module, Wherein a first node of the first switching tube is connected to the power input terminal, a second node of the first switching tube is connected to the power output terminal, a second node of the second switching tube is connected to the control terminal of the first switching tube, a first node of the second switching tube is grounded, and the control terminal of the second switching tube is used for receiving the control signal or the anti-control signal output by the control switching module.

7. The test adapter device according to claim 6, wherein The first switching transistor is a PMOS transistor, wherein the first node of the first switching transistor is the source of the PMOS transistor, the second node of the first switching transistor is the drain of the PMOS transistor, and the control terminal of the first switching transistor is the gate of the PMOS transistor; and The second switching transistor is an NMOS transistor, wherein the first node of the second switching transistor is the source of the NMOS transistor, the second node of the second switching transistor is the drain of the NMOS transistor, and the control terminal of the second switching transistor is the gate of the NMOS transistor.

8. The test adapter device according to claim 7, characterized in that The switching module further includes: a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor, wherein the drain of the NMOS transistor is connected to the power input terminal via the first resistor, and the drain of the NMOS transistor is connected to the gate of the PMOS transistor via the second resistor, wherein a first end of the first capacitor is connected between the source of the PMOS transistor and the power input terminal, and a second end of the first capacitor is grounded, wherein a first end of the second capacitor is connected between the drain of the PMOS transistor and the power output terminal, and a second end of the second capacitor is grounded, wherein a first end of the third resistor is connected between the drain of the PMOS transistor and the power output terminal, and a second end of the third resistor is grounded.

9. The test adapter device according to claim 1, wherein, The USB hub module further includes: an upstream port interface for connecting to the host USB interface; a hub control module for managing data flow; and a high-speed routing module for distributing data from the hub control module to corresponding USB interfaces according to instructions from the hub control module.

10. The test adapter device according to claim 1, wherein Wherein the total number of the multiple channels grouped into the same channel group is a first number, and the first number is the maximum number of the multiple channels that can be supported without exceeding the maximum supported bandwidth of each USB interface.

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