USB aftermarket instrument working system

Abstract

This utility model discloses a USB aftermarket instrument cluster operating system, including a processor. The processor's display data output terminal is connected to the OLED screen's display data input terminal, and the processor's main data terminal is connected to the USB hub's main data terminal. The USB hub's transmission terminal is connected to the transmission terminal of a vehicle. The connector is used to connect to the vehicle's OBD system, and the USB hub is used to connect to the vehicle's infotainment system. It can connect to the vehicle's infotainment system via USB and has a wide range of applications.

Description

Technical Field

[0001] This utility model relates to the field of automotive instrument technology, specifically to a USB aftermarket instrument working system. Background Technology

[0002] Aftermarket instrument clusters refer to dashboard systems that are installed or modified by the user after the car leaves the factory, usually to enhance the vehicle's functionality, aesthetics, or technological feel. However, due to the different interface standards of original instrument clusters from different car manufacturers (such as CAN, LIN, LVDS, etc.), incompatibility issues between the instrument cluster and the vehicle's infotainment system are very common during the modification process. Therefore, there is an urgent need for an aftermarket instrument cluster that can be widely compatible with different car models. Utility Model Content

[0003] This utility model aims to solve the technical problems existing in the prior art, and innovatively proposes a USB aftermarket instrument working system that can connect to the vehicle's infotainment system via USB, with a wide range of applications.

[0004] To achieve the above objectives, this utility model provides a USB aftermarket instrument cluster operating system, including a processor, a processor display data output terminal connected to an OLED screen display data input terminal, a processor main data terminal connected to a USB hub main data terminal, and a USB hub transmission terminal connector for connecting to a vehicle OBD system and a USB hub for connecting to a car infotainment system.

[0005] In the above scheme: the first end of the connector is connected to one end of the transient voltage suppression diode TVS2, one end of the capacitor C64, and the positive terminal of the diode D3; the negative terminal of the diode D3 is connected to one end of the inductor L6, one end of the capacitor C65, and one end of the capacitor C77; the other end of the inductor L6 is connected to the battery output power supply terminal, one end of the capacitor C66, and one end of the capacitor C86; the other ends of the transient voltage suppression diode TVS2, capacitor C64, capacitor C65, capacitor C77, capacitor C66, capacitor C86, and the second end of the connector are all connected to the power ground.

[0006] The fourth end of the connector is connected to the negative terminal of the first group of USB interfaces of the USB hub and one end of diode ESD6; the fifth end of the connector is connected to the positive terminal of the first group of USB interfaces of the USB hub and one end of diode ESD5; the sixth end of the connector is connected to the USB power supply; the eighth end of the connector is connected to the negative terminal of the second group of USB interfaces of the USB hub and one end of diode ESD8; the ninth end of the connector is connected to the positive terminal of the second group of USB interfaces of the USB hub and one end of diode ESD7; the tenth, eleventh, and twelfth ends of the connector, the other end of diode ESD6, the other end of diode ESD7, the other end of diode ESD8, and the other end of diode ESD5 are all connected to the power ground.

[0007] The above solution also includes a battery sampling circuit, which includes a resistor R51. One end of the resistor R51 is connected to the enable terminal of the processor's battery sampling signal. The other end of the resistor R51 is connected to one end of the resistor R53, one end of the capacitor C63, and the base of the transistor Q5. The other ends of the resistor R53, the other end of the capacitor C63, and the emitter of the transistor Q5 are all connected to the power supply ground. The collector of the transistor Q5 is connected to one end of the resistor R54. The other end of the resistor R54 is connected to the base of the transistor Q6, one end of the resistor R52, and one end of the capacitor C62. The emitter of the transistor Q6 is connected to the other ends of the resistor R52, the other end of the capacitor C62, and the battery output power supply terminal. The collector of the transistor Q6 is connected to one end of the resistor R56 and one end of the capacitor C67. The other end of the resistor R56 is connected to one end of the resistor R57, one end of the capacitor C91, and the processor's battery sampling signal input terminal. The other ends of the capacitor C67, the other ends of the resistor R57, and the other ends of the capacitor C91 are all connected to the power supply ground.

[0008] It also includes a USB power sampling circuit, which includes a resistor R61 with one end connected to the enable terminal of the processor's USB power sampling signal, the other end of the resistor R61 connected to one end of the resistor R59, one end of the capacitor C74, and the base of the transistor Q8, the other end of the resistor R59, the other end of the capacitor C74, and the emitter of the transistor Q8 connected to power ground, the collector of the transistor Q8 connected to one end of the resistor R58, the other end of the resistor R58 connected to the base of the transistor Q7 and one end of the resistor R60, the emitter of the transistor Q7 connected to the other end of the resistor R60, the USB power supply, and one end of the diode ESD9, the other end of the diode ESD9 connected to power ground, the collector of the transistor Q7 connected to one end of the resistor R62 and one end of the capacitor C75, the other end of the resistor R62 connected to one end of the resistor R63, one end of the capacitor C92, and the processor's USB power sampling signal input terminal, and the other ends of the capacitor C75, the other ends of the resistor R63, and the other ends of the capacitor C92 all connected to power ground.

[0009] The above solution also includes a power supply module, which comprises a first DC-DC converter voltage input terminal connected to the battery output power supply terminal, one end of capacitor C45, one end of capacitor C46, ​​one end of capacitor C47, and one end of capacitor C48. The other ends of capacitors C45, C46, ​​C47, and C48 are all connected to power ground. The enable terminal of the first DC-DC converter is connected to the first terminal of switching diode D2 and one end of resistor R39. The second terminal of switching diode D2 is connected to the USB power supply. The third terminal of switching diode D2 is connected to the processor's 3.3V enable terminal. The power supply voltage of the first DC-DC converter is connected to one end of capacitor C44, and the other end of capacitor C44 and the other end of resistor R39... The first DC-DC converter's ground terminal is connected to the power supply ground. The first DC-DC converter's BOOT terminal is connected to one end of resistor R34. The other end of resistor R34 is connected to one end of capacitor C38. The other end of capacitor C38 is connected to the first DC-DC converter's SW terminal and one end of inductor L2. The other end of inductor L2 outputs a 3.3V voltage and is connected to one end of resistor R35, one end of capacitor C40, one end of capacitor C41, one end of capacitor C42, and one end of capacitor C43. The first DC-DC converter's feedback terminal is connected to the other end of resistor R35 and one end of resistor R36. The other ends of resistor R36, capacitor C40, capacitor C41, capacitor C42, and capacitor C43 are all connected to the power supply ground.

[0010] In the above scheme: the power supply module further includes a second DC-DC converter voltage input terminal connected to the other end of inductor L2, one end of capacitor C31, one end of capacitor C32, and one end of resistor R28. The other ends of capacitor C31 and C32, the ground terminal of the second DC-DC converter, and the MODE terminal of the second DC-DC converter are all connected to the power supply ground. The other end of resistor R28 is connected to the enable terminal of the second DC-DC converter. The PG terminal of the second DC-DC converter is the SOC power supply enable terminal, connected to resistor R29. The second DC-DC converter's SW terminal is connected to one end of inductor L1. The other end of inductor L1 outputs a 1.3V voltage and is connected to the other end of resistor R29, one end of resistor R31, one end of capacitor C33, one end of capacitor C34, and one end of capacitor C35. The feedback terminal of the second DC-DC converter is connected to the other end of capacitor C33, the other end of resistor R31, and one end of resistor R30. The ground terminal of the second DC-DC converter, the other end of resistor R30, the other end of capacitor C34, and the other end of capacitor C35 are all connected to the power supply ground.

[0011] The PG terminal of the second DC-DC converter is connected to the enable signal input terminal of the SOC power supply enable circuit. The SOC power supply enable circuit includes a resistor R44, one end of which is connected to the PG terminal of the second DC-DC converter. The other end of the resistor R44 is connected to one end of the capacitor C51 and the base of the transistor Q2. The other end of the capacitor C51 and the emitter of the transistor Q2 are both connected to the power supply ground. The collector of the transistor Q2 is connected to one end of the resistor R40. The other end of the resistor R40 is connected to the gate of the field-effect transistor Q1, one end of the resistor R41, and one end of the capacitor C49. The source of the transistor Q1 is connected to the other end of the resistor R41, the other end of the capacitor C49, and the other end of the inductor L2. The drain of the transistor Q1 is the SOC 3.3V power supply terminal, used to power the processor, and is connected to one end of the resistor R42 and one end of the capacitor C50. The other ends of the resistor R42 and the other end of the capacitor C50 are both connected to the power supply ground.

[0012] In the above scheme: the working voltage terminal of the USB hub is connected to one end of resistor R64, one end of capacitor C78, ​​and one end of capacitor C76; the other end of resistor R64 is connected to the other end of inductor L2; the exposed pad port of the USB hub is connected to the other end of capacitor C78, ​​one end of capacitor C79, the other end of capacitor C76, one end of capacitor C87, and power ground; the V5 terminal of the USB hub is connected to the other end of capacitor C79, the other end of capacitor C87, and one end of resistor R64; the first terminal of the USB hub is connected to one end of resistor R73, the normally open terminal of crystal oscillator Y3, and one end of capacitor C90; the other end of capacitor C90 and the first terminal of crystal oscillator Y3 are both connected to power ground; the second terminal of the USB hub is connected to the other end of resistor R73, the normally open terminal of crystal oscillator Y3, and one end of capacitor C89; the other end of capacitor C89 and the third terminal of crystal oscillator Y3 are both connected to power ground.

[0013] The negative terminal of the main USB port of the USB hub is connected to the negative terminal of the main USB port of the processor, and the positive terminal of the main USB port of the USB hub is connected to the positive terminal of the main USB port of the processor.

[0014] In the above scheme: the 3.3V positive power supply terminal of the processor power unit is connected to the drain of transistor Q1, one end of capacitor C20, one end of capacitor C19, one end of capacitor C18, one end of capacitor C17, and one end of capacitor C16. The other ends of capacitors C20, C19, C18, C17, and C16 are all connected to power ground. The 3.3V analog circuit power supply terminal of the processor power unit is connected to one end of resistor R7, one end of capacitor C14, and one end of capacitor C15. The other end of resistor R7 is connected to the drain of transistor Q1. The 3.3V power supply terminal of the processor power unit... The PLL power supply terminal is connected to one end of resistor R6 and one end of capacitor C13. The other end of resistor R6 is connected to the drain of transistor Q1. The other ends of capacitors C13, C14, and C15 are all connected to power ground. The processor power unit operating voltage terminal is connected to the other end of inductor L1, one end of capacitor C12, one end of capacitor C11, one end of capacitor C10, and one end of capacitor C9. The other ends of capacitors C12, C11, C10, and C9 are all connected to power ground. The processor power unit 1.2V analog power supply terminal is connected to one end of capacitor C8 and one end of capacitor C7. The other ends of capacitors C8 and C7 are both connected to power ground.

[0015] The processor power supply unit's SDVREF terminal is connected to one end of resistor R2, one end of resistor R1, and one end of capacitor C5. The other ends of resistor R1 and capacitor C5 are both connected to power ground. The other end of resistor R2 is connected to one end of resistor R27, and the other end of resistor R27 is connected to the processor power supply unit's 1.8VDDR terminal. The processor power supply unit's AVDD_RTC terminal is connected to one end of resistor R3 and one end of capacitor C6. The other end of resistor R3 is connected to the drain of transistor Q1. The processor power supply unit's AVSS_RTC terminal is connected to one end of resistor R4. The processor power supply unit's pad port, the other end of resistor R4, and the other end of capacitor C6 are all connected to power ground.

[0016] The first BOOT terminal of the processor System unit is connected to one end of resistor R8 and the first end of terminal block P1. The other end of resistor R8 is connected to the drain of transistor Q1. The second end of terminal block P1 is connected to power ground. The second BOOT terminal of the processor System unit is connected to one end of resistor R9 and the first end of terminal block P2. The other end of resistor R9 is connected to the drain of transistor Q1. The second end of terminal block P2 is connected to power ground. The oscillator input terminal of the processor System unit is connected to one end of resistor R12, the first end of crystal Y1, and one end of capacitor C24. The other end of capacitor C24 and the normally open end of crystal Y1 are both connected to power ground. The oscillator output terminal of the processor System unit is connected to the other end of resistor R12, the second end of crystal Y1, and one end of capacitor C25. The other end of capacitor C25 and the normally open end of crystal Y3 are both connected to power ground.

[0017] The test clock terminal of the processor System unit debug port is connected to one end of resistor R95. The other end of resistor R95 is connected to one end of resistor R84 and the sixth terminal of terminal block P3, and is connected to an external debugging device through terminal block P3. The other end of resistor R84 is connected to the cathode of diode D4, and the anode of diode D4 is connected to the drain of transistor Q1. The test data output terminal of the processor System unit debug port is connected to one end of resistor R94. The other end of resistor R94 is connected to one end of resistor R85 and the fifth terminal of terminal block P3, and the other end of resistor R85 is connected to the cathode of diode D4. The test data input terminal of the processor System unit debug port is connected to one end of resistor R93. The other end of resistor R93 is connected to one end of resistor R86 and the fourth terminal of terminal block P3, and the other end of resistor R86 is connected to... Connect the negative terminal of diode D4; the test mode selection terminal of the processor System unit debug port is connected to one end of resistor R92, the other end of resistor R92 is connected to one end of resistor R87 and the third terminal of terminal block P3, and the other end of resistor R87 is connected to the negative terminal of diode D4; the test reset terminal of the processor System unit debug port is connected to one end of resistor R91, the other end of resistor R91 is connected to the second terminal of terminal block P3, one end of resistor R89 ​​and the negative terminal of diode D4, and the other end of resistor R89 ​​is connected to power ground; the seventh terminal of terminal block P3 is the system reset switch terminal, connected to one end of resistor R83, and the other end of resistor R83 is connected to the negative terminal of diode D4; the eighth terminal of terminal block P3 is the clock coordination terminal, connected to one end of resistor R90, and the other end of resistor R90 and the ninth terminal of terminal block P3 are connected to power ground.

[0018] The above scheme also includes a memory; the processor memory unit's chip select signal terminal is connected to the memory chip select signal terminal and one end of resistor R24, the other end of resistor R24 ​​is connected to the memory power supply voltage terminal; the processor memory unit's storage clock terminal is connected to the memory clock terminal; the processor memory unit's first storage signal terminal is connected to the memory input terminal; the processor memory unit's second storage signal terminal is connected to the memory output terminal and one end of resistor R25, the other end of resistor R25 is connected to the power supply ground; the processor memory unit's third storage signal terminal is connected to the memory write-protect input terminal and one end of resistor R22. The other end of resistor R22 is connected to the memory power supply voltage terminal. The fourth storage signal terminal of the processor storage unit is connected to the memory reset terminal and one end of resistor R23. The other end of resistor R23 is connected to the memory power supply voltage terminal. The memory power supply voltage terminal is connected to one end of ferrite bead FB2, one end of capacitor C26, and one end of capacitor C27. The other end of ferrite bead FB2 is connected to the negative terminal of diode D1 and one end of capacitor C28. The positive terminal of diode D1 is connected to the drain of transistor Q1. The memory ground terminal, the other end of capacitor C26, the other end of capacitor C27, and the other end of capacitor C28 are all connected to the power supply ground.

[0019] In summary, the beneficial effects of this utility model are as follows: it enables connection to a vehicle's infotainment system via a USB interface. The USB interface is a universal standard interface, used by almost all existing electronic devices. Cars inevitably have USB interfaces pre-installed, reducing the requirements for pre-installed interfaces on the vehicle body compared to traditional car dashboard connections, thus improving installation convenience and compatibility. Furthermore, the USB interface allows for future replacement with a USB 3.0 interface as needed, providing faster data transfer rates when large amounts of data are required. In addition, the USB connection allows for expansion as needed, enabling the connection of other USB devices through a single USB interface, increasing connection flexibility. Moreover, the USB cable also provides power, addressing both data transfer and power supply needs while minimizing wiring. Attached Figure Description

[0020] Figure 1 This is a system diagram of this utility model.

[0021] Figure 2 This is the circuit diagram for the connector.

[0022] Figure 3 This is the circuit diagram of the battery sampling circuit.

[0023] Figure 4 This is a circuit diagram of a USB power sampling circuit.

[0024] Figure 5 This is the circuit diagram of the first DC-DC converter.

[0025] Figure 6 This is the circuit diagram of the second DC-DC converter.

[0026] Figure 7 This is the circuit diagram of the SOC power supply enable circuit.

[0027] Figure 8 This is a circuit diagram for a USB hub.

[0028] Figure 9 This is a circuit diagram of the processor power supply unit.

[0029] Figure 10 This is the circuit diagram of the System unit of the processor.

[0030] Figure 11 This is a circuit diagram of the processor's serial communication unit.

[0031] Figure 12 This is a circuit diagram of the processor's memory unit.

[0032] Figure 13 This is a circuit diagram of a memory.

[0033] Figure 14 This is a circuit diagram of the processor and the OLED. Detailed Implementation

[0034] The present invention will be further described below with reference to embodiments and accompanying drawings:

[0035] like Figures 1-14 As shown, a USB aftermarket instrument cluster operating system includes a processor U1, a display data output terminal of the processor U1 connected to an OLED screen display data input terminal, a main data terminal of the processor U1 connected to a main data terminal of a USB hub U7, a transmission terminal connector P7 of the USB hub U7, the connector P7 being used to connect to the vehicle's OBD system, and the USB hub U7 being used to connect to the vehicle's infotainment system.

[0036] The first terminal of connector P7 is connected to one end of transient voltage suppressor diode TVS2, one end of capacitor C64, and the positive terminal of diode D3. The negative terminal of diode D3 is connected to one end of inductor L6, one end of capacitor C65, and one end of capacitor C77. The other end of inductor L6 is connected to the battery output power supply terminal, one end of capacitor C66, and one end of capacitor C86. The other ends of transient voltage suppressor diode TVS2, capacitor C64, capacitor C65, capacitor C77, capacitor C66, capacitor C86, and the second terminal of connector P7 are all connected to the power ground.

[0037] Connector P7, pin 4, connects to the negative terminal of the first USB port of USB hub U7 and one end of diode ESD6; connector P7, pin 5, connects to the positive terminal of the first USB port of USB hub U7 and one end of diode ESD5; connector P7, pin 6, connects to the USB power supply; connector P7, pin 8, connects to the negative terminal of the second USB port of USB hub U7 and one end of diode ESD8; connector P7, pin 9, connects to the positive terminal of the second USB port of USB hub U7 and one end of diode ESD7; connector P7, pins 10, 11, and 12, the other end of diode ESD6, the other end of diode ESD7, the other end of diode ESD8, and the other end of diode ESD5 are all connected to power ground.

[0038] It also includes a battery sampling circuit, which includes a resistor R51 connected at one end to the enable terminal of the processor U1 battery sampling signal, the other end of resistor R51 connected to one end of resistor R53, one end of capacitor C63 and the base of transistor Q5, the other end of resistor R53, the other end of capacitor C63 and the emitter of transistor Q5 connected to the power supply ground, the collector of transistor Q5 connected to one end of resistor R54, the other end of resistor R54 connected to the base of transistor Q6, one end of resistor R52 and one end of capacitor C62, the emitter of transistor Q6 connected to the other end of resistor R52, the other end of capacitor C62 and the battery output power supply terminal, the collector of transistor Q6 connected to one end of resistor R56 and one end of capacitor C67, the other end of resistor R56 connected to one end of resistor R57, one end of capacitor C91 and the battery sampling signal input terminal of processor U1, and the other end of capacitor C67, the other end of resistor R57 and the other end of capacitor C91 connected to the power supply ground;

[0039] It also includes a USB power sampling circuit. The USB power sampling circuit includes a resistor R61, one end of which is connected to the enable terminal of the processor U1 USB power sampling signal. The other end of the resistor R61 is connected to one end of the resistor R59, one end of the capacitor C74, and the base of the transistor Q8. The other ends of the resistor R59, the other end of the capacitor C74, and the emitter of the transistor Q8 are all connected to the power ground. The collector of the transistor Q8 is connected to one end of the resistor R58. The other end of the resistor R58 is connected to the base of the transistor Q7 and one end of the resistor R60. The emitter of the transistor Q7 is connected to the other end of the resistor R60, the USB power supply, and one end of the diode ESD9. The other end of the diode ESD9 is connected to the power ground. The collector of the transistor Q7 is connected to one end of the resistor R62 and one end of the capacitor C75. The other end of the resistor R62 is connected to one end of the resistor R63, one end of the capacitor C92, and the processor U1 USB power sampling signal input terminal. The other ends of the capacitor C75, the other ends of the resistor R63, and the other ends of the capacitor C92 are all connected to the power ground.

[0040] It also includes a power supply module, which includes a first DC-DC converter U3 whose voltage input terminal is connected to the battery output power supply terminal, one end of capacitor C45, one end of capacitor C46, ​​one end of capacitor C47, and one end of capacitor C48. The other ends of capacitors C45, C46, ​​C47, and C48 are all connected to the power ground. The enable terminal of the first DC-DC converter U3 is connected to the first terminal of switching diode D2 and one end of resistor R39. The second terminal of switching diode D2 is connected to the USB power supply. The third terminal of switching diode D2 is connected to the 3.3V enable terminal of processor U1. The power supply voltage of the first DC-DC converter U3 is connected to one end of capacitor C44. The other end of capacitor C44, the other end of resistor R39, and the first... The ground terminal of DC-DC converter U3 is connected to the power supply ground. The BOOT terminal of the first DC-DC converter U3 is connected to one end of resistor R34. The other end of resistor R34 is connected to one end of capacitor C38. The other end of capacitor C38 is connected to the SW terminal of the first DC-DC converter U3 and one end of inductor L2. The other end of inductor L2 outputs a 3.3V voltage and is connected to one end of resistor R35, one end of capacitor C40, one end of capacitor C41, one end of capacitor C42, and one end of capacitor C43. The feedback terminal of the first DC-DC converter U3 is connected to the other end of resistor R35 and one end of resistor R36. The other ends of resistor R36, capacitor C40, capacitor C41, capacitor C42, and capacitor C43 are all connected to the power supply ground.

[0041] It also includes the second DC-DC converter U4, whose voltage input terminal is connected to the other end of inductor L2, one end of capacitor C31, one end of capacitor C32, and one end of resistor R28. The other ends of capacitors C31 and C32, the ground terminal of the second DC-DC converter U4, and the MODE terminal of the second DC-DC converter U4 are all connected to power ground. The other end of resistor R28 is connected to the enable terminal of the second DC-DC converter U4. The PG terminal of the second DC-DC converter U4 is the SOC power enable terminal and is connected to one end of resistor R29. The second DC-DC converter U4SW terminal is connected to one end of inductor L1. The other end of inductor L1 outputs a 1.3V voltage and is connected to the other end of resistor R29, one end of resistor R31, one end of capacitor C33, one end of capacitor C34, and one end of capacitor C35. The feedback terminal of the second DC-DC converter U4 is connected to the other end of capacitor C33, the other end of resistor R31, and one end of resistor R30. The ground terminal of the second DC-DC converter U4, the other end of resistor R30, the other end of capacitor C34, and the other end of capacitor C35 are all connected to the power supply ground.

[0042] The second DC-DC converter U4PG terminal is connected to one end of resistor R44. The other end of resistor R44 is connected to one end of capacitor C51 and the base of transistor Q2. The other end of capacitor C51 and the emitter of transistor Q2 are both connected to the power supply ground. The collector of transistor Q2 is connected to one end of resistor R40. The other end of resistor R40 is connected to the gate of MOSFET Q1, one end of resistor R41 and one end of capacitor C49. The source of transistor Q1 is connected to the other end of resistor R41, the other end of capacitor C49 and the other end of inductor L2. The drain of transistor Q1 is the SOC 3.3V power supply terminal, used to power processor U1, and is connected to one end of resistor R42 and one end of capacitor C50. The other ends of resistor R42 and capacitor C50 are both connected to the power supply ground.

[0043] The operating voltage terminal of USB hub U7 is connected to one end of resistor R64, one end of capacitor C78, ​​and one end of capacitor C76. The other end of resistor R64 is connected to the other end of inductor L2. The exposed pad port of USB hub U7 is connected to the other end of capacitor C78, ​​one end of capacitor C79, the other end of capacitor C76, one end of capacitor C87, and power ground. The V5 terminal of USB hub U7 is connected to the other end of capacitor C79, the other end of capacitor C87, and one end of resistor R64. The first terminal of USB hub U7 is connected to one end of resistor R73, the normally open terminal of crystal oscillator Y3, and one end of capacitor C90. The other end of capacitor C90 and the first terminal of crystal oscillator Y3 are both connected to power ground. The second terminal of USB hub U7 is connected to the other end of resistor R73, the normally open terminal of crystal oscillator Y3, and one end of capacitor C89. The other end of capacitor C89 and the third terminal of crystal oscillator Y3 are both connected to power ground.

[0044] Connect the negative terminal of the main USB port of USB hub U7 to the negative terminal of the main USB port of processor U1, and connect the positive terminal of the main USB port of USB hub U7 to the positive terminal of the main USB port of processor U1.

[0045] The processor power supply unit U1A 3.3V positive power supply terminal (i.e., pins 2, 20, 38, 65, 85) is connected to the drain of transistor Q1, one end of capacitors C20, C19, C18, C17, and C16. The other ends of capacitors C20, C19, C18, C17, and C16 are all connected to ground. The processor power supply unit U1A 3.3V analog circuit power supply terminal (i.e., pin 4) is connected to one end of resistor R7, one end of capacitor C14, and one end of capacitor C15. The other end of resistor R7 is connected to the drain of transistor Q1. The processor power supply unit U1A 3.3V... The PLL power supply terminal is connected to one end of resistor R6 and one end of capacitor C13. The other end of resistor R6 is connected to the drain of transistor Q1. The other ends of capacitors C13, C14, and C15 are all connected to power ground. The processor power unit U1A operating voltage terminal is connected to the other end of inductor L1, one end of capacitor C12, one end of capacitor C11, one end of capacitor C10, and one end of capacitor C9. The other ends of capacitors C12, C11, C10, and C9 are all connected to power ground. The processor power unit U1A 1.2V analog power supply terminal is connected to one end of capacitor C8 and one end of capacitor C7. The other ends of capacitors C8 and C7 are both connected to power ground.

[0046] The processor power unit U1ASDVREF terminal is connected to one end of resistor R2, one end of resistor R1, and one end of capacitor C5. The other ends of resistor R1 and capacitor C5 are both connected to power ground. The other end of resistor R2 is connected to one end of resistor R27, and the other end of resistor R27 is connected to the processor power unit U1A1.8VDDR terminal. The processor power unit U1AAVDD_RTC terminal is connected to one end of resistor R3 and one end of capacitor C6. The other end of resistor R3 is connected to the drain of transistor Q1. The processor power unit U1AAVSS_RTC terminal is connected to one end of resistor R4. The processor power unit U1A pad port, the other end of resistor R4, and the other end of capacitor C6 are all connected to power ground.

[0047] The U1C serial communication unit of the processor is connected to one end of resistor R13 and one end of resistor R17. The other end of resistor R13 is connected to the drain of transistor Q1. One end of resistor R17 is connected to one end of diode ESD1 and the second terminal of the printer terminal block P4. The other end of diode ESD1 and the first terminal of terminal block P4 are both connected to the power supply ground. The U1C serial communication unit of the processor is connected to one end of resistor R14 and one end of resistor R18. The other end of resistor R14 is connected to the drain of transistor Q1. One end of resistor R18 is connected to one end of diode ESD2 and the third terminal of the printer terminal block P4. The other end of diode ESD2 is connected to the power supply ground.

[0048] The U1C serial communication unit's spare serial port transmitter is connected to one end of resistor R15 and one end of resistor R19. The other end of resistor R15 is connected to the drain of transistor Q1. One end of resistor R19 is connected to one end of diode ESD4 and the second terminal of spare terminal block P5. The other end of diode ESD4 and the first terminal of spare terminal block P5 are both connected to power ground. The U1C serial communication unit's printer serial port receiver is connected to one end of resistor R16 and one end of resistor R20. The other end of resistor R16 is connected to the drain of transistor Q1. One end of resistor R20 is connected to one end of diode ESD3 and the third terminal of spare terminal block P5. The other end of diode ESD3 is connected to power ground.

[0049] The processor U1 OLED power setting output is connected to the OLED screen power setting input; the processor U1 OLED reset output is connected to the OLED screen reset input; the OLED screen synchronization signal output is connected to the processor U1 OLED synchronization signal input; the processor U1 display data first channel positive output is connected to the OLED screen display data first channel positive input; the processor U1 display data first channel negative output is connected to the OLED screen display data first channel negative input; the processor U1 display data second channel positive output is connected to the OLED screen display data second channel positive input; the processor U1 display data second channel negative output is connected to the OLED screen display data second channel negative input; the processor U1 display data clock channel positive output is connected to the OLED screen display data clock channel positive input; the processor U1 display data clock channel negative output is connected to the OLED screen display data clock channel negative input.

[0050] The first BOOT terminal of the processor System unit U1B is connected to one end of resistor R8 and the first end of terminal block P1. The other end of resistor R8 is connected to the drain of transistor Q1. The second end of terminal block P1 is connected to power ground. The second BOOT terminal of the processor System unit U1B is connected to one end of resistor R9 and the first end of terminal block P2. The other end of resistor R9 is connected to the drain of transistor Q1. The second end of terminal block P2 is connected to power ground. The oscillator input terminal of the processor System unit U1B is connected to one end of resistor R12, the first end of crystal Y1, and one end of capacitor C24. The other end of capacitor C24 and the normally open terminal of crystal Y1 are both connected to power ground. The oscillator output terminal of the processor System unit U1B is connected to the other end of resistor R12, the second end of crystal Y1, and one end of capacitor C25. The other end of capacitor C25 and the normally open terminal of crystal Y3 are both connected to power ground.

[0051] The test clock terminal of the System Unit U1B debug port is connected to one end of resistor R95. The other end of resistor R95 is connected to one end of resistor R84 and terminal 6 of terminal block P3, and then connected to an external debugging device via terminal block P3. The other end of resistor R84 is connected to the cathode of diode D4, and the anode of diode D4 is connected to the drain of transistor Q1. The test data output terminal of the System Unit U1B debug port is connected to one end of resistor R94. The other end of resistor R94 is connected to one end of resistor R85 and terminal 5 of terminal block P3, and the other end of resistor R85 is connected to the cathode of diode D4. The test data input terminal of the System Unit U1B debug port is connected to one end of resistor R93. The other end of resistor R93 is connected to one end of resistor R86 and terminal 4 of terminal block P3, and the other end of resistor R86 is connected to... Connect the cathode of diode D4; connect the test mode selection terminal of the debug port of the System unit U1B to one end of resistor R92, the other end of resistor R92 to one end of resistor R87 and the third terminal of terminal block P3, and the other end of resistor R87 to the cathode of diode D4; connect the test reset terminal of the debug port of the System unit U1B to one end of resistor R91, the other end of resistor R91 to the second terminal of terminal block P3, one end of resistor R89 ​​and the cathode of diode D4, and the other end of resistor R89 ​​to power ground; the seventh terminal of terminal block P3 is the system reset switch terminal, connected to one end of resistor R83, the other end of resistor R83 to the cathode of diode D4; the eighth terminal of terminal block P3 is the clock coordination terminal, connected to one end of resistor R90, the other end of resistor R90 and the ninth terminal of terminal block P3 are connected to power ground.

[0052] The processor memory unit U1F's chip select signal terminal is connected to the memory U2's chip select signal terminal and one end of resistor R24. The other end of resistor R24 ​​is connected to the power supply voltage terminal of memory U2. The processor memory unit U1F's clock terminal is connected to the memory U2's clock terminal. The processor memory unit U1F's first storage signal terminal is connected to the memory U2's input terminal. The processor memory unit U1F's second storage signal terminal is connected to the memory U2's output terminal and one end of resistor R25. The other end of resistor R25 is connected to the power supply ground. The processor memory unit U1F's third storage signal terminal is connected to the memory U2's write-protect input terminal and one end of resistor R22. One end of resistor R22 is connected to the power supply voltage terminal of memory U2. The fourth storage signal terminal of processor storage unit U1F is connected to the reset terminal of memory U2 and one end of resistor R23. The other end of resistor R23 is connected to the power supply voltage terminal of memory U2. The power supply voltage terminal of memory U2 is connected to one end of ferrite bead FB2, one end of capacitor C26 and one end of capacitor C27. The other end of ferrite bead FB2 is connected to the negative terminal of diode D1 and one end of capacitor C28. The positive terminal of diode D1 is connected to the drain of transistor Q1. The ground terminal of memory U2, the other end of capacitor C26, the other end of capacitor C27 and the other end of capacitor C28 are all connected to the power supply ground.

Claims

1. A USB after-market instrument operating system, characterized by: It includes a processor (U1), whose display data output terminal is connected to the OLED screen display data input terminal, whose main data terminal is connected to the USB hub (U7) main data terminal, and whose transmission terminal connector (P7) is used to connect to the vehicle's OBD system. The USB hub (U7) is used to connect to the vehicle's infotainment system.

2. The USB after-market gauge operating system of claim 1, wherein: The first end of the connector (P7) is connected to one end of the transient voltage suppression diode TVS2, one end of the capacitor C64, and the positive terminal of the diode D3. The negative terminal of the diode D3 is connected to one end of the inductor L6, one end of the capacitor C65, and one end of the capacitor C77. The other end of the inductor L6 is connected to the battery output power supply terminal, one end of the capacitor C66, and one end of the capacitor C86. The other ends of the transient voltage suppression diode TVS2, capacitor C64, capacitor C65, capacitor C77, capacitor C66, capacitor C86, and the second end of the connector (P7) are all connected to the power ground. The fourth terminal of connector (P7) is connected to the negative terminal of the first group of USB interfaces of USB hub (U7) and one end of diode ESD6. The fifth terminal of connector (P7) is connected to the positive terminal of the first group of USB interfaces of USB hub (U7) and one end of diode ESD5. The sixth terminal of connector (P7) is connected to the USB power supply. The eighth terminal of connector (P7) is connected to the negative terminal of the second group of USB interfaces of USB hub (U7) and one end of diode ESD8. The ninth terminal of connector (P7) is connected to the positive terminal of the second group of USB interfaces of USB hub (U7) and one end of diode ESD7. The tenth, eleventh, and twelfth terminals of connector (P7), the other end of diode ESD6, the other end of diode ESD7, the other end of diode ESD8, and the other end of diode ESD5 are all connected to the power ground.

3. The USB aftermarket instrument operating system according to claim 2, characterized in that: It also includes a battery sampling circuit, which includes a resistor R51. One end of the resistor R51 is connected to the enable terminal of the processor (U1) for the battery sampling signal. The other end of the resistor R51 is connected to one end of the resistor R53, one end of the capacitor C63, and the base of the transistor Q5. The other ends of the resistor R53, the other end of the capacitor C63, and the emitter of the transistor Q5 are all connected to the power supply ground. The collector of the transistor Q5 is connected to one end of the resistor R54, and the other end of the resistor R54 is connected to the base of the transistor Q6. The transistor Q6 is connected to the battery output power supply terminal via one end of resistor R52 and one end of capacitor C62. The emitter of transistor Q6 is connected to the other end of resistor R52, the other end of capacitor C62, and the battery output power supply terminal. The collector of transistor Q6 is connected to one end of resistor R56 and one end of capacitor C67. The other end of resistor R56 is connected to one end of resistor R57, one end of capacitor C91, and the battery sampling signal input terminal of processor (U1). The other ends of capacitor C67, resistor R57, and capacitor C91 are all connected to power ground. It also includes a USB power sampling circuit. The USB power sampling circuit includes a resistor R61, one end of which is connected to the enable terminal of the processor (U1) for USB power sampling signals. The other end of resistor R61 is connected to one end of resistor R59, one end of capacitor C74, and the base of transistor Q8. The other ends of resistor R59, capacitor C74, and the emitter of transistor Q8 are all connected to power ground. The collector of transistor Q8 is connected to one end of resistor R58. The other end of resistor R58 is connected to the base of transistor Q7 and resistor R6. At one end, the emitter of transistor Q7 is connected to the other end of resistor R60, the USB power supply, and one end of diode ESD9. The other end of diode ESD9 is connected to power ground. The collector of transistor Q7 is connected to one end of resistor R62 and one end of capacitor C75. The other end of resistor R62 is connected to one end of resistor R63, one end of capacitor C92, and the USB power sampling signal input terminal of processor (U1). The other ends of capacitor C75, resistor R63, and capacitor C92 are all connected to power ground.

4. The USB retrofit instrument working system according to claim 1, characterized in that: It also includes a power supply module, which comprises a first DC-DC converter (U3) whose voltage input terminal is connected to the battery output power supply terminal, one end of capacitor C45, one end of capacitor C46, ​​one end of capacitor C47, and one end of capacitor C48. The other ends of capacitors C45, C46, ​​C47, and C48 are all connected to the power ground. The enable terminal of the first DC-DC converter (U3) is connected to the first terminal of switching diode D2 and one end of resistor R39. The second terminal of switching diode D2 is connected to the USB power supply. The third terminal of switching diode D2 is connected to the 3.3V enable terminal of processor (U1). The power supply voltage of the first DC-DC converter (U3) is connected to one end of capacitor C44. The other end of capacitor C44, the other end of resistor R39, and the first... The ground terminal of the DC-DC converter (U3) is connected to the power supply ground. The BOOT terminal of the first DC-DC converter (U3) is connected to one end of resistor R34. The other end of resistor R34 is connected to one end of capacitor C38. The other end of capacitor C38 is connected to the SW terminal of the first DC-DC converter (U3) and one end of inductor L2. The other end of inductor L2 outputs a 3.3V voltage and is connected to one end of resistor R35, one end of capacitor C40, one end of capacitor C41, one end of capacitor C42, and one end of capacitor C43. The feedback terminal of the first DC-DC converter (U3) is connected to the other end of resistor R35 and one end of resistor R36. The other ends of resistor R36, capacitor C40, capacitor C41, capacitor C42, and capacitor C43 are all connected to the power supply ground.

5. The USB aftermarket instrument operating system according to claim 4, characterized in that: The power supply module also includes a second DC-DC converter (U4) whose voltage input terminal is connected to the other end of inductor L2, one end of capacitor C31, one end of capacitor C32, and one end of resistor R28. The other ends of capacitor C31 and C32, the ground terminal of the second DC-DC converter (U4), and the MODE terminal of the second DC-DC converter (U4) are all connected to the power ground. The other end of resistor R28 is connected to the enable terminal of the second DC-DC converter (U4). The PG terminal of the second DC-DC converter (U4) is the SOC power supply enable terminal and is connected to resistor R29. At one end, the SW terminal of the second DC-DC converter (U4) is connected to one end of the inductor L1. The other end of the inductor L1 outputs a 1.3V voltage and is connected to the other end of the resistor R29, one end of the resistor R31, one end of the capacitor C33, one end of the capacitor C34, and one end of the capacitor C35. The feedback terminal of the second DC-DC converter (U4) is connected to the other end of the capacitor C33, the other end of the resistor R31, and one end of the resistor R30. The ground terminal of the second DC-DC converter (U4), the other end of the resistor R30, the other end of the capacitor C34, and the other end of the capacitor C35 are all connected to the power supply ground. The PG terminal of the second DC-DC converter (U4) is connected to the enable signal input terminal of the SOC power supply enable circuit. The SOC power supply enable circuit includes a resistor R44, one end of which is connected to the PG terminal of the second DC-DC converter (U4). The other end of the resistor R44 is connected to one end of the capacitor C51 and the base of the transistor Q2. The other end of the capacitor C51 and the emitter of the transistor Q2 are both connected to the power supply ground. The collector of the transistor Q2 is connected to one end of the resistor R40. The other end of the resistor R40 is connected to the gate of the field-effect transistor Q1, one end of the resistor R41, and one end of the capacitor C49. The source of the transistor Q1 is connected to the other end of the resistor R41, the other end of the capacitor C49, and the other end of the inductor L2. The drain of the transistor Q1 is the SOC 3.3V power supply terminal, used to power the processor (U1), and is connected to one end of the resistor R42 and one end of the capacitor C50. The other ends of the resistor R42 and the other end of the capacitor C50 are both connected to the power supply ground.

6. The USB retrofit instrument working system according to claim 1, characterized in that: The operating voltage terminal of the USB hub (U7) is connected to one end of resistor R64, one end of capacitor C78, ​​and one end of capacitor C76. The other end of resistor R64 is connected to the other end of inductor L2. The exposed pad port of the USB hub (U7) is connected to the other end of capacitor C78, ​​one end of capacitor C79, the other end of capacitor C76, one end of capacitor C87, and power ground. The V5 terminal of the USB hub (U7) is connected to the other end of capacitor C79, the other end of capacitor C87, and one end of resistor R64. The first terminal of the USB hub (U7) is connected to one end of resistor R73, the normally open terminal of crystal oscillator Y3, and one end of capacitor C90. The other end of capacitor C90 and the first terminal of crystal oscillator Y3 are both connected to power ground. The second terminal of the USB hub (U7) is connected to the other end of resistor R73, the normally open terminal of crystal oscillator Y3, and one end of capacitor C89. The other end of capacitor C89 and the third terminal of crystal oscillator Y3 are both connected to power ground. The negative terminal of the main USB interface of the USB hub (U7) is connected to the negative terminal of the main USB interface of the processor (U1), and the positive terminal of the main USB interface of the USB hub (U7) is connected to the positive terminal of the main USB interface of the processor (U1).

7. The USB retrofit instrument working system according to claim 1, characterized in that: The processor power supply unit (U1A) has its 3.3V positive power supply terminal connected to the drain of transistor Q1, one end of capacitors C20, C19, C18, C17, and C16. The other ends of capacitors C20, C19, C18, C17, and C16 are all connected to ground. The processor power supply unit (U1A) has its 3.3V analog circuit power supply terminal connected to one end of resistor R7, one end of capacitor C14, and one end of capacitor C15. The other end of resistor R7 is connected to the drain of transistor Q1. The processor power supply unit (U1A) has a 3.3V... The PLL power supply terminal is connected to one end of resistor R6 and one end of capacitor C13. The other end of resistor R6 is connected to the drain of transistor Q1. The other ends of capacitors C13, C14, and C15 are all connected to power ground. The processor power unit (U1A) operating voltage terminal is connected to the other end of inductor L1, one end of capacitor C12, one end of capacitor C11, one end of capacitor C10, and one end of capacitor C9. The other ends of capacitors C12, C11, C10, and C9 are all connected to power ground. The processor power unit (U1A) 1.2V analog power supply terminal is connected to one end of capacitor C8 and one end of capacitor C7. The other ends of capacitors C8 and C7 are both connected to power ground. The processor power supply unit (U1A) SDVREF terminal is connected to one end of resistor R2, one end of resistor R1, and one end of capacitor C5. The other ends of resistor R1 and capacitor C5 are both connected to power ground. The other end of resistor R2 is connected to one end of resistor R27, and the other end of resistor R27 is connected to the 1.8VDDR terminal of the processor power supply unit (U1A). The processor power supply unit (U1A) AVDD_RTC terminal is connected to one end of resistor R3 and one end of capacitor C6. The other end of resistor R3 is connected to the drain of transistor Q1. The processor power supply unit (U1A) AVSS_RTC terminal is connected to one end of resistor R4. The processor power supply unit (U1A) pad port, the other end of resistor R4, and the other end of capacitor C6 are all connected to power ground. The first BOOT terminal of the processor System unit (U1B) is connected to one end of resistor R8 and the first end of terminal block P1. The other end of resistor R8 is connected to the drain of transistor Q1. The second end of terminal block P1 is connected to power ground. The second BOOT terminal of the processor System unit (U1B) is connected to one end of resistor R9 and the first end of terminal block P2. The other end of resistor R9 is connected to the drain of transistor Q1. The second end of terminal block P2 is connected to power ground. The oscillator input terminal of the processor System unit (U1B) is connected to one end of resistor R12, the first end of crystal Y1, and one end of capacitor C24. The other end of capacitor C24 and the normally open end of crystal Y1 are both connected to power ground. The oscillator output terminal of the processor System unit (U1B) is connected to the other end of resistor R12, the second end of crystal Y1, and one end of capacitor C25. The other end of capacitor C25 and the normally open end of crystal Y3 are both connected to power ground. The test clock terminal of the processor System Unit (U1B) debug port is connected to one end of resistor R95. The other end of resistor R95 is connected to one end of resistor R84 and the sixth terminal of terminal block P3, and is connected to an external debugging device through terminal block P3. The other end of resistor R84 is connected to the cathode of diode D4, and the anode of diode D4 is connected to the drain of transistor Q1. The test data output terminal of the processor System Unit (U1B) debug port is connected to one end of resistor R94. The other end of resistor R94 is connected to one end of resistor R85 and the fifth terminal of terminal block P3, and the other end of resistor R85 is connected to the cathode of diode D4. The test data input terminal of the processor System Unit (U1B) debug port is connected to one end of resistor R93. The other end of resistor R93 is connected to one end of resistor R86 and the fourth terminal of terminal block P3, and the other end of resistor R86 is connected to the fourth terminal of terminal block P3. One end is connected to the negative terminal of diode D4; the test mode selection terminal of the processor System unit (U1B) debug port is connected to one end of resistor R92, the other end of resistor R92 is connected to one end of resistor R87 and the third terminal of terminal block P3, and the other end of resistor R87 is connected to the negative terminal of diode D4; the test reset terminal of the processor System unit (U1B) debug port is connected to one end of resistor R91, the other end of resistor R91 is connected to the second terminal of terminal block P3, one end of resistor R89 ​​and the negative terminal of diode D4, and the other end of resistor R89 ​​is connected to power ground; the seventh terminal of terminal block P3 is the system reset switch terminal, connected to one end of resistor R83, and the other end of resistor R83 is connected to the negative terminal of diode D4; the eighth terminal of terminal block P3 is the clock coordination terminal, connected to one end of resistor R90, and the other end of resistor R90 and the ninth terminal of terminal block P3 are connected to power ground.

8. The USB retrofit instrument working system according to claim 7, characterized in that: It also includes a memory (U2), a processor memory unit (U1F) whose chip select signal terminal is connected to the chip select signal terminal of the memory (U2) and one end of resistor R24, the other end of which is connected to the power supply voltage terminal of the memory (U2), a processor memory unit (U1F) whose clock signal terminal is connected to the clock signal terminal of the memory (U2), a first storage signal terminal of the processor memory unit (U1F) connected to the input terminal of the memory (U2), a second storage signal terminal of the processor memory unit (U1F) connected to the output terminal of the memory (U2) and one end of resistor R25, the other end of which is connected to the power supply ground, and a third storage signal terminal of the processor memory unit (U1F) connected to the write-protect input terminal of the memory (U2) and... One end of resistor R22 is connected to the power supply voltage terminal of memory (U2). The fourth storage signal terminal of processor storage unit (U1F) is connected to the reset terminal of memory (U2) and one end of resistor R23. The other end of resistor R23 is connected to the power supply voltage terminal of memory (U2). The power supply voltage terminal of memory (U2) is connected to one end of ferrite bead FB2, one end of capacitor C26, and one end of capacitor C27. The other end of ferrite bead FB2 is connected to the negative terminal of diode D1 and one end of capacitor C28. The positive terminal of diode D1 is connected to the drain of transistor Q1. The ground terminal of memory (U2), the other end of capacitor C26, the other end of capacitor C27, and the other end of capacitor C28 are all connected to the power supply ground.

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