Overvoltage detection circuit, battery management system and energy storage device

Abstract

The utility model provides an overvoltage detection circuit, a battery management system and an energy storage device. The circuit comprises an overvoltage comparison sub-circuit, an overvoltage action sub-circuit and a drive control sub-circuit. The overvoltage comparison sub-circuit is connected with the high-voltage dividing line and the overvoltage action sub-circuit, and the driving control sub-circuit is connected with the overvoltage action sub-circuit and a control switch in a high-voltage loop where the power battery is located; the overvoltage comparison sub-circuit is used for receiving a sampling voltage on a high-voltage dividing line, and outputting a first level signal to the overvoltage action sub-circuit when the sampling voltage is higher than a reference voltage; the overvoltage action sub-circuit outputs a second level signal to the drive control sub-circuit after receiving the first level signal, and the drive control sub-circuit drives the control switch to be turned off after receiving the second level signal. The overvoltage detection link is realized through a hardware circuit, so that the detection process is more stable and reliable, the control switch is quickly turned off when overvoltage abnormity occurs, and the working safety of the high-voltage loop is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of battery management, in particular to an overvoltage detection circuit, a battery management system and an energy storage device. Background Technique

[0002] When the voltage of the power battery appears overvoltage abnormality, the control switch in the high-voltage circuit where the power battery is located needs to be quickly disconnected, so as to timely cut off the high-voltage circuit and avoid irreversible damage to the power supply line during overvoltage abnormality.

[0003] In the related art, in the overvoltage detection link, usually the sampled voltage on the high-voltage voltage division line is converted by an analog-to-digital converter and then transmitted to the controller for overvoltage judgment processing, and then sent to the driver for driving output control processing, and then the control switch is driven to turn off when overvoltage abnormality is detected. Since the overvoltage detection link is mainly implemented by software, the reliability of the software detection process is low, and the detection and drive control processes take a long time. After overvoltage abnormality occurs, the control switch cannot be turned off in time, resulting in the high-voltage circuit being in an overvoltage state for a long time and prone to safety accidents. Summary of the Utility Model

[0004] The utility model provides an overvoltage detection circuit, a battery management system and an energy storage device to solve the defects of untimely response and low reliability of the traditional overvoltage detection scheme.

[0005] On the one hand, the utility model provides an overvoltage detection circuit, which is connected to the high-voltage voltage division line of the power battery, and the circuit includes: an overvoltage comparison sub-circuit, an overvoltage action sub-circuit and a drive control sub-circuit;

[0006] The overvoltage comparison sub-circuit is respectively connected to the high-voltage voltage division line and the overvoltage action sub-circuit, and the drive control sub-circuit is respectively connected to the overvoltage action sub-circuit and the control switch in the high-voltage circuit where the power battery is located;

[0007] The overvoltage comparison sub-circuit is used to receive the sampled voltage on the high-voltage voltage division line, and when the sampled voltage is higher than the reference voltage, output a first level signal to the overvoltage action sub-circuit; the overvoltage action sub-circuit is used to output a second level signal to the drive control sub-circuit after receiving the first level signal; the drive control sub-circuit is used to drive the control switch to turn off after receiving the second level signal.

[0008] According to the overvoltage detection circuit provided by the utility model, the overvoltage comparison sub-circuit includes: an inverting comparator and a first opto-coupler switch;

[0009] The inverting input terminal of the inverting comparator is connected to the high-voltage voltage dividing circuit, the non-inverting input terminal of the inverting comparator is connected to the reference voltage terminal, the output terminal of the inverting comparator is connected to the first opto-coupler switch, and the first opto-coupler switch is connected to the overvoltage action sub-circuit.

[0010] According to the overvoltage detection circuit provided by the present invention, the overvoltage action sub-circuit includes: a trigger and an NMOS transistor;

[0011] The trigger is respectively connected to the overvoltage comparison sub-circuit, the NMOS transistor, and the drive control sub-circuit.

[0012] According to the overvoltage detection circuit provided by the present invention, the overvoltage action sub-circuit further includes: a first anti-reverse diode and a first current-limiting resistor;

[0013] The positive electrode of the first anti-reverse diode is connected to the trigger, the negative electrode of the first anti-reverse diode is connected to the first current-limiting resistor, and the first current-limiting resistor is connected to the overvoltage comparison sub-circuit.

[0014] According to the overvoltage detection circuit provided by the present invention, the overvoltage action sub-circuit further includes: a second anti-reverse diode and a third anti-reverse diode;

[0015] The positive electrode of the second anti-reverse diode is connected to the overvoltage state inverting output pin of the trigger, the positive electrode of the third anti-reverse diode is connected to the overcurrent state inverting output pin of the trigger, and the negative electrodes of the second anti-reverse diode and the third anti-reverse diode are both connected to the drive control sub-circuit.

[0016] According to the overvoltage detection circuit provided by the present invention, the circuit further includes: a controller;

[0017] The NMOS transistor is connected to the set control pin of the controller, and the overcurrent state output pin and the overvoltage state output pin of the trigger are both connected to the data input pin of the controller.

[0018] According to the overvoltage detection circuit provided by the present invention, the drive control sub-circuit includes: a buffer, a high-side driver, and a low-side driver;

[0019] The buffer is respectively connected to the overvoltage action sub-circuit, the high-side driver, and the low-side driver, and both the high-side driver and the low-side driver are connected to the control switch.

[0020] According to the overvoltage detection circuit provided by the present invention, the drive control sub-circuit further includes: a power supply filter capacitor;

[0021] The power supply filtering capacitor is arranged between the power supply pin and the ground pin of the buffer.

[0022] On the other hand, the present utility model also provides a battery management system, including any one of the above-mentioned overvoltage detection circuits.

[0023] On the other hand, the present utility model also provides an energy storage device, including any one of the above-mentioned overvoltage detection circuits or the above-mentioned battery management system.

[0024] The overvoltage detection circuit, battery management system and energy storage device provided by the present utility model, by setting an overvoltage comparison sub-circuit, an overvoltage action sub-circuit and a drive control sub-circuit, the overvoltage comparison sub-circuit is used to receive the sampled voltage on the high-voltage voltage-dividing line, and when the sampled voltage is higher than the reference voltage, output a first level signal to the overvoltage action sub-circuit. After receiving the first level signal, the overvoltage action sub-circuit outputs a second level signal to the drive control sub-circuit. After receiving the second level signal, the drive control sub-circuit drives and controls the switch to turn off. Since the overvoltage detection link is realized by a hardware circuit, the detection process is more stable and reliable, and can respond in time when an overvoltage abnormality occurs, quickly turn off the control switch, so that the high-voltage line can be cut off in time, improving the working safety of the high-voltage loop. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the present utility model or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative work.

[0026] Figure 1 is a schematic structural diagram of a traditional overvoltage detection system;

[0027] Figure 2 is a schematic structural diagram of the overvoltage detection circuit provided by the embodiment of the present utility model;

[0028] Figure 3 is a partial circuit structural diagram of the high-voltage voltage-dividing line;

[0029] Figure 4 is a schematic structural diagram of the overvoltage comparison sub-circuit;

[0030] Figure 5 is a schematic structural diagram of the overvoltage action sub-circuit;

[0031] Figure 6 is a circuit structural diagram related to the buffer;

[0032] Figure 7It is a schematic diagram of the circuit structure related to the high-side driver;

[0033] Figure 8 It is a schematic diagram of the circuit structure related to the low-side driver;

[0034] Figure 9 It is a schematic diagram of the pin connection status of the single-chip microcomputer. Specific implementation manners

[0035] To make the objectives, technical solutions, and advantages of the present utility model clearer, the technical solutions in the present utility model will be clearly and completely described below with reference to the accompanying drawings in the present utility model. Apparently, the described embodiments are some, but not all, of the embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present utility model without making creative efforts shall fall within the protection scope of the present utility model.

[0036] This embodiment relates to the field of battery management and can be specifically applied to the scenario of overvoltage detection of the power battery voltage. In actual applications, the commonly used overvoltage detection solutions currently can be referred to Figure 1 , such as Figure 1 shown. The positive electrode PACK+ of the power battery is connected to the high-voltage positive electrode interface PCBA_HV+ in the battery management system (Battery Management System, BMS) through a voltage sampling line, and then reaches the second optocoupler switch through a 6M ohm first voltage-dividing resistor. When the BMS is not working, VAUX_5V = 0, and at this time, the second optocoupler switch is in the off state, and the high-voltage current cannot pass through the second optocoupler switch. When the BMS is working properly, VAUX_5V = 5V, the second optocoupler switch conducts, and then passes through a 43K ohm second voltage-dividing resistor and returns to the negative electrode PACK- of the power battery through the high-voltage negative electrode interface PCBA_HV-.

[0037] In the overvoltage detection section, when the BMS is working properly, the sampling voltage HV_MSR between the 43K ohm second voltage-dividing resistor and the second opto-coupler switch outputs a digital signal through an Analog to Digital Converter (ADC). After being transmitted to the isolated DC-DC (i.e., DC-DC converter) and the digital communication chip, this digital signal is further sent to the controller in the low-voltage area. After being compared with the preset overvoltage threshold in the controller, it is determined whether an overvoltage anomaly occurs. If an overvoltage anomaly occurs, the controller sends low-level signals to the high-side drive terminal (HSD_DRV) and the low-side drive terminal (LSD_DRV) respectively. After receiving the low-level signals, both the high-side drive terminal and the low-side drive terminal turn off the drive output. In this way, no current passes through the control side of the contactor, the electromagnetic force disappears, the contactor disconnects, and at the same time, the high-voltage circuit is cut off. Currently, the control switch in the high-voltage circuit has used an IGBT (Insulate Gate Bipolar Transistor) to replace the mechanical contactor to improve the opening and closing control effect of the control switch.

[0038] However, during the process of implementing overvoltage detection using the Figure 1 shown overvoltage detection architecture, the sampling voltage needs to be converted by the analog-to-digital converter and then transmitted to the controller for overvoltage judgment processing, and then sent to the high-side drive terminal and the low-side drive terminal for drive output control processing. The detection and drive control processes are complex, resulting in a long time for turning off the control switch after an overvoltage anomaly occurs.

[0039] Since the turn-off time of the control switch is too long after an overvoltage anomaly occurs, it will cause the high-voltage circuit to be in an overvoltage state for a long time, and safety accidents are likely to occur.

[0040] To address the above technical problems, the embodiments of the present utility model provide specific solutions. The following combines Figures 2 to 9 to describe the detailed solutions of the overvoltage detection circuit, battery management system, and energy storage device provided by the embodiments of the present utility model.

[0041] Figure 2 is a schematic structural diagram of the overvoltage detection circuit provided by the embodiments of the present utility model.

[0042] As Figure 2 shown, the overvoltage detection circuit provided by the embodiments of the present utility model is specifically connected to the high-voltage voltage-dividing line 100 of the power battery. The high-voltage voltage-dividing line 100 is connected to the positive electrode PACK+ of the power battery through the high-voltage positive electrode interface PCBA_HV+ and is connected to the negative electrode PACK- of the power battery through the high-voltage negative electrode interface PCBA_HV-.

[0043] The overvoltage detection circuit specifically includes: an overvoltage comparison sub-circuit 110, an overvoltage action sub-circuit 120, and a drive control sub-circuit 130.

[0044] The overvoltage comparison sub-circuit 110 is respectively connected to the high-voltage voltage division line 100 and the overvoltage action sub-circuit 120, and the drive control sub-circuit 130 is respectively connected to the overvoltage action sub-circuit 120 and the control switch 140 in the high-voltage circuit where the power battery is located.

[0045] The overvoltage comparison sub-circuit 110 is used to receive the sampled voltage HV_MSR on the high-voltage voltage division line 100, and when the sampled voltage HV_MSR is higher than the reference voltage VREF, it outputs a first-level signal to the overvoltage action sub-circuit 120; the overvoltage action sub-circuit 120 is used to output a second-level signal to the drive control sub-circuit 130 after receiving the first-level signal, and the drive control sub-circuit 130 is used to drive the control switch 140 to turn off after receiving the second-level signal.

[0046] In this embodiment, the high-voltage voltage division line 100 is Figure 1 consistent with the high-voltage voltage division part structure in the shown traditional overvoltage detection architecture, and both include a first voltage division resistor, a second opto-coupler switch, and a second voltage division resistor. The sampled voltage HV_MSR is specifically the voltage between the second opto-coupler switch and the second voltage division resistor.

[0047] Figure 3 Exemplarily shows a partial circuit structure of the high-voltage voltage division line, such as Figure 3 shown. The VAUX_5V signal passes through the second current-limiting resistor R1 to reach the 1 pin of the second opto-coupler switch Q1, passes through the LED inside the second opto-coupler switch Q1 and then reaches the 2 pin, and then is connected to the GND terminal (i.e., the low-voltage power supply circuit). The high-voltage input signal input from the high-voltage positive interface PCBA_HV+ (i.e., Figure 3 the HV+ terminal in) passes through the 6M ohm first voltage division resistor and the third current-limiting resistor R3, the fourth current-limiting resistor R4, the fifth current-limiting resistor R6, and the sixth current-limiting resistor R6 and then reaches the 4 pin of the second opto-coupler switch Q1.

[0048] When VAUX_5V = 0, the state between the 3 pin and the 4 pin is off, and the high-voltage input signal is blocked on one side of the 4 pin. When there is VAUX_5V = 5V, the MOSFET inside the second opto-coupler switch Q1 conducts, the connection between the 3 pin and the 4 pin is established, and at the same time the high-voltage input signal reaches the 3 pin, and then the high-voltage input signal will be transmitted in two paths. One path passes through the second voltage division resistor R2 and the first filter capacitor C1 and then reaches the high-voltage negative interface PCBA_HV- (i.e., Figure 3The HV- terminal in it), and then returns to the negative electrode of the power battery through the external wiring harness. Another route connects the OV_MSR terminal to the overvoltage comparison sub-circuit, thereby transmitting the sampled voltage to the overvoltage comparison sub-circuit.

[0049] In one embodiment, the overvoltage comparison sub-circuit specifically includes: an inverting comparator and a first opto-coupler switch.

[0050] The inverting input terminal of the inverting comparator is connected to the high-voltage voltage-dividing line, the non-inverting input terminal of the inverting comparator is connected to the reference voltage terminal, the output terminal of the inverting comparator is connected to the first opto-coupler switch, and the first opto-coupler switch is connected to the overvoltage action sub-circuit.

[0051] Figure 4 The specific circuit structure of the overvoltage comparison sub-circuit is exemplarily shown, such as Figure 4 As shown, the 3-pin of the inverting comparator U3 is used to input the reference voltage VREF. The IS0_5V signal provides a 2V reference voltage to the 3-pin after passing through the third voltage-dividing resistor R24 and the fourth voltage-dividing resistor R25. The 4-pin of the inverting comparator U3 is used to input the sampled voltage, which is input from the OV_MSR terminal connected to the 3-pin of the second opto-coupler switch Q1 in Figure 3 It is obtained by dividing the high-voltage input signal by the first voltage-dividing resistor and the second voltage-dividing resistor, and this sampled voltage changes with the voltage value of the high-voltage input signal. According to the voltage division calculation, when the voltage value of the high-voltage input signal is 300V, the sampled voltage input to the inverting comparator U3 is 2.13V, which is greater than the 2V reference voltage VREF.

[0052] The 5-pin of the inverting comparator U3 is the positive power supply access pin, which provides a 5V operating voltage by ISO_5V. At the same time, the 5-pin of the inverting comparator U3 is connected to the positive power supply through the second filter capacitor C2 and the third filter capacitor C3. The 2-pin of the inverting comparator U3 is the negative power supply input pin, which is connected to the HV- terminal of the high-voltage area and uses this voltage as the reference voltage; the 1-pin of the inverting comparator U3 is the output terminal.

[0053] In practical applications, when the sampled voltage input to the inverting comparator U3 is greater than the reference voltage, the inverting comparator U3 outputs a first level signal in a low level state; when the sampled voltage is less than the reference voltage, the inverting comparator U3 outputs a first level signal in a high level state. The pin 1 of the inverting comparator U3 is connected to the pin 2 of the first opto-coupler switch Q2, and the ISO_5V signal reaches the pin 1 of the first opto-coupler switch Q2 through the seventh current-limiting resistor R14. When the pin 1 of the inverting comparator U3 outputs a first level signal in a low level state, the LED inside the first opto-coupler switch Q2 emits light, triggering the internal MOSFET to conduct, and then the first opto-coupler switch Q2 is in a conducting state. When the pin 1 of the inverting comparator U3 outputs a first level signal in a high level state, the input voltage of the first opto-coupler switch Q2 is close to the voltage value of ISO_5V, and no current flows through the inside of the first opto-coupler switch Q2. Therefore, the LED inside the first opto-coupler switch Q2 does not light up, the MOSFET inside the first opto-coupler switch Q2 is turned off, and then the first opto-coupler switch Q2 is in an off state.

[0054] In addition, the pin 4 of the first opto-coupler switch Q2 is connected to the overvoltage action sub-circuit through the OV_IN network port, and the pin 3 of the first opto-coupler switch Q2 is connected to the GND terminal. In practical applications, the inverting comparator U3 can use a device of model TLV9031-Q1, and the first opto-coupler switch Q2 can specifically use a device of model TLX9175J. In this embodiment, the electrical parameters of the inverting comparator can be specifically referred to Table 1 below.

[0055] Table 1 Electrical Parameters of the Inverting Comparator

[0056]

[0057] In one embodiment, as Figure 5 shown, the overvoltage action sub-circuit specifically includes: a trigger U1 and an NMOS transistor Q3.

[0058] The trigger U1 is respectively connected to the overvoltage comparison sub-circuit, the NMOS transistor Q3, and the drive control sub-circuit.

[0059] In one embodiment, as Figure 5 shown, the overvoltage action sub-circuit may further include: a first anti-reverse diode D1 and a first current-limiting resistor R7.

[0060] The positive electrode of the first anti-reverse diode D1 is connected to the trigger U1, the negative electrode of the first anti-reverse diode D1 is connected to the first current-limiting resistor R7, and the first current-limiting resistor R7 is connected to the overvoltage comparison sub-circuit.

[0061] In one embodiment, as Figure 5 shown, the overvoltage action sub-circuit further includes: a second anti-reverse diode D2 and a third anti-reverse diode D4;

[0062] The positive electrode of the second reverse protection diode D2 is connected to the overvoltage state inverting output pin (i.e., pin 6) of the trigger U1, and the positive electrode of the third reverse protection diode D4 is connected to the overcurrent state inverting output pin (i.e., pin 8) of the trigger U1. The negative electrodes of the second reverse protection diode D2 and the third reverse protection diode D4 are both connected to the drive control sub-circuit.

[0063] In one embodiment, as Figure 2 and Figure 5 shown, the above overvoltage detection circuit may further include: a controller 150.

[0064] The NMOS transistor Q3 is connected to the set control pin of the controller 150, and the overcurrent state output pin (i.e., pin 9) and the overvoltage state output pin (i.e., pin 5) of the trigger U1 are both connected to the data input pin of the controller 150.

[0065] As Figure 5 shown, the trigger U1 is a 2-group positive-edge-triggered D-type trigger. The 1 pin of the trigger U1 is connected to the VAUX_5V terminal through the first pull-up resistor R8. The first reverse protection diode D1 is used to prevent the power supply voltage from the OV_IN network port from affecting the 1 pin of the trigger U1. The first current-limiting resistor R7 is used to protect the first reverse protection diode D1 when the OV_IN network port is at a low level. The 1 pin of the trigger U1 is connected to the Figure 4 4 pin of the first opto-coupler switch in. When the MOSFET inside the first opto-coupler switch Q2 is turned off, it is in an open state between the 4 pin and the 3 pin. Since the 1 pin of the trigger U1 is pulled up to VAUX_5V, the 1 pin of the trigger U1 is at a high level at this time. When the MOSFET inside the first opto-coupler switch Q2 is turned on, the OV_IN network port is connected to the GND terminal, and the 1 pin of the trigger U1 is at a low level at this time.

[0066] When an overvoltage abnormality occurs, the first opto-coupler switch Q2 is turned on, the OV_IN network port is pulled down to a low level, and the 1 pin of the trigger U1 also changes from a high level (5V) to a low level (about 0.49V). In this embodiment, the 2 pin, 3 pin, 11 pin, and 12 pin of the trigger U1 are not used and are connected to the GND terminal through the 0-ohm resistors R18, R19, R20, and R21. The 4 pin and 10 pin of the trigger U1 are interconnected by a trace, one end is connected to the second pull-up resistor R10 and pulled up to VAUX_5V; the other end is connected to the Figure 4 3 pin of the NMOS transistor Q3 in. At the same time, the 13 pin of the trigger U1 is connected to the OC_IN network port through the eighth current-limiting resistor R17 and the fourth reverse protection diode D3, and the 13 pin of the trigger U1 is pulled up to VAUX_5V through the third pull-up resistor R9.

[0067] The fourth filter capacitor C4 and the fifth filter capacitor C5 are the filter capacitors for the 4th pin and the 10th pin of the flip-flop U1 respectively, and can filter out spike voltage and high-frequency voltage. When arranging the circuit board layout, the fourth filter capacitor C4 and the fifth filter capacitor C5 are arranged close to the 4th pin and the 10th pin of the flip-flop U1 respectively. The 2nd pin of the NMOS transistor Q3 is directly connected to the GND terminal. The 3rd pin of the NMOS transistor Q3 is connected to the set control pin of the controller through the ninth current-limiting resistor R15 using the MCU_RST network port. At the same time, a 10K ohm intermediate resistor R16 is also connected between the 2nd pin and the 3rd pin of the NMOS transistor Q3 to reduce the gate input impedance of the NMOS transistor Q3 and prevent the NMOS transistor Q3 from being mis-triggered by pulses similar to static electricity.

[0068] In practical applications, when the controller outputs a high-level signal through the MCU_RST network port, the NMOS transistor Q3 is turned on, and the 4th pin and the 10th pin of the flip-flop U1 are connected to the GND terminal through the NMOS transistor Q3 and become low-level states. Otherwise, the 4th pin and the 10th pin of the flip-flop U1 both remain in the high-level state.

[0069] In addition, the 14th pin of the flip-flop U1 is the power supply input pin, connected to the VAUX_5V terminal. The sixth filter capacitor C6 is the filter capacitor for the 14th pin of the flip-flop U1, mainly used to filter out spike voltage and high-frequency voltage. When arranging the circuit board layout, the sixth filter capacitor C6 is close to the 14th pin of the flip-flop U1. The 7th pin of the flip-flop U1 is the low-voltage power supply loop output pin, connected to the GND terminal. The 5th pin of the flip-flop U1 is the overvoltage state output pin, directly connected to the controller through the MCU_OV_OUT network port. When an overvoltage abnormality occurs, the 1st pin of the flip-flop U1 changes from high level to low level, and the 4th pin and the 10th pin of the flip-flop U1 remain in the high-level state unchanged, then the output of the 5th pin of the flip-flop U1 changes from the high-level state to the low-level state.

[0070] The 6th pin of the flip-flop U1 is the inverted output of the 5th pin, that is, the overvoltage state inverted output pin. When the output of the 5th pin of the flip-flop U1 is low level, the output of the 6th pin of the flip-flop U1 is high level. One path of the output of the 6th pin of the flip-flop U1 is pulled up to VAUX_5V through the fourth pull-up resistor R11, and the other path is connected to the network port to achieve output enable.

[0071] The 9th pin of the flip-flop U1 is the overcurrent status output pin. A low level indicates overcurrent, and a high level indicates normal. The 8th pin of the flip-flop U1 is the inverted output of the 9th pin, that is, the overcurrent status inverted output pin. When the output of the 9th pin of the flip-flop U1 is at a low level, the output of the 8th pin of the flip-flop U1 is at a high level. One path of the output of the 8th pin of the flip-flop U1 is pulled up to VAUX_5V through the fifth pull-up resistor R12, and the other path is connected through the third reverse protection diode D4 to the network port to enable the output. The cathodes of the second reverse protection diode D2 and the third reverse protection diode D4 are connected in parallel to the same network port, which means that the two inverted outputs must be at a low level at the same time, and the second level signal output by the network port is a low level signal; as long as one of the inverted outputs is at a high level, then the second level signal output by the network port must be a high level signal.

[0072] In practical applications, the flip-flop U1 can use a device with the model number SN74AHCT74. Taking 2 groups of positive-edge-triggered D-type flip-flops as an example, the input and output functions of a single flip-flop can be seen in Table 2 below.

[0073] Table 2 Function Table of a Single Flip-Flop

[0074]

[0075] In one embodiment, the drive control sub-circuit specifically includes: a buffer, a high-side driver, and a low-side driver;

[0076] The buffer is respectively connected to the overvoltage action sub-circuit, the high-side driver, and the low-side driver. Both the high-side driver and the low-side driver are connected to the control switch.

[0077] In one embodiment, the drive control sub-circuit may further include: a power supply filter capacitor;

[0078] The power supply filter capacitor is arranged between the power supply pin and the ground pin of the buffer.

[0079] Figure 6 The circuit structure related to the buffer is shown. As Figure 6 shown, U2 is a buffer with 6 inputs and 6 inverted outputs. The 16th pin of the buffer U2 is the power supply pin, connected to VAUX_5V. The 8th pin of the buffer U2 is the ground pin, connected to the GND terminal. One end of the power supply filter capacitor C7 is connected to the 16th pin of the buffer U2, and the other end of the power supply filter capacitor C7 and the 8th pin of the buffer U2 are both connected to the ground terminal. The power supply filter capacitor C7 is used to filter out spike voltages and high-frequency voltages. When laying out the circuit board, the power supply filter capacitor C7 is arranged close to the 16th pin of the buffer U2.

[0080] The 1st and 15th pins of buffer U2 are output enable control pins, and the output is valid when the level is low. The 1st and 15th pins of buffer U2 are commonly connected to Figure 5 the network port of flip-flop U1. The 6th, 7th, and 9th to 14th pins of buffer U2 are not used and remain floating. The 2nd pin of buffer U2 is connected to the controller through the MCU_HS_DRV network port and is the first group of input pins of buffer U2. The 3rd pin of buffer U2 is connected to the HS_DRV_CTRL network port and is the inverted output pin corresponding to the first group of input pins of buffer U2. The 4th pin of buffer U2 is connected to the controller through the MCU_LS_DRV network port and is the second group of input pins of buffer U2. The 5th pin of buffer U2 is connected to the LS_DRV_CTRL network port and is the inverted output pin corresponding to the second group of input pins of buffer U2. In practical applications, buffer U2 can use a device with the model number 74HC366. The input and output functions of buffer U2 can be seen in Table 3 below.

[0081] Table 3 Function Table of Buffer

[0082]

[0083]

[0084] In Table 3 above, H represents high level state, L represents low level state, X represents invalid state, and Z represents high impedance off state.

[0085] According to the functions shown in Table 3 above, when there is no fault, both the OE1 and OE2 pins are in the low level state. At this time, if the input signal from the controller is a low level signal, the output is a high level signal; otherwise, the output is a low level signal. When an overvoltage fault occurs, both the OE1 and OE2 pins are in the high level state. At this time, the level state of the input signal from the controller does not need to be considered, the output is prohibited, and the measured value is the low level state.

[0086] Figure 7 Exemplarily shows the circuit structure related to the high-side driver, such as Figure 7 shown, the 15th pin of high-side driver U4 is the low-side power supply input pin, and this pin is directly connected to VAUX_5V. The 9th pin of high-side driver U4 is the low-voltage power supply loop output pin and is connected to the GND terminal. The 11th pin of high-side driver U4 is not used in this embodiment and is also connected to the GND terminal. The 10th pin of high-side driver U4 is the control input pin of the drive output and is connected to Figure 6Pin 3 of buffer U2. In practical applications, the high-side driver U4 can use a device with the model number UCC21750-Q1. The input and output functions of the high-side driver U4 can be seen in Table 4 below.

[0087] Table 4 Function Table of High-Side Driver

[0088]

[0089]

[0090] Among them, PU represents Power Up, that is, the power-on state. At this time, the following conditions are met:

[0091] VCC≥2.85V, VDD≥13.1V, VEE≤0V;

[0092] PD represents Power Down, that is, the power-down state. At this time, the following conditions are met:

[0093] VCC≤2.35V, VDD≤9.9V;

[0094] H represents the high-level state, L represents the low-level state, O represents the off state, X represents the invalid state, P represents the PWM pulse signal, and HiZ represents the high-impedance state.

[0095] In addition, RDY, FLY, and CLMPI are all open-drain outputs. RDY and FLT are configured with pull-ups. When working normally, Z = H; CLMPI is configured with a pull-down. When outputting normally, Z = H. When VDD_O, Z = L.

[0096] According to Table 4 above, when there is no fault and RST = H, Pin 10 of the high-side driver U4 is in the low-level state and outputs a low-level signal. Pin 16 of the high-side driver U4 is the output pin for the IGBT temperature detection value, and the temperature detection value can be sent to the controller through the MCU_IGBT_TEMP_MSR network port. Pin 13 of the high-side driver U4 is the detection pin for the IGBT short-circuit fault state, and the short-circuit fault state detection signal can be sent to the controller through the network port. Pin 13 of the high-side driver U4 is pulled up to VAUX_5V through the sixth pull-up resistor R26. C8 is the filter capacitor for Pin 13 of the high-side driver U4, which can filter out spike voltages and high-frequency voltages. Pin 12 of the high-side driver U4 is the detection pin for the power supply fault state of this chip, and the power supply fault state detection signal can be sent to the controller through the MCU_HS_DRV_RDY network port. Pin 12 of the high-side driver U4 can be pulled up to VAUX_5V through the seventh pull-up resistor R27. C9 is the filter capacitor for Pin 12 of the high-side driver U4, which can filter out spike voltages and high-frequency voltages.

[0097] Pin 14 of the high-side driver U4 is the input pin for the chip reset or enable function. Reset is active low, and enable is active high. Through the network port, the output signal of the single-chip microcomputer can be transmitted to this pin. At the same time, pin 14 of the high-side driver U4 is pulled up to VAUX_5V through the eighth pull-up resistor R28. C10 is the filter capacitor for pin 14 of the high-side driver U4, which can filter out spike voltage and high-frequency voltage.

[0098] Pin 5 of the high-side driver U4 is the input pin for the high-side power supply of the high-side driver, directly connected to HV_HS_VDD. Pin 3 of the high-side driver U4 is the output pin of the high-side high-voltage power supply loop, connected to HV_HS_GND. Pin 1 of the high-side driver U4 is the input pin for IGBT temperature detection, which can be connected to the temperature acquisition circuit through the NTC_TEMP_MSR network port. Pin 2 of the high-side driver U4 is the input pin for high-side IGBT short-circuit fault detection, which can be connected to the short-circuit detection circuit through the HV_HS_DRV_DESAT network port. Pin 4 of the high-side driver U4 is the pull-up pin for the high-side drive output, connected to the HV_HS_GATE network port through the first conduction resistor R29. The first conduction resistor R29 is used to control the peak source current.

[0099] Pin 6 of the high-side driver U4 is the pull-down pin for the high-side drive output, which can be connected to the HV_HS_GATE network port through the first turn-off resistor R30. The first turn-off resistor R30 is used to control the peak sink current. Pin 7 of the high-side driver U4 is the internal Miller clamp pin, which is connected to the control switch through the HV_HS_GATE network port, such as it can be connected to the gate of the IGBT. The HV_HS_GATE network port is connected to the HV_HS_GND network port through the first pull-down resistor R13, that is, the high-side high-voltage power supply loop, to ensure that the output of pin 7 of the high-side driver U4 is low when VDD is disconnected. Pin 8 of the high-side driver U4 is the negative supply rail pin for the gate drive voltage, which can be connected to the HV_HS_VEE network port.

[0100] Figure 8 Exemplarily, the relevant circuit structure of the low-side driver is shown, such as Figure 8 As shown, pin 15 of the low-side driver U5 is the input pin for the low-side power supply of the low-side driver, and this pin is directly connected to VAUX_5V. Pin 9 of the low-side driver U5 is the output pin of the low-voltage power supply loop, connected to the GND terminal. Pin 11 of the low-side driver U5 is not used in this embodiment and is also connected to the GND terminal. Pin 10 of the low-side driver U5 is the control input pin for the drive output, connected to Figure 6Pin 5 of the middle buffer U2. Since the input and output functions of the low-side driver U5 are the same as those of the high-side driver U4, referring to Table 4 above, when there is no fault and RST = H, pin 10 of the low-side driver U5 is at a low level state, and the output signal is a low-level signal.

[0101] Pin 16 of the low-side driver U5 is not used and is connected to the GND terminal. Pin 13 of the low-side driver U5 is the IGBT short-circuit fault status detection pin, and the short-circuit fault status detection signal can be sent to the controller through the network port. At the same time, this pin is pulled up to VAUX_5V through the ninth pull-up resistor R31. C11 is the filter capacitor for pin 13 of the low-side driver U5, which can filter out spike voltages and high-frequency voltages. Pin 12 of the low-side driver U5 is the power supply fault status detection pin of this chip, and the power supply fault status detection signal can be sent to the single-chip microcomputer through the MCU_LS_DRV_RDY network port. This pin is pulled up to VAUX_5V through the tenth pull-up resistor R32. C12 is the filter capacitor for pin 12 of the low-side driver U5, which can filter out spike voltages and high-frequency voltages.

[0102] Pin 14 of the low-side driver U5 is the input pin for the reset or enable function of this chip. Reset is active low, and enable is active high. The output signal of the controller can be received through the network port. This pin is also pulled up to VAUX_5V through the eleventh pull-up resistor R33. C13 is the filter capacitor for pin 14 of the low-side driver U5, which can filter out spike voltages and high-frequency voltages. Pin 5 of the low-side driver U5 is the input pin for the high-voltage side power supply of the low-side driver, which is directly connected to HV_LS_VDD. Pin 3 of the low-side driver U5 is the output pin of the low-side high-voltage power supply loop, which is connected to HV_LS_GND. Pin 1 of the low-side driver U5 is not used and is connected to HV_LS_GND.

[0103] Pin 2 of the low-side driver U5 is the low-side IGBT short-circuit fault detection input pin, which can be connected to the short-circuit detection circuit through the HV_LS_DRV_DESAT network port. Pin 4 of the low-side driver U5 is the low-side drive output pull-up pin, which can be connected to the HV_LS_GATE network port through the second conduction resistor R34. Pin 6 of the low-side driver U5 is the low-side drive output pull-down pin, which can be connected to the HV_LS_GATE network port through the second turn-off resistor R35. Pin 7 of the low-side driver U5 is the internal Miller clamp pin, which is connected to the gate of the IGBT through the HV_LS_GATE network port. The HV_LS_GATE network port is also connected to the HV_LS_GND network port through the second pull-down resistor R22 to ensure that the output of pin 7 of the low-side driver U5 is low when VDD is disconnected. Pin 8 of the low-side driver U5 is the negative power supply rail pin of the gate drive voltage, which is connected to the HV_LS_VEE network port.

[0104] In this embodiment, the controller can use a single-chip microcomputer. Figure 9 Exemplarily, the circuit structure related to the controller is shown, such as Figure 9 As shown, it is the connection status of some pins of the single-chip microcomputer U6 to illustrate the signal reception and control principle of the single-chip microcomputer.

[0105] For the input part, as Figure 9 shown, pin 1 of the single-chip microcomputer U6 receives the overvoltage status detection signal from the Figure 5 flip-flop U1 in through the MCU_OV_OUT network port. A low level indicates an overvoltage abnormality, and a high level indicates normal high-voltage input. Pin 2 of the single-chip microcomputer U6 receives the overcurrent status detection signal from the Figure 5 flip-flop U1 in through the MCU_OC_OUT network port. A low level indicates an overcurrent abnormality, and a high level indicates normal high-voltage passing current. Pin 3 of the single-chip microcomputer U6 receives the power supply status detection signal from the Figure 7 high-side driver U4 in through the MCU_HS_DRV_RDY network port. A low level indicates a power supply failure, and a high level indicates normal power supply.

[0106] Pin 4 of the single-chip microcomputer U6 receives the power supply status detection signal from the Figure 8 low-side driver U5 in through the MCU_LS_DRV_RDY network port. A low level indicates a power supply failure, and a high level indicates normal power supply. Pin 5 of the single-chip microcomputer U6 receives through the MCU_HS_DRV_FLT network from Figure 7The desaturation protection status detection signal of the medium-high side driver U4. A low level indicates an IGBT short circuit fault, and a high level indicates that the IGBT circuit is normal. Pin 6 of the microcontroller U6 receives from the Figure 8 The desaturation protection status detection signal of the medium-low side driver U5. A low level indicates an IGBT short circuit fault, and a high level indicates that the IGBT circuit is normal. Pin 7 of the microcontroller U6 receives from the Figure 7 The IGBT temperature detection value of the medium-high side driver U4.

[0107] For the output part, such as Figure 9 As shown, pin 16 of the microcontroller U6 outputs a set control signal to the Figure 5 Set pins (i.e., pins 4 and 10) of the medium flip-flop U1 to control the gate of the NMOS transistor Q3. When the gate receives a high-level signal, the NMOS transistor Q3 conducts, and the set pins of the flip-flop U1 are in a low-level state; when the gate receives a low-level signal, the NMOS transistor Q3 turns off, and the set pins of the flip-flop U1 are in a high-level state. Pin 15 of the microcontroller U6 outputs a signal to pin 2 of the buffer U2 through the MCU_HS_DRV network port. If a high-level signal is received and OUT_EN = L, the high-side drive control signal output by pin 3 of the buffer U2 is in a low-level state; if a low-level signal is received and OUT_EN = L, the high-side drive control signal output by pin 3 of the buffer U2 is in a high-level state. If U2_OUT_EN = H, the output is prohibited, and due to the external configuration pull-down, the output is in a low-level state.

[0108] Pin 14 of the microcontroller U6 outputs a signal to pin 4 of the buffer U2 through the MCU_LS_DRV network port. If a high level is received and OUT_EN = L, the low-side drive control signal output by pin 5 of the buffer U2 is in a low-level state; if a low level is received and OUT_EN = L, the low-side drive control signal output by pin 5 of the buffer U2 is in a high-level state. If U2_OUT_EN = H, the output is prohibited, and due to the external configuration pull-down, the output is in a low-level state.

[0109] Pin 13 of the microcontroller U6 outputs a signal to pin 14 of the high-side driver U4 through the network port. If a high-level signal is received, the high-side driver U4 is enabled; if a low-level signal is received, the high-side driver U4 is reset. Pin 12 of the microcontroller U6 outputs a signal to the The network port outputs a signal to pin 14 of the low-side driver U5. If a high-level signal is received, the low-side driver U5 is enabled; if a low-level signal is received, the low-side driver U5 is reset.

[0110] In summary, in this embodiment, the sampled voltage OV_MSR is compared with the reference voltage of the inverting comparator U3. When the sampled voltage is higher than the reference voltage, a first level signal in the low-level state is output, indicating that an overvoltage fault has occurred; otherwise, a first level signal in the high-level state is output. When the inverting comparator U3 outputs a first level signal in the low-level state, the first optocoupler switch Q2 conducts, and at this time, OV_IN = L is satisfied, that is, pin 1 of the flip-flop U1 is in the low-level state, so pin 5 of the flip-flop U1 outputs a low-level signal, and its inverted output pin outputs a high-level signal. Since the inverted output pin of the flip-flop U1 is connected to the OE pin of the buffer U2, this pin outputs an enable signal, and it is active low. The inverted output pin of the flip-flop U1 outputs a second level signal in the high-level state, indicating that the buffer U2 is prohibited from outputting. Due to its external configuration being pulled down, when the output is prohibited, its output interface is actually in the low-level state. The output pin of the buffer U2 is connected to the high-side drive control pin of the high-side driver U4 and the low-side drive control pin of the low-side driver U5. When they are low-level signals, the outputs of both the high-side driver U4 and the low-side driver U5 are low-level signals, and at this time, the control switch IGBT is turned off.

[0111] It can be seen that when an overvoltage occurs, the high-side and low-side drive control signals output by the single-chip microcomputer U6 do not affect the control of the overvoltage comparison sub-circuit, the overvoltage action sub-circuit, and the drive control sub-circuit to turn off the control switch IGBT. At this time, only the overvoltage comparison sub-circuit, the overvoltage action sub-circuit, and the drive control sub-circuit can turn off the control switch IGBT.

[0112] In a specific example, the measured data of the inverting comparator U3 can be seen in Table 5 below.

[0113] Table 5 Measured Data of the Inverting Comparator

[0114]

[0115] According to the data shown in Table 5 above, it can be known that the high-voltage overvoltage determination process can be realized by an inverting comparator, rather than using the software judgment process of the controller.

[0116] Furthermore, the measured data of the flip-flop U1 can be seen in Table 6 below.

[0117] Table 6 Measured Data of the Flip-Flop

[0118]

[0119] The measured data of the buffer can be seen in Table 7 below.

[0120] Table 7 Measured Data of the Buffer

[0121]

[0122] The measured data of the high-side driver and the low-side driver can be seen in Table 8 below.

[0123] Table 8 Measured Data of the High-side Driver and the Low-side Driver

[0124]

[0125] According to Tables 6 to 8 above, it can be seen that the disconnection of the control switch IGBT can be achieved by giving instructions to the high-side driver and the low-side driver through an inverter trigger and a buffer, rather than relying on the software control of the controller.

[0126] When there is no overvoltage abnormality, the inverting comparator U3 outputs a first level signal in the high level state. The first optocoupler switch Q2 is disconnected, and OV_IN remains in the high level state, that is, the 1 pin of the flip-flop U1 is in the high level state. Then the 5 pin of the flip-flop U1 outputs a high level signal, and its inverting output pin outputs a second level signal in the low level state. The inverting output pin of the flip-flop U1 is connected to the OE pin of the buffer U2. This pin outputs an enable signal, and it is valid in the low level. At this time, the inverting output pin of the flip-flop U1 outputs a second level signal in the low level state, indicating that the buffer U2 enables output. At this time, both the 2 pin and the 4 pin of the buffer U2 input high level signals, then the buffer U2 outputs a low level signal. The 2 pin and the 4 pin of the buffer U2 are connected to the high-side drive control pin of the high-side driver U4 and the low-side drive control pin of the low-side driver U5. When they are low level signals, both the high-side driver U4 and the low-side driver U5 output low level signals. At this time, the control switch IGBT is disconnected. On the contrary, when the high-side driver U4 and the low-side driver U5 output high level signals, the control switch IGBT is turned on. It can be seen that when there is no fault, the turn-off and turn-on of the control switch IGBT are mainly controlled by the output signal of the controller.

[0127] In summary, due to the overvoltage detection circuit provided in this embodiment, when an overvoltage abnormality occurs, the overvoltage detection and the turn-off control process of the control switch can be achieved without the participation of the controller, and the high-voltage circuit can be cut off in time when an overvoltage abnormality is detected, thereby improving the reliability and safety of the overvoltage detection link.

[0128] In addition, the embodiment of the present invention also provides a battery management system, including the overvoltage detection circuit provided in each of the above embodiments.

[0129] In addition, an embodiment of the present utility model further provides an energy storage device, which includes the overvoltage detection circuit provided in each of the above embodiments or the above battery management system.

[0130] It can be understood that the energy storage device can be a vehicle, a working machine, etc.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present utility model, rather than to limit them; although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present utility model.

Claims

1. An overvoltage detection circuit, characterized in that, The circuit is connected to the high-voltage voltage-dividing line of the power battery, and the circuit includes: an overvoltage comparison sub-circuit, an overvoltage action sub-circuit, and a drive control sub-circuit; The overvoltage comparison sub-circuit is respectively connected to the high-voltage voltage-dividing line and the overvoltage action sub-circuit, and the drive control sub-circuit is respectively connected to the overvoltage action sub-circuit and a control switch in the high-voltage circuit where the power battery is located; The overvoltage comparison sub-circuit is configured to receive the sampled voltage on the high-voltage voltage-dividing line, and when the sampled voltage is higher than the reference voltage, output a first level signal to the overvoltage action sub-circuit; the overvoltage action sub-circuit is configured to output a second level signal to the drive control sub-circuit after receiving the first level signal; the drive control sub-circuit is configured to drive the control switch to turn off after receiving the second level signal.

2. The overvoltage detection circuit according to claim 1, characterized in that, The overvoltage comparison sub-circuit includes: an inverting comparator and a first opto-coupler switch; The inverting input terminal of the inverting comparator is connected to the high-voltage voltage-dividing line, the non-inverting input terminal of the inverting comparator is connected to the reference voltage terminal, the output terminal of the inverting comparator is connected to the first opto-coupler switch, and the first opto-coupler switch is connected to the overvoltage action sub-circuit.

3. The overvoltage detection circuit according to claim 1, wherein The overvoltage action sub-circuit includes: a trigger and an NMOS transistor; The trigger is respectively connected to the overvoltage comparison sub-circuit, the NMOS transistor, and the drive control sub-circuit.

4. The overvoltage detection circuit according to claim 3, characterized in that, The overvoltage action sub-circuit further includes: a first anti-reverse diode and a first current-limiting resistor; The positive electrode of the first anti-reverse diode is connected to the trigger, the negative electrode of the first anti-reverse diode is connected to the first current-limiting resistor, and the first current-limiting resistor is connected to the overvoltage comparison sub-circuit.

5. The overvoltage detection circuit according to claim 3, characterized in that, The overvoltage action sub-circuit further includes: a second anti-reverse diode and a third anti-reverse diode; The positive electrode of the second anti-reverse diode is connected to the overvoltage state inverting output pin of the trigger, the positive electrode of the third anti-reverse diode is connected to the overcurrent state inverting output pin of the trigger, and the negative electrodes of the second anti-reverse diode and the third anti-reverse diode are both connected to the drive control sub-circuit.

6. The overvoltage detection circuit according to any one of claims 3 to 5, characterized in that, The circuit further includes: a controller; The NMOS transistor is connected to the set control pin of the controller, and the overcurrent state output pin and the overvoltage state output pin of the trigger are both connected to the data input pin of the controller.

7. The overvoltage detection circuit according to claim 1, characterized in that, The drive control sub-circuit includes: a buffer, a high-side driver, and a low-side driver; The buffer is respectively connected to the overvoltage action sub-circuit, the high-side driver, and the low-side driver, and the high-side driver and the low-side driver are both connected to the control switch.

8. The overvoltage detection circuit according to claim 7, characterized in that, The drive control sub-circuit further includes: a power supply filter capacitor; The power supply filter capacitor is arranged between the power supply pin and the ground pin of the buffer.

9. A battery management system, characterized in that, Including the overvoltage detection circuit according to any one of claims 1 to 8.

10. A energy storage device, characterized in that, Including the overvoltage detection circuit according to any one of claims 1 to 8 or the battery management system according to claim 9.

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