Communication circuit and scooter

Abstract

The utility model relates to a communication circuit and a scooter. According to the communication circuit, a first withstand voltage boosting module comprises a withstand voltage controllable switching device and is used for being switched on or switched off under the control of a bias signal; data transmission between the first data port and the second data port is opened or closed, and the withstand voltage values of the first data port and the second data port are increased to a first voltage threshold value; the second withstand voltage boosting module comprises a withstand voltage unidirectional switching device and is used for sending a clock signal from the master device to the slave device and increasing the withstand voltage values of the first clock port and the second clock port to a second voltage threshold; the first response speed increasing module comprises a first impedance network and is used for increasing the level change rate of the first data port and the first clock port; and the second response speed increasing module comprises a second impedance network and is used for increasing the level change rate of the second data port and the second clock port. According to the I2C communication port provided by the embodiment of the invention, 100V voltage resistance can be realized, and the response speed is at a microsecond level.

Description

Technical Field

[0001] The present application relates to the technical field of communication circuits, and in particular to a communication circuit and a scooter. Background Art

[0002] Currently, vehicles, such as bicycles, scooters, etc., usually use I2C circuits to implement serial communications. The I2C serial bus is a bus that can be used for communication between a controller and one or more peripheral devices.

[0003] However, the voltage resistance of the I2C serial bus is generally poor, for example, the maximum voltage resistance is only 5V, and external interference or static electricity will cause permanent damage or failure of the controller or peripheral devices. In addition, the serial communication response speed of the I2C serial bus is also slow, which is also disadvantageous for the expected fast data transmission. Utility Model Content

[0004] In view of this, the embodiments of the present application provide a communication circuit and a scooter to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a communication circuit, wherein the communication circuit includes:

[0006] A first withstand voltage enhancement module is serially connected to a bidirectional data line between a first data port of a slave device and a second data port of a master device, and includes a withstand voltage controllable switch device, which is used to be turned on or off under the control of a bias signal to open or close the data transmission between the first data port and the second data port and to increase the withstand voltage values of the first data port and the second data port to a first voltage threshold;

[0007] A second voltage-resistant enhancement module, connected in series to a clock line between the first clock port of the slave device and the second clock port of the master device, comprises a voltage-resistant unidirectional switch device, and is used to send a clock signal from the master device to the slave device and to increase the voltage-resistant values of the first clock port and the second clock port to a second voltage threshold;

[0008] a first response speed improving module, the input end of which is connected to the first power supply end, the first output end of which is connected to the first data port, the second output end of which is connected to the first clock port, and the module includes a first impedance network for improving the level change rate of the first data port and the first clock port; and

[0009] The second response speed improvement module has an input end connected to the second power supply end, a first output end connected to the second data port, and a second output end connected to the second clock port, and includes a second impedance network for improving the level change rate of the second data port and the second clock port.

[0010] In combination with the first aspect, in an optional implementation manner, the voltage-resistant controllable switch device includes a first transistor module;

[0011] The first transistor module includes a control terminal, a first signal terminal, and a second signal terminal, and is configured to control the conduction or disconnection of the path between the first signal terminal and the second signal terminal under the control of the bias signal input at the control terminal, so as to open or close the data transmission between the first data port and the second data port.

[0012] In combination with the first aspect, in an optional implementation manner, the first transistor module includes at least one of the following: bipolar junction transistor; metal oxide semiconductor field effect transistor; insulated gate bipolar transistor; gate turn-off thyristor; silicon controlled rectifier; MOS controlled thyristor; integrated gate-commutated thyristor; electron injection enhanced gate transistor.

[0013] In combination with the first aspect, in an optional implementation manner, the first transistor module includes a first MOS transistor;

[0014] The control terminal of the first MOS transistor is configured to obtain the bias signal; the first end of the first MOS transistor is connected to the first data port; the second end of the first MOS transistor is connected to the second data port.

[0015] In combination with the first aspect, in an optional implementation manner, the voltage-resistant controllable switch device is connected to the first power supply terminal to obtain the bias signal.

[0016] In combination with the first aspect, in an optional implementation manner, the voltage-resistant controllable switch device further includes a fifth resistor;

[0017] The first end of the fifth resistor is connected to the first power supply terminal, and the second end of the fifth resistor is connected to the control terminal of the first MOS transistor.

[0018] In combination with the first aspect, in an optional implementation manner, the voltage-resistant unidirectional switch device includes a first diode;

[0019] The positive electrode of the first diode is connected to the first clock port, and the negative electrode of the first diode is connected to the second clock port.

[0020] In combination with the first aspect, in an optional implementation manner, the first impedance network includes a first resistor and a second resistor;

[0021] The first ends of the first resistor and the second resistor are respectively connected to the first power supply terminal, the second end of the first resistor is connected to the first data port, and the second end of the second resistor is connected to the first clock port.

[0022] In combination with the first aspect, in an optional embodiment, the second impedance network includes a third resistor and a fourth resistor;

[0023] The first ends of the third resistor and the fourth resistor are respectively connected to the second power supply terminal, the second end of the third resistor is connected to the second data port, and the second end of the fourth resistor is connected to the second clock port.

[0024] In a second aspect, an embodiment of the present application provides a scooter, characterized by including the communication circuit as described in the first aspect.

[0025] The beneficial effects brought by the technical solutions provided in the embodiments of the present application include: through the first voltage withstand improvement module including a voltage withstand controllable switch device and the second voltage withstand improvement module including a voltage withstand unidirectional switch device, the influences of surge, static electricity, hot plugging, voltage mutation, etc. can be isolated, the voltage withstand capabilities of the first data port, the second data port, the first clock port, and the second clock port are improved, and the system security is enhanced. And through the first response speed improvement module and the second response speed improvement module, response speed improvement measures can be respectively taken for the I2C port of the slave device and the I2C port of the master device, such as increasing the rising edge slope, so as to overall improve the I2C communication response speed, and the response speed is improved by using a hardware circuit.

[0026] The additional aspects and advantages of the embodiments of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the embodiments of the present application. Description of the Drawings

[0027] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. Among them, the drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of local features. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0028] Figure 1 It is a circuit schematic diagram of a specific example of an I2C circuit in the related art;

[0029] Figure 2 It is a circuit schematic diagram of Example 1 of the communication circuit in the embodiments of the present application;

[0030] Figure 3 It is a circuit schematic diagram of Example 2 of the communication circuit in the embodiments of the present application;

[0031] Figure 4 It is a circuit schematic diagram of Example 3 of the communication circuit in the embodiments of the present application. Detailed Embodiments

[0032] To make the technical solutions and beneficial effects of this application more obvious and understandable, the following will provide a detailed description by listing specific embodiments. Among them, the attached drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0033] The embodiments of this application are not an exhaustive list, but only schematic representations of some embodiments, and do not constitute a specific limitation on the protection scope of this application. Without contradiction, each step in an embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily. For example, the solution after removing some steps in an embodiment can also be implemented as an independent embodiment, and the order of the steps in an embodiment can be arbitrarily exchanged. In addition, the optional implementation manners in an embodiment can be combined arbitrarily; furthermore, the embodiments can be combined arbitrarily. For example, some or all of the steps of different embodiments can be combined arbitrarily, and an embodiment can be combined arbitrarily with the optional implementation manners of other embodiments.

[0034] In each embodiment of this application, if there is no special explanation and logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0035] The terms used in the embodiments of this application are only for the purpose of describing specific embodiments, and do not constitute a limitation on this application.

[0036] In the embodiments of this application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., can mean "one and only one", or can also mean "one or more", "at least one", etc. For example, in the case of using articles such as "a", "an", "the" in English translation, the noun after the article can be understood as a singular expression form or a plural expression form.

[0037] In the embodiments of this application, "a plurality of" means two or more.

[0038] In some embodiments, terms such as "at least one (at least one, at least one item, at least one)(at least one of)", "one or more (one or more)", "a plurality of (a plurality of)", "multiple (multiple)" and the like can be replaced with each other.

[0039] The prefix words such as "first" and "second" in the embodiments of the present application are only used to distinguish different described objects, and do not constitute limitations on the position, order, priority, value or content of the described objects. The description of the described objects refers to the description in the claims or the context of the embodiments, and should not constitute unnecessary limitations due to the use of prefix words. For example, the value of the described object is not limited by the ordinal number and can be one or more. Taking "the first device" as an example, the value of "device" can be one or more. In addition, the objects modified by different prefix words can be the same or different. For example, if the described object is "device", then "the first device" and "the second device" can be the same device or different devices, and their types can be the same or different.

[0040] In some embodiments, the term "signal" can represent a voltage signal or a current signal.

[0041] In some embodiments, the term "connection" can mean that there is a transfer of electrical signals or data between the connected end and the connected-to end, and can be understood as "electrical connection", "communication connection", etc. "Connection" can be a direct connection between two components, or an indirect connection established through other components, or a connection within two components, or any other possible connection form.

[0042] In the process of implementing the present application, the inventors found the following problems in the related art:

[0043] Figure 1 The circuit schematic diagram shows a specific example of an I2C circuit in the related art. As shown in the figure, the I2C circuit includes a peripheral device 1000 and a controller 2000. A serial clock line LSCL and a bidirectional serial data line LSDA are connected between the peripheral device 1000 and the controller 2000. A first zero-ohm resistor R100 is connected in series on the bidirectional serial data line LSDA, and a second zero-ohm resistor R200 is connected in series on the serial clock line LSCL.

[0044] The controller 2000 can be a master device, and the peripheral device 1000 can be a slave device. The serial clock line LSCL can be a clock signal line in I2C communication for transmitting clock signals. The clock signal can be provided by the master device to synchronize the data transmission of all devices on the I2C bus. The bidirectional serial data line LSDA can be a data signal line in I2C communication for transmitting data. The data can be sent by the master device to one or more slave devices or by one slave device to the master device and / or one or more slave devices under the synchronization of the clock signal.

[0045] However, the SDA and SCL pins of the controller 2000 are directly connected to the corresponding pins of the I2C of the peripheral device 1000 through the first zero-ohm resistor R100 and the second zero-ohm resistor R200 respectively. At this time, if the port voltage exceeds the withstand voltage value of the chip pin (such as 5V), the chip will be damaged and cause permanent failure, and there is no improvement measure for the transmission response speed. For example, due to operations such as plugging and unplugging of the battery, surges may occur on the I2C bus, or due to interference such as static electricity, signal mutations may also occur on the I2C bus. Even in some cases, battery failures, misoperations, etc. may occur, resulting in unexpected high voltages on the I2C bus, thus causing chip damage.

[0046] Therefore, an embodiment of the present application provides a communication circuit. Figure 2 The circuit schematic diagram of the first example of the communication circuit in the embodiment of the present application is shown. As shown in the figure, the communication circuit includes:

[0047] The first withstand voltage boosting module 30 is connected in series on the bidirectional data line between the first data port SDA1 of the slave device 10 and the second data port SDA2 of the master device 20, and includes a withstand voltage controllable switch device, which is used to conduct or disconnect under the control of the bias signal VB to open or close the data transmission between the first data port and the second data port and increase the withstand voltage values of the first data port SDA1 and the second data port SDA2 to the first voltage threshold;

[0048] The second withstand voltage boosting module 40 is connected in series on the clock line between the first clock port SCL1 of the slave device 10 and the second clock port SCL2 of the master device 20, and includes a withstand voltage unidirectional switch device, which is used to send a clock signal from the master device 20 to the slave device 10 and increase the withstand voltage values of the first clock port SCL1 and the second clock port SCL2 to the second voltage threshold;

[0049] The first response speed boosting module 50 has an input end connected to the first power supply terminal VDD1, a first output end connected to the first data port SDA1, and a second output end connected to the first clock port SCL1, and includes a first impedance network, which is used to increase the level change rate of the first data port SDA1 and the first clock port SCL1; and

[0050] The second response speed boosting module 60 has an input end connected to the second power supply terminal VDD2, a first output end connected to the second data port SDA2, and a second output end connected to the second clock port SCL2, and includes a second impedance network, which is used to increase the level change rate of the second data port SDA2 and the second clock port SCL2.

[0051] Thus, in the embodiments of the present application, by including a first voltage withstand improvement module including a voltage withstand controllable switch device and a second voltage withstand improvement module including a voltage withstand unidirectional switch device, the influences of surges, static electricity, hot plugging, voltage mutations, etc. can be isolated, the voltage withstand capabilities of the first data port, the second data port, the first clock port, and the second clock port are improved, and the system security is enhanced. Moreover, through the first response speed improvement module and the second response speed improvement module, response speed improvement measures can be respectively taken for the I2C port of the slave device and the I2C port of the master device, such as increasing the rising edge slope, thereby overall improving the I2C communication response speed and achieving the improvement of the response speed by using a hardware circuit.

[0052] In the embodiments of the present application, the voltage withstand controllable switch device may be a switch device with voltage withstand controllable bidirectional transmission, having the characteristic of high voltage withstand, and capable of controlled switching and bidirectional transmission. The voltage withstand unidirectional switch device may be a switch device with voltage withstand unidirectional transmission, having the characteristic of high voltage withstand, and capable of unidirectional transmission, that is, if the first end of the voltage withstand unidirectional switch device can transmit a signal to the second end, then the second end cannot transmit a signal to the first end. The voltage withstand controllable switch device and the voltage withstand unidirectional switch device may respectively adopt different names, and the names are not limited herein.

[0053] In some possible implementation manners, the voltage withstand controllable switch device may include at least one of the following: MOSFET (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as MOS transistor); BJT (Bipolar Junction Transistor, abbreviated as triode); IGBT (Insulated Gate Bipolar Transistor); GTO (Gate Turn-Off Thyristor); SCR (Silicon Controlled Rectifier); MCT (MOS Controlled Thyristor); IGCT (Integrated Gate Commutated Thyristor); IEGT (Injection Enhanced Gate Transistor).

[0054] In some possible implementation manners, the voltage withstand unidirectional switch device may include a diode, such as a zener diode, a rectifier diode, a TVS diode, etc.

[0055] In the embodiments of the present application, the voltage withstand controllable switch device and the voltage withstand unidirectional switch device also play a role in voltage isolation, and can be implemented by using transistors, etc., or can be implemented by using magnetic coupling devices and / or optical coupling devices.

[0056] In the embodiments of the present application, the first voltage withstand improvement module 30 and / or the second voltage withstand improvement module 40 may further include a filtering module, a ripple noise reduction module, etc., which can be set according to actual requirements.

[0057] In the embodiments of the present application, the first reference voltage (such as a positive power supply voltage, a negative power supply voltage, or ground) provided by the first power supply terminal VDD1 and the second reference voltage (such as a positive power supply voltage, a negative power supply voltage, or ground) provided by the second power supply terminal VDD2 can be set according to actual requirements. For example, the first power supply voltage can be less than or greater than the second power supply voltage. Preferably, both the first reference voltage and the second reference voltage are positive power supply voltages, and the first reference voltage is less than the second reference voltage.

[0058] In the embodiments of the present application, the first impedance network and the second impedance network can provide equivalent resistance, so that according to the equivalent resistance and the load capacitance, the rise time and the fall time can be reduced, and the change rate of the I2C port level can be improved.

[0059] In some possible implementation manners, the first impedance network and the second impedance network can include resistors, or can be passive RC networks including resistors and capacitors, or can be active impedance networks including operational amplifiers, etc.

[0060] In the embodiments of the present application, the first voltage threshold can be determined based on a voltage withstand controllable switch device. For example, if the voltage withstand of the voltage withstand controllable switch device is 100V, then the first voltage threshold can be 100V. Similarly, the second voltage threshold can be determined based on a voltage withstand unidirectional switch device. For example, if the voltage withstand of the voltage withstand unidirectional switch device is 100V, then the second voltage threshold can be 100V.

[0061] In an alternative embodiment, the voltage withstand controllable switch device includes a first transistor module;

[0062] The first transistor module includes a control terminal, a first signal terminal, and a second signal terminal, and is configured to conduct or disconnect the path between the first signal terminal and the second signal terminal under the control of the bias signal input at the control terminal, so as to open or close the data transmission between the first data port and the second data port.

[0063] In an alternative embodiment, the first transistor module includes at least one of the following: bipolar junction transistor; metal oxide semiconductor field effect transistor; insulated gate bipolar transistor; gate turn-off thyristor; silicon controlled rectifier; MOS controlled thyristor; integrated gate commutated thyristor; electron injection enhanced gate transistor.

[0064] Figure 3 The circuit schematic diagram of Example 2 of the communication circuit in the embodiments of the present application is shown. As shown in the figure, in an alternative embodiment, the first transistor module includes a first MOS transistor Q1;

[0065] The control terminal of the first MOS transistor Q1 is configured to obtain the bias signal VB; the first terminal of the first MOS transistor Q1 is connected to the first data port SDA1; the second terminal of the first MOS transistor Q1 is connected to the second data port SDA2.

[0066] Exemplarily, the first MOS transistor Q1 may be an NMOS transistor. Those skilled in the art should understand that the first MOS transistor Q1 may also be a PMOS transistor. If the first MOS transistor Q1 is an NMOS transistor, then the control terminal of the first MOS transistor Q1 may be the gate, the first terminal of the first MOS transistor Q1 may be the source, and the second terminal of the first MOS transistor Q1 is the drain.

[0067] In this way, by using a MOS transistor, the breakdown voltage withstand ability can be improved, and the switching speed can be increased, thereby further enhancing the response speed.

[0068] In an alternative embodiment, the breakdown voltage controllable switch device is connected to the first power supply terminal VDD1 to obtain the bias signal VB.

[0069] In an alternative embodiment, the breakdown voltage controllable switch device further includes a fifth resistor R5;

[0070] The first terminal of the fifth resistor R5 is connected to the first power supply terminal VDD1, and the second terminal of the fifth resistor R5 is connected to the control terminal of the first MOS transistor Q1.

[0071] In this way, by connecting the control terminal of the first MOS transistor Q1 to the first power supply terminal VDD1 through the fifth resistor R5, the first reference signal provided by the first power supply terminal VDD1 can be divided, realizing the normal driving of the first MOS transistor Q1, and also reducing the interference of surges, static electricity, etc., and improving the stability of data transmission.

[0072] In the embodiments of the present application, the first resistor R1 can also cooperate with the fifth resistor R5 to divide the voltage, provide the gate-source voltage drop, and improve the stability of data transmission. Exemplarily, the first resistor R1 may be a hundred times or a thousand times that of the fifth resistor R5.

[0073] In an alternative embodiment, the breakdown voltage unidirectional switch device includes a first diode D1;

[0074] The positive electrode of the first diode D1 is connected to the first clock port SCL1, and the negative electrode of the first diode D1 is connected to the second clock port SCL2.

[0075] In this way, through the first diode D1, the breakdown voltage withstand ability can be improved. And the clock signal is transmitted from the second clock port SCL2 to the first clock port SCL1, preventing the reverse flow of current and protecting the safety of the device.

[0076] In an alternative embodiment, the first impedance network includes a first resistor R1 and a second resistor R2;

[0077] The first end of the first resistor R1 and the first end of the second resistor R2 are respectively connected to the first power supply terminal VDD1. The second end of the first resistor R1 is connected to the first data port SDA1, and the second end of the second resistor R2 is connected to the first clock port SCL1.

[0078] In an alternative embodiment, the second impedance network includes a third resistor R3 and a fourth resistor R4;

[0079] The first end of the third resistor R3 and the first end of the fourth resistor R4 are respectively connected to the second power supply terminal VDD2. The second end of the third resistor R3 is connected to the second data port SDA2, and the second end of the fourth resistor R4 is connected to the second clock port SCL2.

[0080] In this way, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 can serve as pull-up resistors, respectively implementing the pull-up resistor setting for the I2C ports of the slave device and the I2C ports of the master device, so as to be more compatible with different ports, reduce the product with the load capacitance, reduce the time of the rising edge and the falling edge, and provide the response speed. For example, the response speed can be increased to the microsecond level.

[0081] Exemplarily, the first reference voltage can be 3.3V, and the second reference voltage can be 5V. Then, the first resistor R1 can be smaller than the third resistor R3, and the second resistor R2 can be equal to the fourth resistor R4. Exemplarily, the first resistor R1 can be 1.5 kΩ, the second resistor R2 can be 1 kΩ, the third resistor R3 can be 2.2 kΩ, and the fourth resistor R4 can be 1 kΩ.

[0082] Figure 4 The circuit schematic diagram of Example 3 of the communication circuit in the embodiment of the present application is shown. As shown in the figure, in an alternative embodiment, a sixth resistor R6 and an eighth resistor R8, as well as a seventh resistor R7 and a ninth resistor R9, can also be respectively connected in series on the bidirectional data line and the clock line as anti-interference resistors, which can eliminate overshoot or undershoot, etc.

[0083] Exemplarily, the anti-interference resistor can be less than 1 kΩ, such as dozens of ohms.

[0084] When the master device 20 and the slave device 10 are communicating normally, data can be transmitted bidirectionally between the master device 20 and the slave device 10 through the bidirectional data line. And if the second clock port SCL2 of the master device 20 sends a low-level signal to the first clock port SCL1 of the slave device 10, due to the unidirectional conduction characteristic of the diode, the anode of the diode will be pulled low, so that the first clock port SCL1 of the slave device 10 can receive the low level. If the second clock port SCL2 of the master device 20 sends a high-level signal to the first clock port SCL1 of the slave device 10, due to the unidirectional conduction characteristic of the diode, the level of the anode of the diode will be pulled high by the second resistor R2, so that the first clock port SCL1 of the slave device 10 can receive the high level.

[0085] In the embodiments of the present application, each component can be single or multiple in series and / or in parallel. For example, a resistor can be a single resistor, or multiple resistors in series and / or in parallel, and can also include a passive resistor network or an active resistor network such as resistors, capacitors, inductors, etc.

[0086] In the embodiments of the present application, the master device can be a circuit with signal processing capabilities. In one implementation, the master device can be a circuit with instruction reading and running capabilities, such as a Central Processing Unit (CPU), a microprocessor, a graphics processing unit (GPU) (which can be understood as a kind of microprocessor), or a digital signal processor (DSP), etc.; in another implementation, the master device can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a Neural Network Processing Unit (NPU), a Tensor Processing Unit (TPU), a Deep learning Processing Unit (DPU), etc.

[0087] The slave device can respond according to the instructions of the master device and can be a sensor, a memory chip, etc. For example, the sensor can include a six-axis / six-degree-of-freedom (6DoF) sensor, etc.

[0088] The embodiments of the present application also provide a scooter, including the communication circuit as described in the above embodiments. Therefore, the voltage withstand capacity and communication response speed of the I2C communication port can be improved.

[0089] It should be understood that the above embodiments are all exemplary and do not cover all possible implementation manners included in the claims. Without departing from the scope of the present disclosure, various deformations and changes can also be made on the basis of the above embodiments. Similarly, the technical features of the above embodiments can also be arbitrarily combined to form additional embodiments of the present application that may not be clearly described. Therefore, the above embodiments only represent several implementation manners of the present application and do not limit the protection scope of the patent of the present application.

Claims

1. A communication circuit, characterized in that, The communication circuit includes: A first breakdown voltage boosting module, connected in series to a bidirectional data line between a first data port of a slave device and a second data port of a master device, including a breakdown voltage controllable switch device, configured to conduct or disconnect under the control of a bias signal to open or close data transmission between the first data port and the second data port and increase the breakdown voltage values of the first data port and the second data port to a first voltage threshold; A second breakdown voltage boosting module, connected in series to a clock line between a first clock port of the slave device and a second clock port of the master device, including a breakdown voltage unidirectional switch device, configured to send a clock signal from the master device to the slave device and increase the breakdown voltage values of the first clock port and the second clock port to a second voltage threshold; A first response speed boosting module, with an input terminal connected to a first power supply terminal, a first output terminal connected to the first data port, and a second output terminal connected to the first clock port, including a first impedance network, configured to increase the level change rate of the first data port and the first clock port; and A second response speed boosting module, with an input terminal connected to a second power supply terminal, a first output terminal connected to the second data port, and a second output terminal connected to the second clock port, including a second impedance network, configured to increase the level change rate of the second data port and the second clock port.

2. The communication circuit according to claim 1, wherein The breakdown voltage controllable switch device includes a first transistor module; The first transistor module includes a control terminal, a first signal terminal, and a second signal terminal, configured to conduct or disconnect the path between the first signal terminal and the second signal terminal under the control of the bias signal input at the control terminal to open or close data transmission between the first data port and the second data port.

3. The communication circuit according to claim 2, wherein The first transistor module includes at least one of the following: bipolar junction transistor; metal oxide semiconductor field effect transistor; insulated gate bipolar transistor; gate turn-off thyristor; silicon controlled rectifier; MOS controlled thyristor; integrated gate-commutated thyristor; electron injection enhanced gate transistor.

4. The communication circuit according to claim 2, characterized in that, The first transistor module includes a first MOS transistor; The control terminal of the first MOS transistor is configured to obtain the bias signal; the first terminal of the first MOS transistor is connected to the first data port; the second terminal of the first MOS transistor is connected to the second data port.

5. The communication circuit according to claim 1, wherein The breakdown voltage controllable switch device is connected to the first power supply terminal to obtain the bias signal.

6. The communication circuit according to claim 4, characterized in that, The breakdown voltage controllable switch device further includes a fifth resistor; The first end of the fifth resistor is connected to the first power supply terminal, and the second end of the fifth resistor is connected to the control terminal of the first MOS transistor.

7. The communication circuit according to claim 1, wherein The breakdown voltage unidirectional switch device includes a first diode; The positive electrode of the first diode is connected to the first clock port, and the negative electrode of the first diode is connected to the second clock port.

8. The communication circuit according to claim 1, wherein The first impedance network includes a first resistor and a second resistor; The first ends of the first resistor and the second resistor are respectively connected to the first power supply terminal, the second end of the first resistor is connected to the first data port, and the second end of the second resistor is connected to the first clock port.

9. The communication circuit according to any one of claims 1-8, characterized in that, The second impedance network includes a third resistor and a fourth resistor; The first ends of the third resistor and the fourth resistor are respectively connected to the second power supply terminal, the second end of the third resistor is connected to the second data port, and the second end of the fourth resistor is connected to the second clock port.

10. A scooter, characterized in that, It includes the communication circuit according to any one of claims 1-9.

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