10-gigabit optical-to-electricity conversion module and assembly using same

Abstract

The utility model provides a ten-gigabit optical-to-electricity module and an assembly using the same, the ten-gigabit optical-to-electricity module comprises a PHY unit, an MCU unit and a power supply unit, the PHY unit is connected with the MCU unit, the power supply unit is connected with the PHY unit and the MCU unit through a filtering unit, and the PHY unit is respectively connected with a crystal oscillator unit and a network transformer unit. The number of the light-to-electricity modules is two, the light-to-electricity modules are a first light-to-electricity module and a second light-to-electricity module, the first light-to-electricity module and the second light-to-electricity module are connected through a network cable, and the first light-to-electricity module is connected with the network card through a golden finger. According to short-distance communication requirements, a pure electric optical module and a transceiving module for transmitting service signals by using a network cable and an existing switch optical port are developed, the service rate can reach 10Gbps, the purpose of communication is achieved, the cost is saved, the labor is reduced, the waste is reduced, and the environment is protected.

Description

Technical Field

[0001] The utility model relates to the fields of optical communication and circuits, in particular to a 10 Gigabit optical-to-electrical conversion module and a component applying the same. Background Art

[0002] At present, various optical fibers are basically used as transmission media in the field of optical communication, and optical-to-electrical conversion, electrical-to-optical conversion and transmission of high-speed service signals are carried out through optical modules.

[0003] Fiber optic communication requires laying long-distance optical cables (hundreds of meters or even hundreds of kilometers), and the core components of the optical module itself are optical transmit lasers and optical receivers, as well as corresponding control, drive, signal processing, clock data recovery electrical chips, etc., which are all a considerable cost.

[0004] For early communication systems, network cables are a low-cost, mature and widely laid signal transmission medium, suitable for short-distance communication, but conventional optical modules cannot be used. Summary of the Utility Model

[0005] Therefore, an object of the present utility model is to provide a 10 Gigabit optical-to-electrical conversion module and a component applying the same to solve the problems mentioned in the background art and overcome the deficiencies in the prior art.

[0006] To achieve the above object, the present utility model adopts the following technical solutions:

[0007] A 10 Gigabit optical-to-electrical conversion module includes a PHY unit, an MCU unit and a power supply unit. The PHY unit is connected to the MCU unit, and the power supply unit is connected to the PHY unit and the MCU unit through a filtering unit. The PHY unit is respectively connected to a crystal oscillator unit and a network transformer unit.

[0008] Further, the PHY unit is implemented through a PHY circuit. The PHY circuit includes a PHY chip. The transceiver interface pins of the PHY chip are connected to the network transformer unit. The clock pin of the PHY chip is connected to the crystal oscillator unit. The power pins of the PHY chip are connected to the power supply unit and the filtering unit. The ground pin of the PHY chip is grounded.

[0009] Further, the MCU unit is implemented by an MCU circuit, and the MCU circuit includes an MCU chip. The first pin of the MCU chip is connected to the interrupt pin of the PHY chip, the second pin of the MCU chip is connected to the enable pin of the PHY chip, the third pin of the MCU chip is connected to the reset pin of the PHY chip, the fourth pin of the MCU chip is connected to the management interface pin of the PHY chip, the fifth pin of the MCU chip is connected to the network transformer unit, the power pin of the MCU chip is connected to the power supply unit and the filtering unit, and the ground pin of the MCU chip is grounded.

[0010] Further, the network transformer unit is implemented by a network transformer circuit, and the network transformer circuit includes an RJ45 connector and a network transformer. The output end of the network transformer is connected to the RJ45 connector, and the input end of the network transformer is connected to the transceiver interface pin of the PHY chip.

[0011] Further, the power supply unit is implemented by a power supply circuit, and the power supply circuit includes a field effect transistor, a first voltage converter and a second voltage converter. The power supply circuit provides voltage sources of 3.3V, 1.9V and 1.0V respectively.

[0012] Further, the filtering unit is implemented by a filtering circuit, and the filtering circuit includes an analog power supply filtering circuit, a digital power supply filtering circuit and a Serdes power supply filtering circuit. The input ends of the analog power supply filtering circuit, the digital power supply filtering circuit and the Serdes power supply filtering circuit are all connected to the power supply circuit, and the output ends of the analog power supply filtering circuit, the digital power supply filtering circuit and the Serdes power supply filtering circuit are all connected to the PHY circuit.

[0013] Further, the crystal oscillator unit is implemented by a crystal oscillator circuit, and the crystal oscillator circuit includes a crystal oscillator Y1. The first output end and the second output end of the crystal oscillator Y1 are connected to the PHY circuit, and the ground end of the crystal oscillator Y1 is grounded.

[0014] The present utility model also provides a component, which includes the above-mentioned 10G optical-to-electrical conversion module, and also includes a network card. There are two of the above-mentioned 10G optical-to-electrical conversion modules, namely a first optical-to-electrical conversion module and a second optical-to-electrical conversion module. The first optical-to-electrical conversion module and the second optical-to-electrical conversion module are connected by a network cable, and the first optical-to-electrical conversion module and the network card are connected by a gold finger.

[0015] Therefore, the present utility model has the following beneficial effects:

[0016] A 10Gigabit optical-to-electrical conversion module of the present utility model and a component applying the same. Corresponding to short-distance communication requirements, a pure electrical optical module is developed, which is a transceiver module that uses network cables and existing optical ports of switches to transmit service signals. The service rate can reach 10 Gbps, achieving the communication purpose while saving costs, reducing labor, reducing waste, and protecting the environment.

[0017] Additional aspects and advantages of the present utility model will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present utility model will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

[0019] Figure 1 is a functional block diagram of a 10Gigabit optical-to-electrical conversion module and its components of the present utility model;

[0020] Figure 2 is a schematic diagram of the PHY circuit of the present utility model;

[0021] Figure 3 is a schematic diagram of the MCU circuit of the present utility model;

[0022] Figure 4 is a schematic diagram of the network transformer circuit of the present utility model;

[0023] Figure 5-1 and Figure 5-2 is a schematic diagram of the power supply circuit of the present utility model;

[0024] Figure 6-1 、 Figure 6-2 and Figure 6-3 is a schematic diagram of the filter circuit of the present utility model;

[0025] Figure 7 is a schematic diagram of the crystal oscillator circuit of the present utility model;

[0026] Figure 8 is a schematic diagram of the SFP connector circuit of the embodiment of the present utility model;

[0027] Figure 9 is a diagram of the receiving and transmitting test results of the 10Gigabit optical-to-electrical conversion module of the embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] Embodiments of the present utility model will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present utility model, and should not be construed as a limitation of the present utility model.

[0029] In the present utility model, unless otherwise clearly defined and limited, terms such as "installation", "connection", "connection", "fixation" and other terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0030] A 10 Gigabit optical-to-electrical conversion module includes a PHY unit, an MCU unit, and a power supply unit. The PHY unit is connected to the MCU unit, and the power supply unit is connected to the PHY unit and the MCU unit through a filtering unit. The PHY unit is respectively connected with a crystal oscillator unit and a network transformer unit.

[0031] Furthermore, the PHY unit is implemented through a PHY circuit. The PHY circuit includes a PHY chip. The transceiver interface pins of the PHY chip (i.e., the MDIAN, MDIAP, MDIBP, MDIBN, MDICN, MDICP, MDIDP, MDIDN pins of the PHY chip) are connected to the network transformer unit. The clock pins of the PHY chip (i.e., the XTAL_N, XTAL_P of the PHY chip) are connected to the crystal oscillator unit. The power pins of the PHY chip are connected to the power supply unit and the filtering unit, and the ground pins of the PHY chip are grounded.

[0032] More specifically, the PHY circuit is as Figure 2As shown, the PHY circuit includes PHY chip U1, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, capacitor C21, capacitor C34, capacitor C35, capacitor C36, capacitor C37, capacitor C51. The model of PHY chip U1 is RTL8261BE. The AGND_PHY pin, SGND pin, EPAD_AGND pin, and EPAD_DGND pin of PHY chip U1 are all grounded. The DVDDL pin of PHY chip U1 is connected to the DVDDLS power supply. The DVDDIO18 pin of PHY chip U1 is connected to the DVDDIOLS power supply. The DVDDIOLED pin of PHY chip U1 is connected to DVDDIO_3.3V power supply. The AVDDH_PHY1 pin, AVDDH_PHY7 pin, and AVDDH_PHY14 pin of PHY chip U1 are all connected to the AVDDH_PHY0 power supply. The AVDDL_PHY8 pin and AVDDL_PHY13 pin of PHY chip U1 are both connected to the AVDDL_PHY0 power supply. The AVDDH_PLL_BASE pin of PHY chip U1 is connected to the AVDDH_PLL0 power supply. The AVDDL_PLL_BASE pin of PHY chip U1 is connected to the AVDDL_PLL0 power supply. The SVDDL_CK pin of PHY chip U1 is connected to the SVDD0_CK power supply. The SVDDL_TR pin of PHY chip U1 is connected to the SVDD0_TRX power supply. The NRESET pin of PHY chip U1 is respectively connected to one end of resistor R12 and one end of capacitor C51. The other end of resistor R12 is connected to the DVDDIOLS power supply, and the other end of capacitor C51 is grounded. The CLK_SEL pin of PHY chip U1 is connected to one end of resistor R11, and the other end of resistor R11 is grounded. The SIN pin of PHY chip U1 is connected to one end of capacitor C34. The SIP pin of PHY chip U1 is connected to one end of capacitor C35. The S0N pin of PHY chip U1 is connected to one end of capacitor C36. The SOP pin of PHY chip U1 is connected to one end of capacitor C37. The PHYAD0 pin of PHY chip U1 is connected to one end of resistor R7, and the other end of resistor R7 is grounded. The PHYAD1 pin of PHY chip U1 is connected to one end of resistor R6, and the other end of resistor R6 is grounded. The PHYAD2 pin of PHY chip U1 is connected to one end of resistor R8, and the other end of resistor R8 is grounded. The PHYAD3 pin of PHY chip U1 is connected to one end of resistor R9, and the other end of resistor R9 is grounded. The PHYAD4 pin of PHY chip U1 is connected to one end of resistor R10, and the other end of resistor R10 is grounded. The INT pin of PHY chip U1 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the VDDHID power supply. The MDI_ORDER pin of PHY chip U1 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the DVDDIOLS power supply. The PHY_DIS pin of PHY chip U1 is connected to one end of resistor R3, and the other end of resistor R3 is connected to the DVDDIOLS power supply. The REST pin of PHY chip U1 is grounded through resistor R1. The MDIO pin of PHY chip U1 is respectively connected to one end of capacitor C21 and one end of resistor R2. The other end of capacitor C21 is grounded, and the other end of resistor R2 is connected to the DVDDIO_3.3V power supply.

[0033] Further, the MCU unit is implemented through an MCU circuit. The MCU circuit includes an MCU chip. The first pin (PB4) of the MCU chip is connected to the interrupt pin (INT) of the PHY chip. The second pin (PA11) of the MCU chip is connected to the enable pin (PHY_DIS) of the PHY chip. The third pin (PA12) of the MCU chip is connected to the reset pin (NRESET) of the PHY chip. The fourth pin (PA10) of the MCU chip is connected to the management interface pin (MDIO) of the PHY chip. The fifth pin (PB6 and PB7) of the MCU chip is connected to the network transformer unit. The power pin of the MCU chip is connected to the power supply unit and the filtering unit. The ground pin of the MCU chip is grounded.

[0034] More specifically, the MCU circuit is as Figure 3As shown in the figure, the MCU circuit includes an MCU chip U2, capacitors C59, C70, C75, C76, C77, C78, resistors R13, R14, R15, R16, R17, R18, R19, R20, R28, R29, and R30. The model of the MCU chip is GD32E232K8Q7. One end of resistor R20 is connected to the PF0 pin of MCU chip U2, and the other end of resistor R20 is grounded. One end of capacitor C59 and one end of resistor R19 are respectively connected to the NRST pin of MCU chip U2. The other end of capacitor C59 is grounded, and the other end of resistor R19 is connected to the VCC_3.3V power supply. The VREF pin of MCU chip U2 is grounded through capacitor C70. One end of capacitor C75, one end of capacitor C76, and the VCC_3.3V power supply are respectively connected to the VDDA pin of MCU chip U2. The other ends of capacitor C75 and capacitor C76 are grounded. One end of resistor R28 is connected to the PA3 pin of MCU chip U2. The other end of resistor R28 is respectively connected to one end of resistor R29 and one end of resistor R30. The other end of resistor R29 is connected to the VCC_3.3V power supply, and the other end of resistor R30 is connected to the PHY_DIS pin of PHY chip U1. One end of capacitor C77, one end of capacitor C78, and the VCC_3.3V power supply are respectively connected to the VDD pin of MCU chip U2. The other ends of capacitor C77 and capacitor C78 are both grounded. The PA8 pin of MCU chip U2 is connected to the VDD pin of MCU chip U2. The PA9 pin of MCU chip U2 is connected to the MDC pin of PHY chip U1. The PA10 pin of MCU chip U2 is connected to the MDIO pin of PHY chip U1. The PA11 pin of MCU chip U2 is connected to the PHY_DIS pin of PHY chip U1. The PA12 pin of MCU chip U2 is connected to the NRESET pin of PHY chip U1. One end of resistor R18 is connected to the PA15 pin of MCU chip U2. The other end of resistor R18 is respectively connected to one end of resistor R16, one end of resistor R15, and the VCC_3.3V power supply. One end of resistor R14 is connected to the PB3 pin of MCU chip U2. The other end of resistor R14 is respectively connected to one end of resistor R16, one end of resistor R15, and the VCC_3.3V power supply. One end of resistor R13 and the INT pin of PHY chip U1 are respectively connected to the PB4 pin of MCU chip U2. The other end of resistor R13 is respectively connected to one end of resistor R16, one end of resistor R15, and the VCC_3.3V power supply. One end of resistor R17 is connected to the PB9 pin of MCU chip U2. The other end of resistor R17 is grounded. The PGND pin of MCU chip U2 is grounded.

[0035] The MCU unit / circuit is used to provide the initialization information and control configuration information of the PHY.

[0036] Further, the network transformer unit is implemented through a network transformer circuit, which includes an RJ45 connector and a network transformer. The output end of the network transformer is connected to the RJ45 connector, and the input ends (the second, third, fifth, sixth, eighth, ninth, eleventh, and twelfth ends of network transformer U6) of the network transformer are connected to the transceiver interface pins of the PHY chip.

[0037] More specifically, the network transformer circuit is as Figure 4As shown, the network transformer circuit includes an RJ45 connector J2, a network transformer U6, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a capacitor C89, a capacitor C90, a capacitor C91, a capacitor C92, a capacitor C93, a capacitor C94, a capacitor C95, a capacitor C96, a capacitor C97, a capacitor C98, an inductor LP2, and an inductor L6. The model of the network transformer U6 is T24P03SW. The network transformer U6 has 24 pin ports, and the RJ45 connector J2 has eight pin ports. The first end, the fourth end, the seventh end, and the tenth end of the network transformer U6 are short-circuited. The second end of the network transformer U6 is connected to the MDIDN pin of the PHY chip U1. The third end of the network transformer U6 is connected to the MDIDP pin of the PHY chip U1. The fifth end of the network transformer U6 is connected to the MOICN pin of the PHY chip U1. The sixth end of the network transformer U6 is connected to the MDICP pin of the PHY chip U1. The eighth end of the network transformer U6 is connected to the MDIBN pin of the PHY chip U1. The ninth end of the network transformer U6 is connected to the MDIBP pin of the PHY chip U1. The eleventh end of the network transformer U6 is connected to the MDIAN pin of the PHY chip U1. The twelfth end of the network transformer U6 is connected to the MDIAP pin of the PHY chip U1. The fifteenth end of the network transformer U6 is connected to one end of a capacitor C88 through a resistor R34. The eighteenth end of the network transformer U6 is connected to one end of the capacitor C88. The twenty-first end of the network transformer U6 is connected to one end of the capacitor C88. The twenty-fourth end of the network transformer U6 is connected to one end of the capacitor C88. The other end of the capacitor C88 is grounded. The thirteenth end of the network transformer U6 is connected to the first end of the RJ45 connector J2. The fourteenth end of the network transformer U6 is connected to the second end of the RJ45 connector J2. The sixteenth end of the network transformer U6 is connected to the third end of the RJ45 connector J2. The seventeenth end of the network transformer U6 is connected to the fourth end of the RJ45 connector J2. The nineteenth end of the network transformer U6 is connected to the fifth end of the RJ45 connector J2. The twentieth end of the network transformer U6 is connected to the sixth end of the RJ45 connector J2. The twenty-second end of the network transformer U6 is connected to the seventh end of the RJ45 connector J2. The twenty-third end of the network transformer U6 is connected to the eighth end of the RJ45 connector J2. One end of the capacitor C89 is connected to the first end of the inductor LP2 and the AVDDHS power supply respectively, and the other end of the capacitor C89 is grounded. The capacitor C90 is connected in parallel with the capacitor C89. The other end of the inductor LP2 is connected to one end of the capacitor C91 and one end of the inductor L6 respectively. The other end of the capacitor C91 is grounded. The capacitor C92 is connected in parallel with the capacitor C91. The other end of the inductor L6 is connected to one end of the capacitor C93 and the first end of the network transformer U6 respectively. The other end of the capacitor C93 is grounded. The capacitors C94, C95, C96, C97, and C98 are all connected in parallel with the capacitor C93.

[0038] As an implementation, the network transformer unit further includes an SFP connector circuit. As Figure 8 shown, the SFP connector circuit includes an SFP connector J1, resistors R21, R22, R23, R24, R25, R26, and R27. The VEET1 pin, MOD_ABS pin, VEER1 pin, VEER2 pin, VEER3 pin, VEET2 pin, and VEET3 pin of the SFP connector J1 are all grounded. The Tx_F pin of the SFP connector J1 is connected to the PB3 pin of the MCU chip U2. The Tx_DIS pin of the SFP connector J1 is connected to the other end of the resistor R28 and one end of the resistor R21 respectively. The other end of the resistor R21 is connected to the VCC_3.3V power supply. The SDA pin of the SFP connector J1 is connected to the PB7 pin of the MCU chip U2 and the other end of the resistor R16 respectively. The SCL pin of the SFP connector J1 is connected to the PB6 pin of the MCU chip U2 and the other end of the resistor R15 respectively. The RS0 pin of the SFP connector J1 is connected to one end of the resistor R24. The other end of the resistor R24 is connected to one end of the resistor R22 and one end of the resistor R26 respectively. The other end of the resistor R22 is connected to the VCC_3.3V power supply. The other end of the resistor R26 is grounded. The LOS pin of the SFP connector J1 is connected to the PA15 pin of the MCU chip U2. The RS1 pin of the SFP connector J1 is connected to one end of the resistor R25. The other end of the resistor R25 is connected to one end of the resistor R23 and one end of the resistor R27 respectively. The other end of the resistor R23 is connected to the VCC_3.3V power supply. The other end of the resistor R27 is grounded. The RD- pin of the SFP connector J1 is connected to the other end of the capacitor C36. The RD+ pin of the SFP connector J1 is connected to the other end of the capacitor C37. The VCCR pin and VCCT pin of the SFP connector J1 are both connected to the VCC_IN power supply. The TD+ pin of the SFP connector J1 is connected to the other end of the capacitor C35. The TD- pin of the SFP connector J1 is connected to the other end of the capacitor C34.

[0039] The network transformer unit / circuit provides electrical isolation between the PHY side and the network cable transmission medium side.

[0040] Furthermore, the power supply unit is implemented through a power supply circuit. The power supply circuit includes a field effect transistor, a first voltage converter, and a second voltage converter. The power supply circuit provides voltage sources of 3.3V, 1.9V, and 1.0V respectively.

[0041] More specifically, the power supply circuit is as Figure 5-1 and Figure 5-2As shown, the power supply circuit includes a field effect transistor U3, a first voltage converter U4, a second voltage converter U5, capacitors PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC11, PC12, PC13, PC14, PC15, PC16, PC17, PC18, PC19, PC20, PC21, PC22, PC23, PC24, PC25, PC26, PC27, PC28, PC29, PC30, PC31, PC32, PC33, PC34, PC35, PC36, PC37, PC38, PC39, PC40, PC41, PC42, PC43, PC44, PC45, PC46, PC47, resistors RR1, RR2, RR3, RR4, RR5, RR6, inductors L5, PL1, PL2, PL3, PL4, PL5, PL6, PL7, PL8. The models of the first voltage converter U4 and the second voltage converter U5 are both JW5252. The S terminal of the field effect transistor U3 is connected to the VCC_IN power supply. The G terminal of the field effect transistor U3 is grounded through the resistor PR1. One end of the capacitor PC1 is connected to the S terminal of the field effect transistor U3, and the other end of the capacitor PC1 is connected to the G terminal of the field effect transistor U3. The D terminal of the field effect transistor U3 is connected to one end of the inductor L5. The other end of the inductor L5 is grounded through the capacitor PC2. The other end of the inductor L5 outputs the VCC_3.3V power supply signal. The EN pin of the first voltage converter U4 is connected to the VCC_3.3V power supply. The VIN pin of the first voltage converter U4 is respectively connected to VCC_3.One end of the 3V power supply is connected to one end of the capacitor PC11, the other end of the capacitor PC11 is grounded, the GND pin of the first voltage converter U4 is grounded, the SW pin of the first voltage converter U4 is connected to one end of the inductor PL3, the other end of the inductor PL3 is grounded through the capacitor PC4, the capacitors PC5, PC6, and PC7 are all connected in parallel with the capacitor PC4, the other end of the inductor PL3 outputs the DVDDLS power supply signal, the FB pin of the first voltage converter U4 is respectively connected to one end of the capacitor PC3, one end of the resistor PR2, and one end of the resistor PR3, the other end of the capacitor PC3 is respectively connected to the other end of the inductor PL3 and one end of the capacitor PC18, the other end of the resistor PR2 is respectively connected to the other end of the inductor PL3 and one end of the capacitor PC18, the other end of the resistor PR3 is grounded, the other end of the capacitor PC18 is grounded, the inductor PL1 and the inductor PL2 are connected in parallel, one end of the inductor PL1 is connected to the DVDDLS power supply, the other end of the inductor PL1 outputs the AVDDLS power supply signal, one end of the capacitor PC12 is connected to the DVDDLS power supply, the other end of the capacitor PC12 is grounded, the capacitors PC13, PC14, PC15, PC16, and PC17 are all connected in parallel with the capacitor PC12.

[0042] The connection method of the second voltage converter U5 is the same as that of the first voltage converter U4, which will not be elaborated here. The difference lies in the specification parameters of the connected capacitors, resistors and other components. The VCC_3.3V power supply is used as the input to output the DVDDIOLS power supply signal. The inductor PL5 and the inductor PL6 are connected in parallel, one end of the inductor PL5 is connected to the DVDDIOLS power supply, the other end of the inductor PL1 outputs the AVDDHS power supply signal, one end of the capacitor PC29 is connected to the DVDDIOLS power supply, the other end of the capacitor PC29 is grounded, the capacitors PC30, PC31, PC32, PC33, and PC34 are all connected in parallel with the capacitor PC29, one end of the inductor PL7 is connected to the VCC_3.3V power supply, the other end of the inductor PL7 is connected to one end of the capacitor PC35, the other end of the capacitor PC35 is grounded, the capacitors PC36, PC37, PC38, PC39, PC40, and PC41 are all connected in parallel with the capacitor PC35, the other end of the inductor PL7 outputs the VDDH power supply signal, one end of the capacitor PC42 is connected to the VDDH power supply, the other end of the capacitor PC42 is grounded, the capacitors PC43, PC44, PC45, PC46, and PC47 are all connected in parallel with the capacitor PC42, one end of the inductor PL8 is connected to the VDDH power supply, the other end of the inductor PL8 outputs the DVDDIO_3.3V power supply signal.

[0043] The power supply circuit / unit supplies power to the PHY circuit / unit with voltages of 1.9V and 1.0V other than 3.3V.

[0044] Furthermore, the filtering unit is implemented by a filtering circuit, which includes an analog power supply filtering circuit, a digital power supply filtering circuit, and a Serdes power supply filtering circuit. The input ends of the analog power supply filtering circuit, the digital power supply filtering circuit, and the Serdes power supply filtering circuit are all connected to the power supply circuit, and the output ends of the analog power supply filtering circuit, the digital power supply filtering circuit, and the Serdes power supply filtering circuit are all connected to the PHY circuit.

[0045] More specifically, the filtering circuit is as Figure 6-1 , Figure 6-2 and Figure 6-3 shown, where Figure 6-1 is the analog power supply filtering circuit, Figure 6-2 is the digital power supply filtering circuit, Figure 6-3 is the Serdes power supply filtering circuit.

[0046] The analog power supply filtering circuit includes inductors L1, L2, LP1, FB1, capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C22, C23, C25, C26, C28, C29, C30, C31, C32, C33. One end of inductor LP1 is connected to one end of capacitor C1 and the AVDDHS power supply respectively. The other end of capacitor C1 is grounded. Capacitor C2 is in parallel with capacitor C1. The other end of inductor LP1 is connected to one end of capacitor C3. The other end of capacitor C3 is grounded. Capacitors C4, C5, C6, C7, C8, C9, C10, C11 are all in parallel with capacitor C3. The other end of inductor LP1 outputs the AVDDH_PHY0 power supply signal. One end of inductor L1 is connected to one end of capacitor C12 and the AVDDLS power supply respectively. The other end of capacitor C12 is grounded. Capacitor C13 is in parallel with capacitor C12. The other end of inductor L1 is connected to one end of capacitor C14. The other end of capacitor C14 is grounded. Capacitors C15, 16, C17, C18, C19, C20 are all in parallel with capacitor C14. The other end of inductor L1 outputs the AVDDL_PHY0 power supply signal. One end of inductor FB1 is connected to one end of capacitor C25 and the AVDDHS power supply respectively. The other end of capacitor C25 is grounded. Capacitor C26 is in parallel with capacitor C25. The other end of inductor FB1 is connected to one end of capacitor C28. The other end of capacitor C28 is grounded. Capacitors C22, 23 are all in parallel with capacitor C28. The other end of inductor FB1 outputs the AVDDH_PLL0 power supply signal. One end of inductor L2 is connected to one end of capacitor C29 and the AVDDLS power supply respectively. The other end of capacitor C29 is grounded. Capacitor C30 is in parallel with capacitor C29. The other end of inductor L2 is connected to one end of capacitor C31. The other end of capacitor C31 is grounded. Capacitors C32, 33 are all in parallel with capacitor C31. The other end of inductor L2 outputs the AVDDL_PLL0 power supply signal.

[0047] The digital power supply filtering circuit includes capacitor C38, capacitor C39, capacitor C40, capacitor C41, capacitor C42, capacitor C43, capacitor C44, capacitor C45, capacitor C46, capacitor C47, capacitor C48, capacitor C49, capacitor C50, capacitor C52, capacitor C53, capacitor C54, capacitor C55, capacitor C56, capacitor C57, capacitor C58, capacitor C60, capacitor C61, capacitor C62, capacitor C63, capacitor C64, capacitor C65, capacitor C66, capacitor C67, capacitor C68, capacitor C69, capacitor C71, capacitor C72, capacitor C73, capacitor C74. One end of capacitor C38 is connected to the DVDDLS power supply, and the other end of capacitor C38 is grounded. Capacitor C39, capacitor C40, and capacitor C41 are all in parallel with capacitor C38. One end of capacitor C42 is connected to the DVDDLS power supply, and the other end of capacitor C42 is grounded. Capacitor C43, capacitor C44, capacitor C45, capacitor C46, capacitor C47, capacitor C48, capacitor C49, and capacitor C50 are all in parallel with capacitor C42. One end of capacitor C52 is connected to the DVDDIO_3.3V power supply, and the other end of capacitor C52 is grounded. Capacitor C53, capacitor C54, and capacitor C55 are all in parallel with capacitor C52. One end of capacitor C56 is connected to the DVDDIO_3.3V power supply and the DVDDIOM pin of PHY chip U1 respectively, and the other end of capacitor C56 is grounded. Capacitor C57 and capacitor C58 are all in parallel with capacitor C56. One end of capacitor C60 is connected to the DVDDLS power supply, and the other end of capacitor C60 is grounded. Capacitor C71, capacitor C72, capacitor C61, capacitor C62, and capacitor C63 are all in parallel with capacitor C60. One end of capacitor C73 is connected to the DVDDIOLS power supply, and the other end of capacitor C73 is grounded. Capacitor C74, capacitor C64, capacitor C65, capacitor C66, capacitor C67, capacitor C68, and capacitor C69 are all in parallel with capacitor C73.

[0048] The Serdes power supply filtering circuit includes inductor L3, inductor L4, capacitor C79, capacitor C80, capacitor C81, capacitor C82, capacitor C83, capacitor C84, capacitor C85, capacitor C86. One end of inductor L3 is connected to the DVDDLS power supply and one end of capacitor C79 respectively, the other end of capacitor C79 is grounded, the other end of inductor L3 is connected to one end of capacitor C80, the other end of capacitor C80 is grounded, capacitor C81 and capacitor C82 are both in parallel with capacitor C80, the other end of inductor L3 outputs the SVDD0_TRX power supply signal. One end of inductor L4 is connected to the DVDDLS power supply and one end of capacitor C83 respectively, the other end of capacitor C83 is grounded, the other end of inductor L4 is connected to one end of capacitor C84, the other end of capacitor C84 is grounded, capacitor C85 and capacitor C86 are both in parallel with capacitor C84, and the other end of inductor L4 outputs the SVDD0_CK power supply signal.

[0049] Further, the crystal oscillator unit is implemented through a crystal oscillator circuit, which includes a crystal oscillator Y1. The first output terminal (OUT1 pin) and the second output terminal (OUT2 pin) of the crystal oscillator Y1 are connected to the PHY circuit, and the grounding terminal of the crystal oscillator Y1 is grounded.

[0050] More specifically, the crystal oscillator circuit is as Figure 7 shown. The crystal oscillator circuit includes a crystal oscillator Y1, a capacitor C24, and a capacitor C27. The model of the crystal oscillator Y1 is TXC_7M_50MHz. The OUT1 pin of the crystal oscillator Y1 is respectively connected to the XTAL_N pin of the PHY chip and one end of the capacitor C24, and the other end of the capacitor C24 is grounded. The GND1 pin and the GND2 pin of the crystal oscillator Y1 are both grounded. The OUT2 pin of the crystal oscillator Y1 is respectively connected to the XTAL_P pin of the PHY chip and one end of the capacitor C27, and the other end of the capacitor C27 is grounded.

[0051] As an implementation manner, the PHY circuit, the MCU circuit, the network transformer circuit, the power supply circuit, the filtering circuit, and the crystal oscillator circuit are all arranged on the PCB board.

[0052] The present utility model also provides a component, as Figure 1 shown, which includes the above-mentioned 10G optical-to-electrical conversion module and also includes a network card. There are two of the above-mentioned 10G optical-to-electrical conversion modules, namely a first optical-to-electrical conversion module and a second optical-to-electrical conversion module. The first optical-to-electrical conversion module and the second optical-to-electrical conversion module are connected by a network cable, and the first optical-to-electrical conversion module and the network card are connected by a gold finger.

[0053] The PHY chip is RTL8261BE, and its own SI and SO interfaces perform service communication with the PHY interface in the network card through the gold finger.

[0054] Among them, the network card, as a communication component one level higher than the electrical module, distributes and returns service signals to the electrical module, and at the same time supplies power to the electrical module slot (optical port), etc.

[0055] Among them, the 10G electrical module (the first optical-to-electrical conversion module) performs electrical signal communication with the network card through the gold finger of the module, and at the same time performs signal transmission and reception with another 10G electrical module (the second optical-to-electrical conversion module) through the network port RJ45 and the network cable.

[0056] As an implementation manner, the network cable selects a Category 6 network cable as the transmission medium for electrical signals, and the length is between 0 and 30 meters.

[0057] As Figure 9 shown, by using the existing network cable (30 meters) and a 10G network card / switch, the 10G electrical module is chained into the transmission network. After testing, the reception and transmission of channels 1 and 2 in cross-interconnection are equal, and the packet loss rate is 0%, realizing the transmission of 10G Ethernet.

[0058] In an all-electric signal environment, the present utility model innovatively uses a PHY chip to achieve the transmission and reception of electric signals, and at the same time utilizes the optical port of a network card / switch for service transmission.

[0059] A 10 Gigabit optical-to-electric module of the present utility model and a component applying the same develop an all-electric optical module corresponding to short-distance communication requirements, and a transceiver module that uses a network cable and the existing optical port of a switch to transmit service signals. The service rate can reach 10 Gbps, achieving the communication purpose while saving costs, reducing labor, decreasing waste, and protecting the environment.

[0060] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0061] It is not difficult for those skilled in the art to understand that the present utility model includes any combination of the above-mentioned utility model content and specific implementation part of the specification and each part shown in the drawings. Due to space limitations and to make the specification concise, the various schemes formed by these combinations are not described one by one. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

[0062] Although the embodiments of the present utility model have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present utility model. Those of ordinary skill in the art can make changes, modifications, replacements, and variations to the above embodiments within the scope of the present utility model without departing from the principle and purpose of the present utility model. The scope of the present utility model is defined by the appended claims and their equivalents.

Claims

1. A 10 Gigabit optical-to-electrical module, characterized in that, It includes a PHY unit, an MCU unit and a power supply unit. The PHY unit is connected to the MCU unit. The power supply unit is connected to the PHY unit and the MCU unit through a filtering unit. The PHY unit is respectively connected to a crystal oscillator unit and a network transformer unit.

2. The ten-gigabit optical-to-electrical conversion module according to claim 1, wherein The PHY unit is implemented through a PHY circuit. The PHY circuit includes a PHY chip. The transceiver interface pins of the PHY chip are connected to the network transformer unit. The clock pins of the PHY chip are connected to the crystal oscillator unit. The power pins of the PHY chip are connected to the power supply unit and the filtering unit. The ground pins of the PHY chip are grounded.

3. The 10 Gigabit optical-to-electrical module according to claim 2, characterized in that The MCU unit is implemented through an MCU circuit. The MCU circuit includes an MCU chip. The first pin of the MCU chip is connected to the interrupt pin of the PHY chip. The second pin of the MCU chip is connected to the enable pin of the PHY chip. The third pin of the MCU chip is connected to the reset pin of the PHY chip. The fourth pin of the MCU chip is connected to the management interface pin of the PHY chip. The fifth pin of the MCU chip is connected to the network transformer unit. The power pins of the MCU chip are connected to the power supply unit and the filtering unit. The ground pins of the MCU chip are grounded.

4. The 10 Gigabit optical-to-electrical conversion module according to claim 2, characterized in that, The network transformer unit is implemented through a network transformer circuit. The network transformer circuit includes an RJ45 connector and a network transformer. The output end of the network transformer is connected to the RJ45 connector. The input end of the network transformer is connected to the transceiver interface pins of the PHY chip.

5. A 10G optical-to-electrical conversion module according to any one of claims 2-4, characterized in that The power supply unit is implemented through a power supply circuit. The power supply circuit includes a field effect transistor, a first voltage converter and a second voltage converter. The power supply circuit respectively provides 3.3V, 1.9V and 1.0V voltage sources.

6. The ten-gigabit optical-to-electrical conversion module according to claim 5, wherein The filtering unit is implemented through a filtering circuit. The filtering circuit includes an analog power supply filtering circuit, a digital power supply filtering circuit and a Serdes power supply filtering circuit. The input ends of the analog power supply filtering circuit, the digital power supply filtering circuit and the Serdes power supply filtering circuit are all connected to the power supply circuit. The output ends of the analog power supply filtering circuit, the digital power supply filtering circuit and the Serdes power supply filtering circuit are all connected to the PHY circuit.

7. The ten-gigabit optical-to-electrical conversion module according to claim 2, characterized in that, The crystal oscillator unit is implemented through a crystal oscillator circuit. The crystal oscillator circuit includes a crystal oscillator Y1. The first output end and the second output end of the crystal oscillator Y1 are connected to the PHY circuit. The ground end of the crystal oscillator Y1 is grounded.

8. A component, comprising a 10G optical-to-electrical conversion module according to any one of claims 1-7, characterized in that, It further includes a network card. There are two such 10G optical-to-electrical conversion modules, namely a first optical-to-electrical conversion module and a second optical-to-electrical conversion module. The first optical-to-electrical conversion module and the second optical-to-electrical conversion module are connected through a network cable. The first optical-to-electrical conversion module and the network card are connected through a gold finger.

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