Main control system for energy storage battery management

Abstract

The utility model provides a master control system for energy storage battery management. The master control system comprises a main processor, and a high-voltage detection circuit, a driving control circuit and an input detection circuit which are electrically connected with the main processor. The high-voltage detection circuit comprises a total voltage detection circuit and an insulation detection circuit, and the insulation detection circuit adopts an unbalanced bridge method and can detect insulation resistance; the total voltage detection circuit divides the input total voltage through a resistor and then converts the total voltage through a digital-to-analog converter, and the main processor and the digital-to-analog converter perform information interaction through an isolation chip to obtain a conversion value; the driving control circuit comprises a high-side driving chip, a channel is selected based on an IS pin of the high-side driving chip, current is output, and the main processor monitors the state of the monitoring equipment in real time by detecting the voltage of the IS pin; and the input detection circuit comprises multiple paths of digital and analog input detection circuits and is used for performing dual detection and proofreading on detection data. The system is rich in function and high in adaptability, and can be used for energy storage systems under various use conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of energy storage batteries, and particularly to a main control system for energy storage battery management. Technical Background

[0002] With the development of the energy storage field, lithium-ion battery systems are widely used in the energy storage field, and among them, lithium-ion liquid-cooled battery packs have gradually become the mainstream products in the market. The lithium-ion liquid-cooled battery packs in the energy storage field require the main control board of the corresponding battery management system to have high-precision detection data, high product reliability, long life, and low cost. There is a lack of a main control system with high compatibility, high reliability, and high sampling accuracy suitable for commercial applications in the prior art. Summary of the Invention

[0003] In view of the above problems, the present invention provides a main control system for energy storage battery management, which has rich functions and high adaptability, can meet the requirements of high compatibility, high reliability, and high sampling accuracy of the main control board product, and can be used in energy storage systems under various operating conditions.

[0004] A main control system for energy storage battery management includes a main processor and a high-voltage detection circuit, a drive control circuit, and an input detection circuit electrically connected thereto. The high-voltage detection circuit includes a total voltage detection circuit and an insulation detection circuit. The insulation detection circuit adopts an unbalanced bridge method and can detect the insulation resistance. The total voltage detection circuit divides the input total voltage through resistors and then converts it through an analog-to-digital converter. The main processor and the analog-to-digital converter perform information interaction through an isolation chip to obtain the conversion value. The drive control circuit includes a high-side drive chip, selects a channel based on the IS pin of the high-side drive chip and outputs current, and the main processor monitors the working state of the monitoring device in real time by detecting the voltage of the IS pin. The input detection circuit includes a multi-channel digital input detection circuit and an analog input detection circuit, and double-checks and proofreads the detection data.

[0005] Preferably, in the insulation detection circuit, the upper and lower bridge arms of the unbalanced bridge and three sampling points in the bridge arm are connected to a control switch, the control switch is connected to the chassis, fixed-value resistors are connected between the chassis and the positive and negative terminals of the battery pack, and the main processor obtains the insulation resistance value by comparing the sampling values before and after the control switch.

[0006] Preferably, in the total voltage detection circuit, the acceptable voltage value after voltage division is connected to an inductive bead and a common-mode inductor for noise reduction and filtering, and then is connected to an analog-to-digital converter for analog-to-digital conversion.

[0007] Preferably, in the drive control circuit, the configuration logic for the IS pin selection channel is as follows: first, second, and third selection switches are respectively set between the IS pin and the DEN pin, DSEL1 pin, and DSEL0 pin. When DEN = 1, the first selection switch is set to a channel; when DSEL1 = 0, the second selection switch is set to a channel; when DSEL0 = 0, the third selection switch is set to a channel. One channel of the third selection switch is connected to channel 0, and the second channel of the third selection switch is connected to channel 1. When the first channels of the first, second, and third selection switches are connected, that is, when DEN = 1, DSEL1 = 0, and DSEL0 = 0 are satisfied simultaneously, the IS pin is connected to channel 0, and I is output. IS0 When the first channels of the first and second selection switches and the second channel of the third selection switch are connected, that is, when DEN = 1, DSEL1 = 0, and DSEL0 = 1, the IS pin is connected to channel 1, and I is output. IS1 A fourth selection switch is set between the second channel of the second selection switch, DSEL0, and the DSEL1 pin. When DSEL0 = 0, the fourth selection switch is set to a channel, and the first channel is connected to channel 2. When DSEL0 = 1, the fourth selection switch is set to a second channel, and the second channel is connected to channel 3. That is, when DEN = 1, DSEL1 = 1, and DSEL0 = 0 are satisfied simultaneously, the IS pin is connected to channel 2, and I is output. IS2 When DEN = 1, DSEL1 = 1, and DSEL0 = 1 are satisfied simultaneously, the IS pin is connected to channel 3, and I is output. IS3 .

[0008] Preferably, two FAULT switches are set. The FAULT is a double-headed normally open switch. The first FAULT switch is connected to channel 0, channel 1, and channel FAULT. The second FAULT switch is connected to channel FAULT, channel 2, and channel 3. When a fault occurs at the drive pin, the FAULT switch automatically closes.

[0009] Preferably, in the input detection circuit, a TVS is provided at the port to suppress high-voltage spike signals. A ceramic capacitor and a magnetic bead are provided at the port to form an LC filter circuit. One end of the ceramic capacitor is connected to the input DI, and the other end is grounded. One end of the magnetic bead is connected to the ceramic capacitor, and the other end is used as the output end of the LC filter circuit. In the digital input detection circuit, the output end of the LC filter circuit is connected to a resistor and a diode and then connected to a 24V power supply. The output end of the LC filter circuit is also connected to a MOS transistor to achieve level conversion. A zener diode is provided between the gate and source of the MOS transistor to stabilize the Vgs voltage of the MOS transistor. The drain of the MOS transistor is connected to the digital signal input end of the main processor. In the analog input detection circuit, the output end of the LC filter circuit is connected to a temperature-variable resistor and then connected to a 3.3V power supply. The output end of the LC filter circuit is also connected to the analog signal input end of the main processor.

[0010] Preferably, the feedback pin is detected based on the digital input detection circuit. The feedback pin is connected to the input terminal DI. When the switch is closed and shorted to GND, the measured voltage is 0V, or when the switch is closed and shorted to 24V, the working state of the feedback pin is judged by the change of the switch; the temperature is detected based on the analog input detection circuit. When the circuit is connected, the partial voltage value of the variable resistor with temperature is collected, and the corresponding temperature value can be obtained by looking up the resistance-temperature table.

[0011] Preferably, the main control system further includes a low-voltage power supply protection circuit. A varistor and a TVS are provided at the port of the protection circuit to suppress abnormal overvoltage.

[0012] Preferably, the main control system further includes a communication interface circuit, including a CAN bus circuit, an RS485 bus circuit, and an Ethernet bus circuit. The communication circuit adopts isolated communication, and the main control board communicates with the slave control through the CAN bus circuit.

[0013] Preferably, the CAN interface chip adopts the TJA1042T / 3 of NXP. The CAN interface chip exchanges information with the main processor through a dual-channel isolation chip, and several TVSs are designed at the interface for multiple protections.

[0014] Beneficial effects

[0015] Compared with the main control system of general energy storage battery management, the beneficial effects of the present invention are as follows:

[0016] (1) The main control system disclosed in the present invention is a main control integration solution for a battery management system dedicated to industrial and commercial energy storage, meeting the functional requirements of industrial and commercial energy storage systems, and meeting the requirements of high compatibility, long life, high reliability, and high sampling accuracy of the main control board products;

[0017] (2) For the complex and harsh operating conditions of the energy storage system, the main control system disclosed in the present invention enhances the protection and anti-interference capabilities of the interface circuit of the main control; multiple temperature monitoring, voltage monitoring, current monitoring, etc. are designed, and the working states of various components of the energy storage system can be monitored, such as components such as low-voltage power supplies, fuses, and relays. Dual monitoring can improve the reliability of the monitored sampling data, thereby ensuring the reliability and safety of the system;

[0018] (3) The sampling functions such as total voltage sampling, insulation sampling, and current detection in the main control system disclosed in the present invention have high accuracy. The total voltage sampling can achieve the detection accuracy of 0.5% in the full temperature range and full voltage range; the insulation detection accuracy can achieve the detection accuracy of 15%; the current detection accuracy: 0.5%;

[0019] (4) The drive control circuit of the main control system disclosed in the present invention is designed with an intelligent diagnosis function, which can monitor the working current and working state of the drive circuit in real time, and the processor can identify various drive circuit faults such as output short circuit to ground, etc. Description of the Drawings

[0020] Figure 1 is a schematic diagram of the main control architecture of an embodiment of the present invention;

[0021] Figure 2 is a CAN bus circuit diagram of an embodiment of the present invention;

[0022] Figure 3 is an insulation detection circuit diagram of an embodiment of the present invention;

[0023] Figure 4 is a total pressure detection circuit diagram of an embodiment of the present invention;

[0024] Figure 5 is a high-side drive circuit diagram of an embodiment of the present invention;

[0025] Figure 6 is an IS pin configuration diagram of an embodiment of the present invention;

[0026] Figure 7 is a low-side drive circuit diagram of an embodiment of the present invention;

[0027] Figure 8 is a dry contact drive circuit diagram of an embodiment of the present invention;

[0028] Figure 9 is a digital input detection circuit diagram of an embodiment of the present invention;

[0029] Figure 10 is an analog input detection circuit diagram of an embodiment of the present invention;

[0030] Figure 11 is a schematic diagram of the main control board PCB of an embodiment of the present invention;

[0031] Figure 12 is a low-voltage power supply protection circuit of an embodiment of the present invention. Detailed Description of the Invention

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0033] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "center", "upper", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meanings of "multiple" and "several" are two or more.

[0034] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection: it can be a mechanical connection or an electrical connection: it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0035] The present invention discloses a main control integration solution for a battery management system dedicated to industrial and commercial energy storage, which meets the functional requirements of the industrial and commercial energy storage system and the requirements of high compatibility, long life, high reliability, and high sampling accuracy of the main control board product.

[0036] As Figure 1 shown, a main control system for energy storage battery management includes a main processor and a power supply circuit, a communication interface circuit, a high-voltage detection circuit, a drive control circuit, and an input detection circuit electrically connected thereto. In this embodiment, the main processor used is ST's STM32MP157AAC3. Figure 1 The red arrow in Figure 1 represents the direction of the large current, and the black is the signal direction. The power supply circuit corresponds to the 24V to 12V module and the 12V to 5V module connected to the EN pin in Figure 1 . This port is externally connected to a power supply module to supply power to the entire circuit board. The communication interface circuit corresponds to the CAN transceiver, CAN controller, and 485 transceiver module in Figure 1 for realizing the communication and exchange between the main control board and the slave control. The high-voltage detection circuit corresponds to the total voltage detection module and the insulation detection module in Figure 1The middle drive and detection circuit module monitors the working state and drive current of the drive load in real time for energy storage systems under different working conditions. The input detection circuit corresponds to Figure 1 the analog input detection module, digital input detection module, and dry contact input detection module, which are used to detect components such as fuses, relays, circuit breakers, and low-voltage power supplies. The main control system of the present invention is comprehensively designed and can meet the functional requirements of industrial and commercial energy storage systems, as well as the requirements of high compatibility, long life, high reliability, and high sampling accuracy of the main control board products.

[0037] The communication interface circuit includes a CAN bus circuit, an RS485 bus circuit, and an Ethernet bus circuit. The communication interfaces are rich and have high adaptability. Considering its actual relatively harsh use environment, the multi-channel communication circuits use isolated communication, and the main control board and the slave control communicate through the CAN bus to ensure the reliability and stability of communication. As Figure 2 shown, the CAN interface chip used is the TJA1042T / 3 of NXP. The CAN0 signals EXT_CAN0_H, EXT_CAN0_RES, and EXT_CAN0_L of the slave control board are connected to the CAN_H and CAN_L pins of the CAN interface chip through TVS12, TVS8, TVS9, and TVS45. Based on TVS12, TVS8, TVS9, and TVS45, multiple protections are realized, effectively improving the anti-interference ability of the bus and ensuring the reliability and stability of the product. The RXD and TXD pins of the CAN interface chip are connected to a dual-channel isolation chip (ISO7721QDRQ1 of TI) to interact with the main processor. Specifically, the OUTA and INB pins of the isolation chip are connected to the MCU_CAN0_RX and MCU_CAN0_TX pins of the main control chip.

[0038] The high-voltage detection circuit includes two-way total voltage detection and one-way insulation detection circuit:

[0039] The insulation detection circuit, as Figure 3As shown, the non - balanced bridge method is adopted. It can accurately detect the insulation resistance within the equal - width input voltage range of 50 - 1600V. The sampled values are uploaded to the main processor through a four - channel isolation chip, and the main processor calculates the insulation resistance value based on the uploaded data. Specifically, the insulation detection circuit uses the non - balanced bridge method. One end of the upper bridge arm is connected to the positive pole of the battery, and one end of the lower bridge arm is connected to the negative pole of the battery. Three sampling points (DOWN_SW, MID_SW, UP_SW), namely the other ends of the upper and lower bridge arms and the control switch connected in the bridge arm, are taken. The control switch is connected to the chassis. Preferably, the control switch is an optocoupler QCPL - A58JV - 500E. By controlling the connection of a fixed - value resistor between pe (chassis) and b+ and b - (positive and negative terminals of the battery pack), the insulation resistance value can be obtained by comparing and calculating the sampled values before and after the switch. At the same time, the input voltage Volt_Meas3 is connected to the BLM18PG471 inductive bead to suppress high - frequency noise in the power - line application, reduce the possibility of resonance, provide a distortion - free signal waveform, and then filter the common - mode interference signal through a common - mode inductor to obtain Volt_Meas3+ / - . The Volt_Meas3+ / - signal is connected to the analog input port AIN pin of the analog - to - digital converter for analog - to - digital conversion, and then connected to the main processor through a four - channel isolation chip. The main processor exchanges information with the four - channel isolation chip to obtain the conversion value of the analog - to - digital converter, protecting the security of the system. Among them, the analog - to - digital converter is ADS1118IDGSR, and the four - channel isolation chip is ISO7741DWR. Its INA, INB, INC, OUTD pins are connected to the corresponding pins of the main processor to achieve isolation between high voltage and low voltage.

[0040] The total - voltage detection circuit, as Figure 4 shown, can detect a maximum total voltage of 0 - 1600V, and the detection accuracy of high - precision full - temperature and full - voltage can reach 0.5%. First, the total voltages VIN1+ and VIN2+ are subjected to resistor voltage division to obtain acceptable voltage values Volt_Meas1 and Volt_Meas2. Volt_Meas1 and Volt_Meas2 pass through inductive beads (BLM18PG471) to suppress high - frequency noise in the power - line application, reduce resonance, and filter the common - mode interference signal through a common - mode inductor to obtain Volt_Meas1+ / - and Volt_Meas2+ / - .

[0041] Volt_Meas1+ / - and Volt_Meas2+ / - are converted by an analog-to-digital converter. The analog-to-digital converter uses ADS1118IDGSR. The Volt_Meas1+ / - and Volt_Meas2+ / - pins are correspondingly connected to the analog input ports AIN of the analog-to-digital converter chip for analog-to-digital conversion, and then connected to the main processor through a four-channel isolation chip. The four-channel isolation chip selects ISO7741DWR, and its INA, INB, INC, and OUTD pins are connected to the corresponding pins of the main processor to achieve isolation between high voltage and low voltage. The main processor interacts with the four-channel isolation chip to obtain the conversion value of the analog-to-digital converter, protecting the security of the system.

[0042] The drive control circuit includes multiple high-side drives, low-side drives, and dry contact drive circuits with intelligent diagnosis. The driving capabilities of the drive circuit have multiple options and can be adapted to energy storage systems under different operating conditions. The main processor can monitor the working status of the controlled device in real time.

[0043] The high-side drive circuit, such as Figure 5 shown, U32 is a four-channel high-side drive chip (BTT6200-4EMA of Infineon). PIN24 is OUT0, PIN20 is OUT1, PIN 17 is OUT2, and PIN 13 is OUT3 corresponding to four channels. The four-channel ports are all connected to the HSD connector through TVS diodes. Among them, SMBJ36 is selected as the protection device for TVS. PIN7 is the IS pin, PIN6 is the DEN pin, and PIN8 and PIN11 are the DSEL0 and DSEL1 pins. The main processor can configure and select channels through the DEN, DSEL1, and DSEL0 pins according to Figure 6 to achieve an IS pin output current that is scaled down proportionally to the corresponding selected channel. At the same time, when a corresponding fault occurs at the drive pin, the main processor can also identify the fault through this IS pin and upload it. Specifically, a first selection switch is set between the IS pin and the DEN pin. When DEN = 1, the first selection switch is set to one channel;

[0044] A second selection switch is set between the IS pin and the DSEL1 pin. When DSEL1 = 0, the second selection switch is set to one channel;

[0045] A third selection switch is set between the IS pin and DSEL0. When DSEL0 = 0, the third selection switch is set to one channel. One channel of the third selection switch is connected to channel 0, and the second channel of the third selection switch is connected to channel 1.

[0046] One channels of the first, second, and third selection switches are connected. That is, when DEN = 1, DSEL1 = 0, and DSEL0 = 0 are all satisfied at the same time, the IS pin is connected to channel 0, and I is output IS0When one channel of the first and second selection switches and two channels of the third selection switch are connected, that is, when DEN = 1, DSEL1 = 0, and DSEL0 = 1 are satisfied simultaneously, the IS pin is connected to channel 1 and outputs I IS 。

[0047] A fourth selection switch is set between the DSEL0 and DSEL1 pins, and the fourth selection switch is connected to two channels of the second selection switch. When the fourth selection switch is set to one channel (DSEL0 = 0), it is connected to channel 2, and when it is set to two channels (DSEL0 = 1), it is connected to channel 3.

[0048] One channel of the first selection switch, two channels of the second selection switch, one channel of the fourth selection switch, and channel 2 are connected. That is, when DEN = 1, DSEL1 = 1, and DSEL0 = 0 are satisfied simultaneously, the IS pin is connected to channel 2 and outputs I IS2 。

[0049] One channel of the first selection switch, two channels of the second selection switch, two channels of the fourth selection switch, and channel 3 are connected. That is, when DEN = 1, DSEL1 = 1, and DSEL0 = 1 are satisfied simultaneously, the IS pin is connected to channel 3 and outputs I IS3 。

[0050] The FAULT switch is a normally open double-headed switch. Two FAULT switches are set. The first FAULT switch is connected to channel 0, channel 1, and channel FAULT, and the second FAULT switch is connected to channel FAULT, channel 2, and channel 3. When the driving pin encounters a corresponding fault, the FAULT automatically closes. At this time, the fault current is large enough to cover the current of any channel. That is, no matter which channel the IS pin is connected to, a large current can be recognized. At this time, by reading the current magnitude of the IS pin, the fault can be recognized.

[0051] Since the main processor collects voltage values or voltage drops, an equal-proportion resistor is set at the IS pin. By comparing the state switches during the operation process to judge the current of the IS pin, the working state of the driving load and the driving current can be monitored in real time. At the same time, the data uploaded by the IS pin is processed to obtain the working state of the corresponding driving pin, and corresponding actions such as disconnecting the drive and uploading the fault are performed to protect the safe, stable, and normal operation of the system.

[0052] Low-side drive circuit, such as Figure 7As shown, M34 is a single-channel low-side drive chip. In this embodiment, NCV8406ASTT3G of ON is adopted. PIN2 and PIN4 are output ports, and the output ports are externally connected to connectors through protection devices such as TVS diodes and ESD capacitor C212. Among them, SMBJ36 is selected as the TVS protection device. PIN1 of M34 is the control pin. The main processor controls the drive chip M34 through the RC filter circuit composed of resistor R312 and capacitor C208. The low-side output port is fed back to the main processor through the RC filter circuit composed of resistor R324 and capacitor C209. The main processor judges the working state of the drive circuit through the detection results of the front and back feedback pins of the switch. The existence of the zener diode Z28 can protect the sampling port of the main processor and prevent it from being damaged by overvoltage.

[0053] Dry contact drive circuit, such as Figure 8 As shown, HFD4 / 5-SR of HF is adopted. The main processor controls the switch of K3 through M37. Diode D57 is used to suppress the voltage across DS of M37 during freewheeling when the switching transistor M37 is turned off.

[0054] Input detection circuit, including multi-channel digital input and analog input detection circuits. Such as Figures 9 to 10As shown in the figure, the input detection circuit is respectively provided with TVS26 and TVS31 at the analog input port AI and the digital input port DI, which can effectively suppress high-voltage spike signals to protect internal devices and avoid overvoltage damage to subsequent devices. In the digital input detection circuit, the ceramic capacitor C176 and the magnetic bead FB22 form an LC filter circuit, which can filter out some high-frequency interference signals and avoid abnormal circuit operation caused by high-frequency interference signals. The LC filter circuit is connected to the MOS transistor M19 to achieve level conversion, converting the 24V level into a 3.3V level acceptable to the main processor, and also playing a certain isolation role to protect the subsequent main processor. The zener diode Z19 is connected between the gate and source of M19 to stabilize the Vgs voltage of M19 and avoid overvoltage damage to M19. The drain of M19 is connected to the digital signal input terminal of the main processor. In the analog input detection circuit, the ceramic capacitor C185 and the magnetic bead FB26 form an LC filter circuit, which can filter out some high-frequency interference signals and avoid abnormal circuit operation caused by high-frequency interference signals. The output terminal of the LC filter circuit is connected to the resistor R255 and the resistor R258. The output terminal of the resistor R258 is connected to the resistor R263 and then grounded. The capacitor C188 and the zener diode Z30 are connected in parallel across the two ends of the resistor R263. The zener diode Z30 stabilizes the voltage across the capacitor C188 to avoid overvoltage damage to the main processor; the output terminal of the resistor R258 is also connected to the analog signal input terminal of the main processor. The LC filter circuit is connected to the analog signal input terminal of the main processor. In the energy storage system, the input detection circuit is used to detect components such as fuses, relays, circuit breakers, and low-voltage power supplies, and can monitor the operating temperature of these components to judge the operating state of the components. At the same time, it can also monitor the feedback pins of some components and the output voltage of the low-voltage power supply. The feedback pin is detected through the digital input detection circuit. The feedback pin is equivalent to a digital quantity. As Figure 9 shown in the figure, the digital quantity is connected to the input terminal DI6. When the switch is closed and shorted to GND, the measured voltage is 0V, or when the switch is closed and shorted to 24V, the operating state of the feedback pin is judged by the change of the switch. The temperature is detected through the analog input detection circuit. As Figure 10 shown in the figure, the input section AI1 of the LC filter circuit is connected to a variable resistor (thermistor) that changes with temperature, and then is voltage-divided with R255 through the LC filter circuit. The voltage of the voltage division is further voltage-divided by the resistor R258 and the resistor R263. The main processor can calculate the resistance value of the external thermistor by detecting the voltage value of the resistor R263, and the corresponding temperature value can be obtained by looking up the resistance-temperature table of the temperature-variable resistor. By double-monitoring and calibrating the operating temperature of the peripheral components and the feedback pins, the reliability of the detected data is increased. In case of abnormal operation of the components such as abnormal temperature, corresponding actions such as alarm can be taken in a timely manner.

[0055] As Figure 11As shown, it is the PCB of the main control board that integrates the above-mentioned circuits. On the one hand, to meet the design requirements of high-precision sampling, the relevant sampling circuits are selected according to higher precision requirements. At the same time, considering the cost, corresponding low-cost detection schemes are also reserved. Each module circuit has a margin to adapt to energy storage systems with different requirements. On the other hand, for important components of the energy storage system such as fuses, the main control board not only monitors its own temperature in real time through the analog input detection circuit, but also monitors its feedback pins through the digital input detection circuit. At the same time, its detection circuit is also designed with a corresponding LC filter circuit to filter out interference. The main processor judges the working state of the component based on the sampled data, and then performs corresponding operations according to the detection results to ensure the safe and reliable operation of the component. At the same time, dual monitoring can improve the reliability of the monitored sampling data, thus ensuring the reliability and safety of the system.

[0056] Considering the operating conditions of the energy storage system, corresponding protective devices such as TVS are added to each external pin, such as Figure 12 The protection circuit of the power supply circuit shown is connected with a fuse JFC2410 at the port

[0057] 2100, and a varistor R4 and a TVS1 are provided at the port for protection to suppress abnormal overvoltage in the circuit and avoid damage to the subsequent components due to overvoltage, resulting in abnormal circuit operation. At the same time, the combined use of the varistor R4 and the TVS1 can improve the protection ability of the protection circuit. A Schottky diode SS15U60PQ is also provided to prevent reverse connection and play a protection role. At the same time, a corresponding differential and common-mode filter circuit is also designed at the power supply port, such as Figure 12 The L1, L4 and the corresponding filter capacitors C73, C74, C114, etc. shown form a filter, which can filter out the corresponding high-frequency interference. EXT is externally connected to a 24V voltage, and 24V-OUT is output to supply power to the drive circuit, 24V-BAT is output for network power supply, 24V-DI is output for digital circuit power supply, and 24V is output for subsequent conversion to 5V and 3.3V to supply power to the internal logic chips.

[0058] This application designs a main control integration solution for a battery management system dedicated to industrial and commercial energy storage, meeting the functional requirements of industrial and commercial energy storage systems. In view of the actual situations such as the complex use environment and strong interference of energy storage, each interface of the main control board has corresponding protection, and at the same time, multiple protections are designed for some interfaces to ensure the reliability of the product and strong anti-interference ability; at the same time, dual monitoring is designed for each main component of the energy storage system to ensure the stable and safe operation of the system, and the corresponding drive circuits are all designed with intelligent diagnosis work. At the same time, this system can achieve high-precision and low-error sampling of higher total battery pack voltage, charge and discharge current, and insulation resistance, and is stable and reliable; the main control board needs to be able to collect single-cell voltages of 0-1600V, with an accuracy of 0.5% (within the full voltage range). The temperature range is -40°C to 125°C, with an accuracy of 1°C and an error of 1°C. The current sampling accuracy is 0.5%. The insulation detection accuracy is 15%, meeting the requirements of high compatibility, long life, high reliability, and high sampling accuracy of the main control board product.

[0059] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A master control system for energy storage battery management, characterized in that, It includes a main processor, a high-voltage detection circuit, a drive control circuit, and an input detection circuit that are electrically connected thereto. The high-voltage detection circuit includes a total voltage detection circuit and an insulation detection circuit. The insulation detection circuit adopts the unbalanced bridge method and can detect the insulation resistance. The total voltage detection circuit divides the input total voltage through resistors and then converts it through an analog-to-digital converter. The main processor and the analog-to-digital converter exchange information through an isolation chip to obtain the conversion value. The drive control circuit includes a high-side drive chip, selects a channel based on the IS pin of the high-side drive chip and outputs current. The main processor monitors the working state of the monitoring device in real time by detecting the voltage of the IS pin. The input detection circuit includes a multi-channel digital input detection circuit and an analog input detection circuit, which perform double detection and verification on the detection data.

2. The master control system according to claim 1, wherein In the insulation detection circuit, the upper and lower bridge arms of the unbalanced bridge and three sampling points in the bridge arm are connected to a control switch. The control switch is connected to the chassis, and fixed-value resistors are connected between the chassis and the positive and negative terminals of the battery pack. The main processor obtains the insulation resistance value by comparing the sampling values before and after the control switch.

3. The master control system according to claim 1, characterized in that, In the total voltage detection circuit, the acceptable voltage value after voltage division is connected to an inductive bead and a common-mode inductor for noise reduction and filtering, and then connected to an analog-to-digital converter for analog-to-digital conversion.

4. The master control system according to any one of claims 1-3, characterized in that, In the drive control circuit, the high-side drive chip adopts BTT6200-4EMA, PIN7 is the IS pin, and PIN6 is DEN The pins, PIN8 and PIN11 are DSEL0 and DSEL1 pins respectively. The configuration logic for the IS pin to select channels is as follows: First, second, and third selection switches are respectively set between the IS pin and the DEN pin, DSEL1 pin, and DSEL0 pin. When DEN = 1, the first selection switch is set to a channel. When DSEL1 = 0, the second selection switch is set to a channel. When DSEL0 = 0, the third selection switch is set to a channel. One channel of the third selection switch is connected to channel 0, and the other channel of the third selection switch is connected to channel 1. When the channels of the first, second, and third selection switches are connected, that is, when DEN = 1, DSEL1 = 0, and DSEL0 = 0 are satisfied simultaneously, the IS pin is connected to channel 0 and outputs I IS0 ; When the channels of the first and second selection switches and the other channel of the third selection switch are connected, that is, when DEN = 1, DSEL1 = 0, and DSEL0 = 1, the IS pin is connected to channel 1 and outputs I IS1 ; A fourth selection switch is set between the second channel of the second selection switch and the DSEL0 and DSEL1 pins. When DSEL0 = 0, the fourth selection switch is set to the first channel, and the first channel is connected to channel 2. When DSEL0 = 1, the fourth selection switch is set to the second channel, and the second channel is connected to channel 3. That is, when DEN = 1, DSEL1 = 1, and DSEL0 = 0 are satisfied simultaneously, the IS pin is connected to channel 2, and I is output IS2 , simultaneously satisfying When DEN = 1, DSEL1 = 1, and DSEL0 = 1, the IS pin is connected to channel 3 and outputs I IS3 .

5. The master control system according to claim 4, characterized in that Two FAULT switches are set. FAULT is a double-headed normally open switch. The first FAULT switch is connected to channel 0, channel 1, and channel FAULT, and the second FAULT switch is connected to channel FAULT, channel 2, and channel 3. When a fault occurs at the drive foot, the FAULT switch automatically closes.

6. The master control system according to claim 1, characterized in that In the input detection circuit, a TVS is provided at the port to suppress high-voltage spike signals. A ceramic capacitor and an inductive bead are provided at the port to form an LC filter circuit. One end of the ceramic capacitor is connected to the input DI, and the other end is grounded. One end of the inductive bead is connected to the ceramic capacitor, and the other end is used as the output end of the LC filter circuit. In the digital input detection circuit, the output end of the LC filter circuit is connected to a resistor and a diode and then connected to a 24V power supply. The output end of the LC filter circuit is also connected to a MOS tube to achieve level conversion. A zener diode is provided between the gate and source of the MOS tube to stabilize the Vgs voltage of the MOS tube. The drain of the MOS tube is connected to the digital signal input end of the main processor. In the analog input detection circuit, the output end of the LC filter circuit is connected to resistor R255 and resistor R258, and the output end of resistor R258 is connected to resistor R263 and the analog signal input end of the main processor.

7. The master control system according to claim 1, wherein Detect the feedback pin based on the digital input detection circuit, connect the feedback pin to the input terminal DI, close the switch to short-circuit to GND, measure the voltage of 0V, or close the switch to short-circuit to 24V, and judge the working state of the feedback pin through the change of the switch; detect the temperature based on the analog input detection circuit, connect a variable resistor that changes with temperature at the input terminal of the LC filter circuit, collect the divided voltage value of the variable resistor that changes with temperature, and the corresponding temperature value can be obtained by looking up the resistance-temperature table.

8. The master control system according to claim 1, characterized in that, The main control system further includes a low-voltage power supply protection circuit, and a varistor and a TVS are provided at the protection circuit port to suppress abnormal overvoltage.

9. The master control system according to claim 1, wherein The main control system further includes a communication interface circuit, including a CAN bus circuit, an RS485 bus circuit, and an Ethernet bus circuit. The communication circuit uses isolated communication, and the main control board communicates with the slave control through the CAN bus circuit.

10. The master control system according to claim 9, wherein The CAN interface chip uses NXP's TJA1042T / 3. The CAN interface chip exchanges information with the main processor through a dual-channel isolation chip, and several TVSs are designed at the interface for multiple protections.

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