Hardware overvoltage protection threshold PWM adjusting circuit

Abstract

The utility model discloses a hardware overvoltage protection threshold PWM adjusting circuit, which comprises a comparator U18D, a diode D27, a comparator U18C and an NPN tube Q29, the anti-phase end of the comparator U18D is used for accessing an adjusting signal DSPPWM, the in-phase end of the comparator U18D is used for accessing a reference voltage, the anode of the diode D27 is connected with the anti-phase end of the comparator U18D, the cathode of the diode D27 is connected with the anode of the comparator U18D, and the anode of the diode D27 is connected with the cathode of the comparator U18C. The negative electrode of the diode D27 is connected to the output end of the comparator U18D, the anti-phase end of the comparator U18D is connected with the in-phase end of the comparator U18C, the anti-phase end of the comparator U18C is used for accessing a bus sampling voltage signal AD-DC-BUSA, the output end signal of the comparator U18C is transmitted to the base electrode of the NPN tube Q29, the emitting electrode of the NPN tube Q29 is grounded, and the negative electrode of the NPN tube Q29 is grounded. The collector electrode of the NPN tube Q29 is connected to a power supply end through a resistor R197, and the collector electrode of the NPN tube Q29 is also used for outputting a bus voltage characterization signal. Hardware parameters do not need to be changed, threshold adjustment is easy to achieve, and the amplitude limiting function is achieved.

Description

Technical Field

[0001] The utility model relates to an overvoltage protection circuit, in particular to a hardware overvoltage protection threshold PWM adjustment circuit. Background Art

[0002] At present, there are a wide variety of common motor controllers. In actual applications, these motor controllers are required to match different voltage platforms. To achieve the purpose of overvoltage protection, overvoltage protection measures need to be set in the matching circuit. In the prior art, the overvoltage protection threshold in the overvoltage protection circuit is generally achieved by manually changing the component parameters on the PCB board. For example, manually adjusting a potentiometer. This adjustment method is prone to problems such as missed modification, resulting in situations such as mismatch in on-site applications and the need to return to the factory for correction, and cannot meet the application requirements of flexible adjustment. Summary of the Utility Model

[0003] The technical problem to be solved by the utility model is to provide a hardware overvoltage protection threshold PWM adjustment circuit that does not require changing hardware parameters, is easy to adjust the threshold, and has an amplitude limiting function, aiming at the deficiencies of the prior art.

[0004] To solve the above technical problem, the utility model adopts the following technical solutions.

[0005] A hardware overvoltage protection threshold PWM adjustment circuit includes a comparator U18D, a diode D27, a comparator U18C, and an NPN transistor Q29. The inverting terminal of the comparator U18D is used to access the adjustment signal DSP_PWM, the non-inverting terminal of the comparator U18D is used to access a reference voltage, the anode of the diode D27 is connected to the inverting terminal of the comparator U18D, the cathode of the diode D27 is connected to the output terminal of the comparator U18D, the inverting terminal of the comparator U18D is connected to the non-inverting terminal of the comparator U18C, the inverting terminal of the comparator U18C is used to access the bus sampling voltage signal AD-DC-BUSA, the output signal of the comparator U18C is transmitted to the base of the NPN transistor Q29, the emitter of the NPN transistor Q29 is grounded, the collector of the NPN transistor Q29 is connected to the power supply terminal through a resistor R197, and the collector of the NPN transistor Q29 is also used to output a bus voltage characterization signal.

[0006] Preferably, the adjustment signal DSP_PWM is transmitted to the inverting terminal of the comparator U18D through a three-stage RC filter circuit.

[0007] Preferably, the three-stage RC filter circuit includes a resistor R173, a capacitor C87, a resistor R174, a capacitor C94, a resistor R175, and a capacitor C215. The resistor R173, the resistor R174, the resistor R175, and the inverting terminal of the comparator U18D are connected in series in sequence. The connection point between the resistor R173 and the resistor R174 is grounded through the capacitor C87. The connection point between the resistor R174 and the resistor R175 is grounded through the capacitor C94. The connection point between the resistor R175 and the inverting terminal of the comparator U18D is grounded through the capacitor C215.

[0008] Preferably, it includes a resistor R177 and a resistor R186. The resistor R177 and the resistor R186 are connected in series in sequence and then connected between the power supply terminal and the ground. The connection point between the resistor R177 and the resistor R186 is connected to the non-inverting terminal of the comparator U18D.

[0009] Preferably, the bus sampling voltage signal AD-DC-BUSA is transmitted to the inverting terminal of the comparator U18C through a resistor R188. The connection point between the resistor R188 and the inverting terminal of the comparator U18C is grounded through a capacitor C236.

[0010] Preferably, the output terminal of the comparator U18C is connected to the base of the NPN transistor Q29 through a resistor R192.

[0011] Preferably, the base of the NPN transistor Q29 is grounded through a resistor R193.

[0012] The PWM adjustment circuit for the hardware overvoltage protection threshold disclosed by the present utility model, during its operation, the DSP_PWM port of the control board outputs a PWM wave with an amplitude of 3.3V and a duty cycle of 0 - 100%, as the adjustment signal DSP_PWM. This adjustment signal DSP_PWM is filtered and then output to the inverting terminal of the comparator U18D. By setting the duty cycle of the adjustment signal DSP_PWM, the REF_VDC node has an analog level of 0 - 3.3V. At the same time, the comparator U18D and the diode D27 form an amplitude limiting circuit, that is, when the amplitude of the adjustment signal DSP_PWM exceeds the reference voltage value at the non-inverting terminal of the comparator U18D, the diode D27 conducts and pulls down the adjustment signal DSP_PWM. When the amplitude of the adjustment signal DSP_PWM does not exceed the set reference voltage value, the voltage of the REF_VDC node is loaded onto the non-inverting terminal of the comparator U18C. The bus sampling voltage signal AD-DC-BUSA is the voltage value obtained by sampling the bus voltage and then scaled down in the ratio of 1200:2.7. The comparator U18C is used to compare with the voltage of the REF_VDC node. When the voltage of the REF_VDC node > the bus sampling voltage signal AD-DC-BUSA, it indicates that the bus voltage is normal. When the voltage of the REF_VDC node < the bus sampling voltage signal AD-DC-BUSA, it indicates that the bus voltage is overvoltage. A corresponding bus voltage characterization signal is output through the collector of the NPN transistor Q29 for further processing by the controller. Compared with the prior art, the present utility model only needs to set the amplitude of the adjustment signal DSP_PWM to achieve the adjustment of the overvoltage protection threshold, without changing the hardware parameters, so it is easy to achieve on-site threshold adjustment. At the same time, the present utility model has an amplitude limiting function for the adjustment signal DSP_PWM, thereby limiting the overvoltage protection threshold within a reasonable range. Brief Description of the Drawings

[0013] Figure 1 It is the schematic diagram of the PWM adjustment circuit for the hardware overvoltage protection threshold of the present utility model. Detailed Embodiment

[0014] The present utility model will be described in more detail below in conjunction with the drawings and embodiments.

[0015] The present utility model discloses a PWM adjustment circuit for the hardware overvoltage protection threshold. Please refer to Figure 1, which includes a comparator U18D, a diode D27, a comparator U18C, and an NPN transistor Q29. The inverting terminal of the comparator U18D is used to access the adjustment signal DSP_PWM, the non-inverting terminal of the comparator U18D is used to access the reference voltage, the anode of the diode D27 is connected to the inverting terminal of the comparator U18D, the cathode of the diode D27 is connected to the output terminal of the comparator U18D, the inverting terminal of the comparator U18D is connected to the non-inverting terminal of the comparator U18C, the inverting terminal of the comparator U18C is used to access the bus sampling voltage signal AD-DC-BUSA, the output signal of the comparator U18C is transmitted to the base of the NPN transistor Q29, the emitter of the NPN transistor Q29 is grounded, the collector of the NPN transistor Q29 is connected to the power supply terminal through a resistor R197, and the collector of the NPN transistor Q29 is also used to output a bus voltage characterization signal.

[0016] During the operation of the above circuit, the DSP_PWM port of the control board outputs a PWM wave with an amplitude of 3.3V and a duty cycle of 0-100% as the adjustment signal DSP_PWM. This adjustment signal DSP_PWM is filtered and then output to the inverting terminal of the comparator U18D. By setting the duty cycle of the adjustment signal DSP_PWM, the REF_VDC node is set to an analog level of 0-3.3V. At the same time, the comparator U18D and the diode D27 form an amplitude limiting circuit. That is, when the amplitude of the adjustment signal DSP_PWM exceeds the reference voltage value at the non-inverting terminal of the comparator U18D, the diode D27 conducts and pulls down the adjustment signal DSP_PWM. When the amplitude of the adjustment signal DSP_PWM does not exceed the set reference voltage value, the voltage of the REF_VDC node is loaded onto the non-inverting terminal of the comparator U18C. The bus sampling voltage signal AD-DC-BUSA is the voltage value obtained by sampling the bus voltage and then scaled down in a ratio of 1200:2.7. The comparator U18C is used to compare the voltage of the REF_VDC node with the bus sampling voltage signal AD-DC-BUSA. When the voltage of the REF_VDC node > the bus sampling voltage signal AD-DC-BUSA, it indicates that the bus voltage is normal. When the voltage of the REF_VDC node < the bus sampling voltage signal AD-DC-BUSA, it indicates that the bus voltage is overvoltage. The corresponding bus voltage characterization signal is output through the collector of the NPN transistor Q29 for further processing by the controller. Compared with the prior art, the present invention only needs to set the amplitude of the adjustment signal DSP_PWM to achieve the adjustment of the overvoltage protection threshold without changing the hardware parameters, so it is easy to achieve on-site threshold adjustment. At the same time, the present invention has an amplitude limiting function for the adjustment signal DSP_PWM, thus limiting the overvoltage protection threshold within a reasonable range.

[0017] In order to filter out the clutter interference of the adjustment signal DSP_PWM, in this embodiment, the adjustment signal DSP_PWM is transmitted to the inverting terminal of the comparator U18D through a three-stage RC filter circuit.

[0018] Specifically, please refer to Figure 1 , the three-stage RC filter circuit includes a resistor R173, a capacitor C87, a resistor R174, a capacitor C94, a resistor R175, and a capacitor C215. The resistor R173, the resistor R174, the resistor R175, and the inverting terminal of the comparator U18D are connected in series in sequence. The connection point between the resistor R173 and the resistor R174 is grounded through the capacitor C87. The connection point between the resistor R174 and the resistor R175 is grounded through the capacitor C94. The connection point between the resistor R175 and the inverting terminal of the comparator U18D is grounded through the capacitor C215.

[0019] As a preferred method, this embodiment includes a resistor R177 and a resistor R186. The resistor R177 and the resistor R186 are connected in series in sequence and then connected between the power supply terminal and the ground. The connection point between the resistor R177 and the resistor R186 is connected to the non-inverting terminal of the comparator U18D. Among them, the resistor R177 and the resistor R186 play a role of series voltage division. The voltage at the middle node after the two divide the voltage is used as a reference voltage and is loaded on the non-inverting terminal of the comparator U18D. On this basis, a capacitor C235 is connected in parallel with the resistor R186, and this capacitor C235 is used to filter the reference voltage.

[0020] Please refer to Figure 1 , in this embodiment, the bus sampling voltage signal AD-DC-BUSA is transmitted to the inverting terminal of the comparator U18C through a resistor R188. The connection point between the resistor R188 and the inverting terminal of the comparator U18C is grounded through a capacitor C236. Among them, the bus sampling voltage signal AD-DC-BUSA is a voltage value obtained by reducing the bus voltage in a ratio of 1200:2.7. The resistor R188 is used to limit the current of the bus sampling voltage signal AD-DC-BUSA.

[0021] In order to limit the current of the base signal of the NPN transistor Q29, in this embodiment, the output terminal of the comparator U18C is connected to the base of the NPN transistor Q29 through a resistor R192. Further, the base of the NPN transistor Q29 is grounded through a resistor R193.

[0022] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent replacements, or improvements made within the technical scope of the present utility model shall be included within the scope protected by the present utility model.

Claims

1. A hardware overvoltage protection threshold PWM regulation circuit, characterized in that, It includes comparator U18D, diode D27, comparator U18C and NPN transistor Q29. The inverting terminal of comparator U18D is used to access the regulation signal DSP_PWM, the non-inverting terminal of comparator U18D is used to access the reference voltage, the anode of diode D27 is connected to the inverting terminal of comparator U18D, the cathode of diode D27 is connected to the output terminal of comparator U18D, the inverting terminal of comparator U18D is connected to the non-inverting terminal of comparator U18C, the inverting terminal of comparator U18C is used to access the bus sampling voltage signal AD-DC-BUSA, the output signal of comparator U18C is transmitted to the base of NPN transistor Q29, the emitter of NPN transistor Q29 is grounded, the collector of NPN transistor Q29 is connected to the power supply terminal through resistor R197, and the collector of NPN transistor Q29 is also used to output the bus voltage characterization signal.

2. The hardware overvoltage protection threshold PWM adjustment circuit according to claim 1, wherein The regulation signal DSP_PWM is transmitted to the inverting terminal of comparator U18D through a three-stage RC filter circuit.

3. The hardware overvoltage protection threshold PWM regulation circuit according to claim 2, wherein The three-stage RC filter circuit includes resistor R173, capacitor C87, resistor R174, capacitor C94, resistor R175 and capacitor C215. Resistor R173, resistor R174, resistor R175 and the inverting terminal of comparator U18D are connected in series in sequence. The connection point between resistor R173 and resistor R174 is grounded through capacitor C87. The connection point between resistor R174 and resistor R175 is grounded through capacitor C94. The connection point between resistor R175 and the inverting terminal of comparator U18D is grounded through capacitor C215.

4. The hardware overvoltage protection threshold PWM regulation circuit according to claim 1, wherein It includes resistor R177 and resistor R186. Resistor R177 and resistor R186 are connected in series in sequence between the power supply terminal and the ground, and the connection point between resistor R177 and resistor R186 is connected to the non-inverting terminal of comparator U18D.

5. The hardware overvoltage protection threshold PWM regulation circuit according to claim 1, wherein The bus sampling voltage signal AD-DC-BUSA is transmitted to the inverting terminal of comparator U18C through resistor R188, and the connection point between resistor R188 and the inverting terminal of comparator U18C is grounded through capacitor C236.

6. The hardware over-voltage protection threshold PWM adjustment circuit according to claim 1, characterized in that A resistor R192 is connected between the output terminal of comparator U18C and the base of NPN transistor Q29.

7. The hardware overvoltage protection threshold PWM adjustment circuit according to claim 1, wherein The base of NPN transistor Q29 is grounded through resistor R193.

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