Power supply circuit and energy storage system

Abstract

The utility model discloses a power supply circuit and an energy storage system. The power supply circuit comprises a first auxiliary power supply, a second auxiliary power supply, a power supply output end, a first anti-backflow circuit, a second anti-backflow circuit and a switching circuit. The first auxiliary power supply is connected with the power supply output end through the first anti-backflow circuit, the second auxiliary power supply is connected with one end of the second anti-backflow circuit through the switching circuit, and the other end of the second anti-backflow circuit is connected with the power supply output end; the switching circuit is also connected with the first auxiliary power supply and the power supply output end; the switching circuit is used for turning off the second auxiliary power supply to supply power to the power output end when the first auxiliary power supply supplies power, so that the first auxiliary power supply supplies power prior to the second auxiliary power supply. According to the embodiment of the invention, the first auxiliary power supply is preferentially adopted to supply power to the battery management system under the condition that the first auxiliary power supply is normal, the energy in the second auxiliary power supply is not consumed, and meanwhile, the battery management system can maintain power supply no matter which state the first auxiliary power supply is in.

Description

Technical Field

[0001] The utility model relates to the technical field of energy storage, in particular to a power supply circuit and an energy storage system. Background Art

[0002] In an industrial and commercial energy storage system, two auxiliary power supplies are required to supply power to the BMS (Battery Management System). One of the auxiliary power supplies has an input source of AC mains power, which is converted into DC 24V through AC / DC conversion (AC / DC conversion represents the conversion from AC to DC). The input source of the other auxiliary power supply is an energy storage battery, which is converted into DC 24V through DC / DC conversion (DC / DC conversion represents the conversion from DC to DC and can convert the DC basic power supply into DC of other voltage types).

[0003] Although the ideal output of both auxiliary power supplies is 24V, in the actual power supply process, the two power supply voltages respectively corresponding to the two auxiliary power supplies will not be exactly equal. The auxiliary power supply with a slightly higher power supply voltage will pour back into the auxiliary power supply with a slightly lower power supply voltage, thus causing a failure. Therefore, in the prior art, diodes are usually used to prevent the power supplies from pouring back into each other, that is, diodes are added to the circuit corresponding to the auxiliary power supply with an input source of AC mains power, and diodes are also added to the circuit corresponding to the other auxiliary power supply with an input source of an energy storage battery.

[0004] However, in an industrial and commercial energy storage system, if the above circuit using two auxiliary power supplies to supply power to the BMS is adopted, although the circuit structure using diodes to prevent pouring back is simple, the power supply priority of each of the two auxiliary power supplies to the BMS cannot be determined, and uninterrupted power supply to the BMS cannot be ensured either. Summary of the Utility Model

[0005] Embodiments of the utility model provide a power supply circuit and an energy storage system, aiming to solve the problem that the circuit structure using diodes to prevent pouring back in the existing dual auxiliary power supplies is simple, but the power supply priority of each of the two auxiliary power supplies to the BMS cannot be determined, and uninterrupted power supply to the BMS cannot be ensured either.

[0006] In a first aspect, the utility model provides a power supply circuit, including: a first auxiliary power supply, a second auxiliary power supply, a power output terminal, a first anti-backflow circuit, a second anti-backflow circuit, and a switch circuit; the first auxiliary power supply is connected to the power output terminal through the first anti-backflow circuit, the second auxiliary power supply is connected to one end of the second anti-backflow circuit through the switch circuit, and the other end of the second anti-backflow circuit is connected to the power output terminal; the switch circuit is also connected to both the first auxiliary power supply and the power output terminal;

[0007] The switch circuit is used to turn off the power supply of the second auxiliary power supply to the power output terminal when the first auxiliary power supply is powered on and supplies power to the power output terminal, so that the first auxiliary power supply supplies power to the power output terminal prior to the second auxiliary power supply;

[0008] The first anti-backflow circuit is used to prevent current backflow between the first auxiliary power supply and the second auxiliary power supply;

[0009] The second anti-backflow circuit is used to prevent current backflow between the second auxiliary power supply and the first auxiliary power supply.

[0010] Further, the first anti-backflow circuit includes a first switch unit and a first control unit; the input end of the first switch unit is connected to the first auxiliary power supply, and the output end of the first switch unit is connected to the power output terminal; the first end of the first control unit is connected to the output end of the first switch unit, the second end of the first control unit is connected to the input end of the first switch unit, and the output end of the first control unit is connected to the control end of the first switch unit.

[0011] Further, the first anti-backflow circuit further includes a second switch unit and a second control unit; the input end of the second switch unit is connected to the control end of the first switch unit, and the output end of the second switch unit is connected to the output end of the first switch unit; the first end of the second control unit is connected to the input end of the first switch unit, the second end of the second control unit is connected to the output end of the first switch unit, and the output end of the second control unit is connected to the control end of the second switch unit.

[0012] Further, the first control unit includes a first comparison unit, the voltage acquisition terminals of the first comparison unit are respectively connected to the input end and the output end of the first switch unit to acquire a first voltage difference between the input end and the output end of the first switch unit, the output end of the first comparison unit is connected to the control end of the first switch unit, and the first comparison unit is used to compare the magnitude between the first voltage difference and a first reference voltage to control the on / off of the first switch unit.

[0013] Further, the second control unit includes a second comparison unit, the voltage acquisition terminals of the second comparison unit are respectively connected to the input end and the output end of the second switch unit to acquire a second voltage difference between the input end and the output end of the second switch unit, the output end of the second comparison unit is connected to the control end of the second switch unit, and the second comparison unit is used to compare the magnitude between the second voltage difference and a second reference voltage to control the on / off of the second switch unit.

[0014] Further, the first switching unit is a first PMOS transistor. The first comparison unit includes a first comparator and a first reference unit for providing the first reference voltage. The drain of the first PMOS transistor is connected to the first auxiliary power supply. The source of the first PMOS transistor is connected to the power output terminal. The gate of the first PMOS transistor is connected to the output terminal of the first comparator. The positive input terminal of the first comparator is connected to the source of the first PMOS transistor. The negative input terminal of the first comparator is connected to the drain of the first PMOS transistor through the first reference unit.

[0015] Further, the second switching unit is a second PMOS transistor. The second comparison unit includes a second comparator and a second reference unit for providing the second reference voltage. The drain of the second PMOS transistor is connected to the output terminal of the first comparator. The source of the second PMOS transistor is connected to the source of the first PMOS transistor. The gate of the second PMOS transistor is connected to the output terminal of the second comparator. The positive input terminal of the second comparator is connected to the drain of the first PMOS transistor. The negative input terminal of the second control unit is connected to the source of the first PMOS transistor through the second reference unit.

[0016] Further, the second anti-backflow circuit includes a third switching unit and a third control unit. The first end of the switching circuit is connected to a second auxiliary power supply. The input terminal of the third switching unit is connected to the second end of the switching circuit. The output terminal of the third switching unit is connected to the power output terminal. The first end of the third control unit is connected to the output terminal of the third switching unit. The second end of the third control unit is connected to the input terminal of the third switching unit. The output terminal of the third control unit is connected to the control terminal of the third switching unit.

[0017] Further, the second anti-backflow circuit further includes a fourth switching unit and a fourth control unit. The input terminal of the fourth switching unit is connected to the control terminal of the third switching unit. The output terminal of the fourth switching unit is connected to the output terminal of the third switching unit. The first end of the fourth control unit is connected to the input terminal of the third switching unit. The second end of the fourth control unit is connected to the output terminal of the third switching unit. The output terminal of the fourth control unit is connected to the control terminal of the fourth switching unit.

[0018] Further, the switching circuit includes a first MOS transistor and a fifth control unit. The drain of the first MOS transistor is connected to a second auxiliary power supply, and the source of the first MOS transistor is connected to the input end of the third switching unit. The first end of the fifth control unit is connected to the drain of the first MOS transistor, the second end of the fifth control unit is connected to the output end of the third switching unit, the output end of the fifth control unit is connected to the gate of the first MOS transistor, and the second end of the fifth control unit is also connected to the first auxiliary power supply.

[0019] Further, the fifth control unit includes a key switch, a first diode, a second diode, a first resistor, a second resistor, and a first driving chip. The first end of the key switch is connected to the drain of the first MOS transistor, and the second end of the key switch is connected to the positive electrode of the first diode. The negative electrode of the first diode is connected to the first end of the first resistor, and the negative electrode of the first diode is also connected to the negative electrode of the second diode. The second end of the first resistor is grounded through the second resistor, and the second end of the first resistor is also connected to the UVP pin of the first driving chip. The positive electrode of the second diode is connected to the power output terminal.

[0020] Further, the fifth control unit further includes a third resistor and a fourth resistor. The first end of the third resistor is connected to the first auxiliary power supply, the second end of the third resistor is grounded through the fourth resistor, and the second end of the third resistor is also connected to the OVP pin of the first driving chip.

[0021] Further, the power supply circuit further includes an energy storage capacitor, and the power output terminal is grounded through the energy storage capacitor.

[0022] In a second aspect, the present invention further provides an energy storage system, including a power supply circuit and a battery management system. The power supply circuit is the above-mentioned power supply circuit, and the power output terminal of the power supply circuit is connected to the battery management system.

[0023] The present utility model provides a power supply circuit and an energy storage system. The power supply circuit includes a first auxiliary power supply, a second auxiliary power supply, a power output terminal, a first anti-backflow circuit, a second anti-backflow circuit, and a switch circuit. The first auxiliary power supply is connected to the power output terminal through the first anti-backflow circuit. The second auxiliary power supply is connected to one end of the second anti-backflow circuit through the switch circuit, and the other end of the second anti-backflow circuit is connected to the power output terminal. The switch circuit is also connected to both the first auxiliary power supply and the power output terminal. The switch circuit is configured to turn off the power supply of the second auxiliary power supply to the power output terminal when the first auxiliary power supply is powered on and supplies power to the power output terminal, so that the first auxiliary power supply supplies power to the power output terminal prior to the second auxiliary power supply. The first anti-backflow circuit is used to prevent current backflow between the first auxiliary power supply and the second auxiliary power supply. The second anti-backflow circuit is used to prevent current backflow between the second auxiliary power supply and the first auxiliary power supply. By implementing the embodiments of the present application, when the first auxiliary power supply is normal, the first auxiliary power supply is preferably used to supply power to the battery management system, which can avoid consuming the energy in the second auxiliary power supply and ensure that the battery management system can maintain power supply regardless of the state of the first auxiliary power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 The circuit schematic block diagram of the power supply circuit according to the embodiment of the present application is shown;

[0026] Figure 2 The circuit schematic diagram of the first anti-backflow circuit of the power supply circuit according to the embodiment of the present application is shown;

[0027] Figure 3 The circuit schematic diagram of the second anti-backflow circuit of the power supply circuit according to the embodiment of the present application is shown;

[0028] Figure 4 The circuit diagram of the first anti-backflow circuit of the power supply circuit according to the embodiment of the present application is shown;

[0029] Figure 5 The circuit logic schematic block diagram of the power supply circuit according to the embodiment of the present application is shown;

[0030] Figure 6 The circuit diagram of the self-locking circuit structure of the power supply circuit according to the embodiment of the present application is shown;

[0031] Figure 7The circuit diagram shows the circuit structure of the power supply circuit in the embodiment of the present application to realize the disconnection of the first auxiliary power supply and the power supply of the second auxiliary power supply.

[0032] Figure 8 The circuit diagram shows a specific example scenario of the power supply circuit in the embodiment of the present application. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] The directional terms mentioned in the present invention, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are only references to the directions in the attached drawings. Therefore, the directional terms used are for explaining and understanding the present invention, rather than for limiting the present invention. In addition, in the drawings, structures that are similar or the same are denoted by the same reference numerals.

[0035] Please refer to Figure 1 , the embodiment of the present invention shows a power supply circuit, including: a first auxiliary power supply 10, a second auxiliary power supply 20, a power output terminal 30, a first anti-backflow circuit 41, a second anti-backflow circuit 42, and a switch circuit 43; the first auxiliary power supply 10 is connected to the power output terminal 30 through the first anti-backflow circuit 41, the second auxiliary power supply 20 is connected to one end of the second anti-backflow circuit 42 through the switch circuit 43, and the other end of the second anti-backflow circuit 42 is connected to the power output terminal 30; the switch circuit 43 is also connected to both the first auxiliary power supply 10 and the power output terminal 30;

[0036] The switch circuit 43 is configured to turn off the power supply of the second auxiliary power supply 20 to the power output terminal 30 when the first auxiliary power supply 10 is powered on and supplies power to the power output terminal, so that the first auxiliary power supply 10 supplies power to the power output terminal 30 prior to the second auxiliary power supply 20;

[0037] The first anti-backflow circuit 41 is configured to prevent current backflow between the first auxiliary power supply 10 and the second auxiliary power supply 20;

[0038] The second anti-backflow circuit 42 is configured to prevent current backflow between the second auxiliary power supply 20 and the first auxiliary power supply 10.

[0039] Refer to Figure 1, specifically, the first auxiliary power supply 10 uses the mains power as the input source. The mains power is converted into DC 24V through AC / DC conversion to serve as the first auxiliary power supply 10. The second auxiliary power supply 20 is a battery module (such as an energy storage battery). The battery in the battery module is converted into DC 24V through DC / DC conversion and serves as the second auxiliary power supply 20. The power output terminal 30 is connected to the battery management system (i.e., BMS) to supply power to it. The first auxiliary power supply 10 is used as the main power supply and the second auxiliary power supply 20 is used as the backup power supply to supply power to the battery management system (wherein, the supply voltage corresponding to the power output terminal 30 can be set to DC 24V as in the above example), that is, the first auxiliary power supply 10 supplies power to the power output terminal 30 prior to the second auxiliary power supply 20.

[0040] Among them, when the first auxiliary power supply 10 is powered on and can supply power to the power output terminal 30, the switch circuit 43 can be controlled to cut off the power supply of the second auxiliary power supply 20 to the power output terminal 30, and in this process, the reverse power flow from the first auxiliary power supply 10 to the second auxiliary power supply 20 can also be prevented based on the reverse power flow prevention characteristic of the first reverse power flow prevention circuit 41 itself.

[0041] If the first auxiliary power supply 10 is not powered on but the second auxiliary power supply 20 is powered on, the switch circuit 43 can be turned on by pressing the push-button switch in the switch circuit 43 (for example, when a MOS transistor is also provided in the switch circuit 43 in addition to the push-button switch, pressing the push-button switch will turn on the MOS transistor), so that the second auxiliary power supply 20 supplies power to the power output terminal 30. And in this process, the reverse power flow from the first auxiliary power supply 10 to the second auxiliary power supply 20 can also be prevented based on the reverse power flow prevention characteristic of the second reverse power flow prevention circuit 42 itself.

[0042] If the first auxiliary power supply 10 suddenly loses power, it is necessary to switch to the second auxiliary power supply 20 to supply power to the power output terminal 30. Specifically, if the power output terminal 30 is also grounded through a storage capacitor, when the first auxiliary power supply 10 suddenly loses power, due to the existence of the storage capacitor, the power output terminal 30 loses power slowly; moreover, the voltage of the power output terminal 30 is self-locked with the signal of the switch circuit 43 (specifically, a first driving chip that jointly forms a control unit with the push-button switch is also provided in the switch circuit 43, and the voltage of the power output terminal 30 is interlocked with the signal of one of the pins of the first driving chip, such as the Enable enable pin), and the switch circuit 43 is reopened (specifically, the MOS transistor is re-conducted), so that the second auxiliary power supply 20 supplies power to the power output terminal 30.

[0043] Of course, there is also a situation where the first auxiliary power supply 10 is not powered on before startup but the second auxiliary power supply 20 is powered on. In this case, the switch circuit 43 can be turned on by pressing the push-button switch in the switch circuit 43 for black start-up, so that the second auxiliary power supply 20 supplies power to the power output terminal 30.

[0044] In one embodiment, referring to Figure 2 , the first anti-backflow circuit 41 includes a first switch unit 411 and a first control unit 412; the input end of the first switch unit 411 is connected to the first auxiliary power supply 10, and the output end of the first switch unit 411 is connected to the power output terminal 30; the first end of the first control unit 412 is connected to the output end of the first switch unit 411, the second end of the first control unit 412 is connected to the input end of the first switch unit 411, and the output end of the first control unit 412 is connected to the control end of the first switch unit 411.

[0045] In this embodiment, the first anti-backflow circuit 41 simulates an ideal diode circuit through the first switch unit 411 and the first control unit 412. The ideal diode has the characteristics of zero forward voltage drop, infinite reverse impedance, instantaneous conduction and cut-off, and no power consumption. Among them, zero forward voltage drop means that under forward bias conditions, that is, when the current flows from the anode to the cathode, the voltage drop of the ideal diode is 0V, which means that the ideal diode does not generate any energy loss when conducting; infinite reverse impedance means that in the reverse bias state, that is, when the voltage is applied in such a way that the current tries to flow from the cathode to the anode, the ideal diode does not conduct electricity at all, showing an infinite resistance, that is, there is no reverse leakage current; instantaneous conduction and cut-off means that the ideal diode immediately conducts when the forward voltage exceeds a certain threshold (theoretically can be considered as 0V), and immediately cuts off under reverse bias, just like a perfect electronic switch without delay; no power consumption means that due to the forward voltage drop being 0 and not conducting electricity under reverse bias, the ideal diode does not consume energy and does not heat up when working.

[0046] Compared with the anti-backflow circuit in the industrial and commercial energy storage system using a diode, since the diode itself has a voltage drop of 0.5V, the higher the current flowing through it, the higher the temperature rise of the diode. Although each battery pack in the industrial and commercial energy storage system is equipped with a fan, the overall load is large, and the diode is prone to overheating and damage, so it can no longer prevent the two power supplies from flowing back to each other. In this application, through the ideal diode circuit simulated by the first switch unit 411 and the first control unit 412, the tube voltage drop of the original diode is reduced to nearly 0V, making it have the characteristics of zero forward voltage drop, infinite reverse impedance, instantaneous conduction and cut-off, and no power consumption, so that the first anti-backflow circuit 41 cannot be easily damaged, thus preventing the two power supplies from flowing back to each other.

[0047] In one embodiment, continue to refer toFigure 2 The first anti-backflow circuit 41 further includes a second switch unit 413 and a second control unit 414; the input end of the second switch unit 413 is connected to the control end of the first switch unit 411, and the output end of the second switch unit 413 is connected to the output end of the first switch unit 411; the first end of the second control unit 414 is connected to the input end of the first switch unit 411, the second end of the second control unit 414 is connected to the output end of the first switch unit 411, and the output end of the second control unit 414 is connected to the control end of the second switch unit 413.

[0048] In this embodiment, the second switch unit 413 and the second control unit 414 are components of the first anti-backflow circuit 41, and their function is to accelerate the turn-off of the first switch unit 411 acting as an ideal diode in the case of reverse voltage.

[0049] In one embodiment, the first control unit 412 includes a first comparison unit. The voltage acquisition terminals of the first comparison unit are respectively connected to the input end and the output end of the first switch unit 411 to acquire the first voltage difference between the input end and the output end of the first switch unit 411. The output end of the first comparison unit is connected to the control end of the first switch unit 411. The first comparison unit is used to compare the magnitude of the first voltage difference with a first reference voltage to control the on / off of the first switch unit 411.

[0050] In this embodiment, the first comparison unit compares the magnitude of the first voltage difference between the two ends of the first switch unit 411 with the first reference voltage to output a control signal to control the conduction or turn-off of the first switch unit 411. Specifically, the comparison unit used by the first comparison unit can be a comparator, an operational amplifier, or other digital logic circuits and other devices with comparison functions, which are not limited herein. The comparison unit used by the first comparison unit has a voltage acquisition terminal. The voltage acquisition terminal is respectively connected to the input end and the output end of the first switch unit 411. The first voltage difference between the input end and the output end of the first switch unit 411 is acquired through the voltage acquisition terminal. Whether there is current backflow can be obtained through this first voltage difference. Then, the first voltage difference is compared with the first reference voltage to timely turn off the first switch unit 411 to prevent current backflow. The first reference voltage can be a voltage value preset inside the first comparison unit or a voltage value obtained through a reference voltage, which is not limited herein. Since the first reference voltage is a stable voltage value, using the first reference voltage as the comparison object can improve the stability and reliability of the on / off of the first switch unit.

[0051] In one embodiment, the second control unit 414 includes a second comparison unit. The voltage acquisition terminals of the second comparison unit are respectively connected to the input terminal and the output terminal of the second switching unit 413 to acquire a second voltage difference between the input terminal and the output terminal of the second switching unit 413. The output terminal of the second comparison unit is connected to the control terminal of the second switching unit 413. The second comparison unit is configured to compare the magnitude between the second voltage difference and a second reference voltage to control the on / off of the second switching unit 413.

[0052] In this embodiment, the process in which the second comparison unit in the second control unit 414 controls the on / off of the second switching unit 413 by comparing the magnitude between the second voltage difference and the second reference voltage is similar to the process in which the first comparison unit in the foregoing first control unit 412 controls the on / off of the second switching unit 413 by comparing the magnitude between the first voltage difference and the first reference voltage. Moreover, since the input terminal of the second switching unit 413 is connected to the control terminal of the first switching unit 411, the on / off of the second switching unit 413 can directly control the control terminal of the first switching unit 411. Therefore, the conduction of the second switching unit 413 can directly turn off the first switching unit 411, realizing the accelerated turn-off of the first switching unit 411. Moreover, when dealing with a sudden reverse current. Since the second reference voltage is a stable voltage value, using the second reference voltage as the comparison object can improve the stability and reliability of the on / off of the second MOS transistor.

[0053] In one embodiment, please refer to Figure 1 、 Figure 2 and Figure 4 ,the first switching unit 411 is a first PMOS transistor Q1. The first comparison unit includes a first comparator AMP1 and a first reference unit Vref1 for providing the first reference voltage. The drain of the first PMOS transistor Q1 is connected to the first auxiliary power supply 10. The source of the first PMOS transistor Q1 is connected to the power output terminal 30. The gate of the first PMOS transistor Q1 is connected to the output terminal of the first comparator AMP1. The positive input terminal of the first comparator AMP1 is connected to the source of the first PMOS transistor Q1. The negative input terminal of the first comparator AMP1 is connected to the drain of the first PMOS transistor Q1 through the first reference unit Vref1.

[0054] In this embodiment, specifically, such as Figure 1 、 Figure 2 、 Figure 4 、 Figure 5 and Figure 8As shown, the drain of the first PMOS transistor Q1 is connected to the anode of the third diode D3, the cathode of the third diode D3 is connected to the source of the first PMOS transistor Q1, the gate and the source of the first PMOS transistor Q1 are connected through the fifth resistor R5, and the drain of the first PMOS transistor Q1 is also grounded through the first capacitor C1. Figure 5 The first control unit 412 in Figure 8 can specifically adopt the second driving chip U2 in

[0055] In an embodiment, please refer to Figure 1 、 Figure 2 and Figure 4 . The second switch unit 413 is a second PMOS transistor Q2. The second comparison unit includes a second comparator AMP2 and a second reference unit Vref2 for providing the second reference voltage. The drain of the second PMOS transistor Q2 is connected to the output terminal of the first comparator AMP1, the source of the second PMOS transistor Q2 is connected to the source of the first PMOS transistor Q1, the gate of the second PMOS transistor Q2 is connected to the output terminal of the second comparator AMP2, the positive input terminal of the second comparator AMP2 is connected to the drain of the first PMOS transistor Q1, and the negative input terminal of the second control unit AMP2 is connected to the source of the first PMOS transistor Q1 through the second reference unit Vref2.

[0056] In this embodiment, specifically, as Figure 1 , Figure 2 and Figure 4 shown, the gate of the second PMOS transistor Q2 is connected to the output terminal of the first comparator AMP1 through a sixth resistor R6, the gate of the second PMOS transistor Q2 is connected to the output terminal of the second comparator AMP2 through a seventh resistor R7, a connection is made between the gate and the source of the second PMOS transistor Q2 through an eighth resistor R8, and the source of the second PMOS transistor Q2 is also grounded through a second capacitor C2. The second comparator AMP2 compares the magnitude relationship between Vout - Vin and the second reference voltage provided corresponding to the second reference unit Vref1. The condition for the second comparator AMP2 to output a low level is that Vout - Vin > the second reference voltage, and when the second comparator AMP2 outputs a low level, the second PMOS transistor Q2 is turned on. After the second PMOS transistor Q2 is turned on, the gate voltage of the first PMOS transistor Q1 is pulled to the same as the source voltage, so that the first PMOS transistor Q1 is quickly turned off (this will immediately eliminate the electric field control of the gate on the channel in the first PMOS transistor Q1, resulting in the first PMOS transistor Q1 quickly changing from the on state to the off state), thereby coping with the sudden reverse current. The above setting realizes the direct gate control of the first PMOS transistor Q1, which not only improves the turn-off speed, but also enables the first PMOS transistor Q1 to have better unidirectional conductivity (that is, it conducts only at the forward voltage and quickly cuts off at the reverse voltage). Among them, the positive input terminal of the second comparator AMP2 can be regarded as the first terminal of the second control unit 414, the negative input terminal of the second comparator AMP2 can be regarded as the second terminal of the second control unit 414, and the output terminal of the second comparator AMP2 can be regarded as the output terminal of the second control unit 414.

[0057] Of course, in specific implementation, as Figure 2 and Figure 4 shown, the first switch unit 411 and the second switch unit 413 can also use NMOS transistors, and their circuits and working principles are similar to those of the above embodiment, which will not be elaborated here. In addition, the connection of the positive input terminal and the negative input terminal of the first comparator AMP1 and the second comparator AMP2 can also be swapped. For example, the positive input terminal connected to the source and the negative input terminal connected to the drain can be swapped to the positive input terminal connected to the drain and the negative input terminal connected to the source. The combination schemes formed by those skilled in the art according to simple polarity swapping to change the connection method are all equivalent to this embodiment.

[0058] In one embodiment, please refer to Figures 1 - 5, the second anti-backflow circuit 42 includes a third switch unit 421 and a third control unit 422; the input end of the third switch unit 421 is connected to the second end of the switch circuit 43, and the output end of the third switch unit 421 is connected to the power output end 30; the first end of the third control unit 422 is connected to the output end of the third switch unit 421, the second end of the third control unit 422 is connected to the input end of the third switch unit 421, and the output end of the third control unit 422 is connected to the control end of the third switch unit 421.

[0059] In this embodiment, both the core circuit structures of the second anti-backflow circuit 42 and the first anti-backflow circuit 41 include a control unit corresponding to the switch unit. For example, referring to Figure 3 , Figure 5 and Figure 8 the third switch unit 421 in uses a third PMOS transistor Q4 specifically, and the drain of the third PMOS transistor Q4 is connected to the positive electrode of the fourth diode D4, and the negative electrode of the fourth diode D4 is connected to the source of the third PMOS transistor Q4. The circuit structures of the second anti-backflow circuit 42 and the first anti-backflow circuit 41 are the same, except that the input end of the third switch unit 421 in the second anti-backflow circuit 42 is connected to the second auxiliary power supply 20 through the switch circuit 43, while the input end of the first switch unit 411 in the first anti-backflow circuit 41 is directly connected to the first auxiliary power supply 10. Among them, the switch circuit 43 connected to the second anti-backflow circuit 42 is used to construct a capacitive load soft start and support short-circuit protection. Figure 5 the third control unit 422 in can be specifically implemented by Figure 8 the third driving chip U3 in, and the second driving chip U3 can also be regarded as an ideal diode driving chip.

[0060] Among them, the second anti-backflow circuit 42 also simulates an ideal diode circuit through the third switch unit 421 and the third control unit 422, and also reduces the original diode forward voltage drop to nearly 0V, so that it has the characteristics of zero forward voltage drop, infinite reverse impedance, instantaneous conduction and cut-off, and no power consumption, which also makes the second anti-backflow circuit 42 not easily damaged, thus preventing the two power supplies from flowing back into each other.

[0061] In one embodiment, please refer to Figures 1 - 5, the second anti-backflow circuit 42 further includes a fourth switch unit 423 and a fourth control unit 424; the input end of the fourth switch unit 423 is connected to the control end of the third switch unit 421, the output end of the fourth switch unit 423 is connected to the output end of the third switch unit 421, the first end of the fourth control unit 424 is connected to the input end of the third switch unit 421, the second end of the fourth control unit 424 is connected to the output end of the third switch unit 421, and the output end of the fourth control unit 424 is connected to the control end of the fourth switch unit 423.

[0062] Specifically, in implementation, for the specific circuit and components used in the third switch unit 421, reference can be made to the first switch unit 411; for the specific circuit and components used in the third control unit 422, reference can be made to the first control unit 412; for the specific circuit and components used in the fourth switch unit 423, reference can be made to the second switch unit 413; for the specific circuit and components used in the fourth control unit 424, reference can be made to the second control unit 414, and details will not be elaborated here.

[0063] In an embodiment, please refer to Figure 1 , Figure 3 and Figures 5 - 8 , the switch circuit 43 includes a first MOS transistor Q3 and a fifth control unit 431. The drain of the first MOS transistor Q3 is connected to the second auxiliary power supply 20, and the source of the first MOS transistor Q3 is connected to the input end of the third switch unit 421; the first end of the fifth control unit 431 is connected to the drain of the first MOS transistor Q3, the second end of the fifth control unit 431 is connected to the output end of the third switch unit 421, the output end of the fifth control unit 431 is connected to the gate of the first MOS transistor Q3, and the second end of the fifth control unit 431 is also connected to the first auxiliary power supply 10.

[0064] In this embodiment, when a MOS transistor is specifically used in the switching circuit 43, compared with using a relay as the starting switch in the anti-backflow circuit of the industrial and commercial energy storage system, since the direct current of the relay is small, it is difficult to support the fan current of the fans loaded by each battery pack in the industrial and commercial energy storage system. If the relay model is increased, the total fan current it can load can be increased, but this will result in a larger volume of the relay, which is not conducive to the miniaturization design of the anti-backflow circuit. At the same time, the capacitive load carrying capacity of the relay is weak. When the number of its corresponding main board and slave boards is large and there is an input capacitor, it will cause the risk of contact adhesion of the relay, thus limiting the number of its switching times. In this application, the MOS transistor can construct a capacitive load soft start and support short-circuit protection, making up for the problems of insufficient switching ability, short service life, and insufficient overcurrent and short-circuit protection performance of using a relay. Moreover, by using the above switching circuit, the black start of the power supply circuit is realized, the stability and reliability of the power supply circuit are improved, and the service life is extended.

[0065] In one embodiment, please refer to Figure 1 , Figure 3 and Figures 5 - 8 , the fifth control unit 431 includes a key switch W1, a first diode D1, a second diode D2, a first resistor R1, a second resistor R2, and a first driving chip U1; the first end of the key switch W1 is connected to the drain of the first MOS transistor Q3, and the second end of the key switch W1 is connected to the positive electrode of the first diode D1; the negative electrode of the first diode D1 is connected to the first end of the first resistor R1, and the negative electrode of the first diode D1 is also connected to the negative electrode of the second diode D2; the second end of the first resistor R1 is grounded through the second resistor R2, and the second end of the first resistor R1 is also connected to the UVP pin of the first driving chip U1; the positive electrode of the second diode D2 is connected to the power output terminal 30.

[0066] In this embodiment, the UVP pin of the first driving chip U1 serves as the enable pin for turning on the first MOS transistor Q3 (specifically the Enable enable pin). When the first auxiliary power supply 10 is not powered on, press the key switch W1. The UVP pin of the first driving chip U1 detects that the current voltage is higher than the undervoltage point of the first driving chip U1 (which can specifically use a high-side driving chip). At this time, the first driving chip U1 turns on the first MOS transistor Q3, so that the second auxiliary power supply 20 supplies power to the power output terminal 30. After the DC voltage (such as DC24V) at the power output terminal 30 is established, the Enable signal sent by the first driving chip U1 to the first MOS transistor Q3 can be maintained through the second diode D2 to achieve enable self-locking. After that, pressing the key switch W1 again can release the process in which the first driving chip U1 continuously sends the Enable signal to the first MOS transistor Q3.

[0067] In one embodiment, please refer to Figure 1 , Figure 3 and Figures 5 - 8 , the fifth control unit 431 further includes a third resistor R3 and a fourth resistor R4; a first end of the third resistor R3 is connected to the first auxiliary power supply 10, a second end of the third resistor R3 is grounded through the fourth resistor R4, and the second end of the third resistor R3 is further connected to an OVP pin of the first driver chip U1.

[0068] In this embodiment, the OVP pin of the first driver chip U1 serves as another enable pin (specifically, the Disable enable pin) for turning off the first MOS transistor Q3. At this time, if the second auxiliary power supply 20 supplies power to the power output terminal 30 but the first auxiliary power supply 10 has been powered on, when the OVP pin of the first driver chip U1 detects that the current voltage is higher than the overvoltage protection point of the first driver chip U1, the first driver chip U1 turns off the first MOS transistor Q3 and switches back to the first auxiliary power supply 10 to supply power to the power output terminal 30, so that the first auxiliary power supply 10 supplies power to the power output terminal 30 prior to the second auxiliary power supply 20.

[0069] In one embodiment, please refer to Figures 1 - 8 , the power supply circuit further includes a storage capacitor C3, and the power output terminal 30 is grounded through the storage capacitor C3.

[0070] In this embodiment, when the first auxiliary power supply 10 suddenly loses power, when the second auxiliary power supply 20 has not immediately provided a DC voltage (such as DC24V) to the power output terminal 30, due to the presence of the storage capacitor C3, the power output terminal 30 loses power relatively slowly. The power output terminal 30 enables the first MOS transistor Q3 to conduct, realizing uninterrupted power supply to the battery management system.

[0071] Moreover, the storage capacitor C3 and the second diode D2 can also prevent a surge current from flowing through the key switch W1 when the power output terminal 30 is initially powered on, causing oxidation of the key contacts of the key switch W1 and resulting in poor contact.

[0072] In order to meet the uninterrupted operation of the battery management system, when actually selecting the storage capacitor C3, the capacitance value of the storage capacitor C3 is related to I, Δt, and ΔU, and the capacitance of the storage capacitor C3 satisfies the following conditions:

[0073]

[0074] Among them, C is the capacitance value of the energy storage capacitor C3, I is the maximum load current of the power output terminal 30, Δt is the switching time from the power failure of the first auxiliary power supply 10 to the opening of the first MOS tube Q3, and ΔU is the voltage difference between the power output terminal 30 and the preset undervoltage point of the first driver chip U1. Specifically, when the first auxiliary power supply 10 is powered off, the total capacitance of the input terminal corresponding to the power output terminal 30 is C (that is, the capacitance value of the energy storage capacitor C3). The voltage difference from 24V to the preset undervoltage point of the power output terminal 30, such as DC24V, is ΔU. Here, the "preset undervoltage point" refers to the undervoltage threshold of the UVP pin inside the first driver chip U1, which is converted to the voltage value of the power output terminal 30 through the voltage divider coefficient of the first resistor R1 and the second resistor R2, so that the actual voltage drop is less than the allowable voltage drop, and a certain margin is left, which can meet the uninterrupted operation of the battery management system, that is, the following inequality is satisfied:

[0075]

[0076] After the above inequality (2) is transformed into a formula, the capacitance value C of the energy storage capacitor C3 satisfies the above formula (1).

[0077] Reference Figures 1 - 8 In order to further understand the working principle of the power supply circuit of this embodiment, the following is explained through a specific application example scenario. The power supply circuit of this embodiment has the following states:

[0078] The first one is that the first auxiliary power source 10 is not powered, but the second auxiliary power source 20 is powered. By pressing the key switch W1, the first MOS tube Q3 is turned on, and the second auxiliary power source 20 supplies power to the battery management system.

[0079] The second type is that when the first auxiliary power supply 10 is powered on, the first auxiliary power supply 10 turns off the first MOS tube Q3 through the OVP pin of the first driver chip U1, so that the first auxiliary power supply 10 gives priority to powering the battery management system;

[0080] The third type is that when the first auxiliary power supply 10V suddenly loses power, the OVP pin of the first driver chip U1 is released. Due to the existence of the energy storage capacitor C3, the power output terminal 30 loses power more slowly; due to the second diode D2, the power output terminal 30 is self-locked to the enable signal, and the first MOS tube Q3 is turned on again, realizing uninterrupted power supply to the battery management system.

[0081] In summary, for the power supply circuit of this embodiment, when the first auxiliary power supply is normal, the first auxiliary power supply is preferentially used to supply power to the battery management system. In this way, the battery energy in the second auxiliary power supply can be saved, and at the same time, it can ensure that the battery management system can maintain power supply regardless of the state of the battery (protection state, under-voltage state, discharged state), which is convenient for personnel to check faults and perform repairs. Moreover, when the mains power supply of the first auxiliary power supply suddenly cuts off, it automatically switches to the second auxiliary power supply to achieve uninterrupted power supply. In addition, in the case of a mains power cut, the second auxiliary power supply is started up by black start through a button, enabling the battery to work under load.

[0082] An embodiment of the present invention further provides an energy storage system, including a power supply circuit and a battery management system. The power supply circuit is the power supply circuit of the above embodiment, and the power output terminal of the power supply circuit is connected to the battery management system. Specifically, the power supply circuit has been described in detail in the above embodiment. For the sake of simplicity of the specification, it will not be repeated here.

[0083] Through the energy storage system of this embodiment, the dual-power supply has priority. The first auxiliary power supply has priority over the second auxiliary power supply for power supply, and when the first auxiliary power supply loses power, it automatically switches to the second auxiliary power supply for power supply to achieve uninterrupted power supply for the system. The energy storage system uses an ideal diode to replace the traditional diode, reducing heat generation and preventing reverse current. Moreover, in the circuit using MOS transistors to construct the ideal diode, the accelerated turn-off of the ideal diode is realized. In addition, the energy storage system also realizes the black start and self-locking of the battery management system.

[0084] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A power supply circuit, characterized in that, Comprising: A first auxiliary power supply, a second auxiliary power supply, a power output terminal, a first anti-backflow circuit, a second anti-backflow circuit, and a switching circuit; The first auxiliary power supply is connected to the power output terminal through the first anti-backflow circuit, the second auxiliary power supply is connected to one end of the second anti-backflow circuit through the switching circuit, and the other end of the second anti-backflow circuit is connected to the power output terminal; the switching circuit is also connected to both the first auxiliary power supply and the power output terminal; The switching circuit is configured to turn off the power supply of the second auxiliary power supply to the power output terminal when the first auxiliary power supply is powered on and supplies power to the power output terminal, so that the first auxiliary power supply supplies power to the power output terminal prior to the second auxiliary power supply; The first anti-backflow circuit is configured to prevent current backflow between the first auxiliary power supply and the second auxiliary power supply; The second anti-backflow circuit is configured to prevent current backflow between the second auxiliary power supply and the first auxiliary power supply.

2. The power supply circuit according to claim 1, characterized in that The first anti-backflow circuit includes a first switching unit and a first control unit; the input end of the first switching unit is connected to the first auxiliary power supply, and the output end of the first switching unit is connected to the power output terminal; the first end of the first control unit is connected to the output end of the first switching unit, the second end of the first control unit is connected to the input end of the first switching unit, and the output end of the first control unit is connected to the control end of the first switching unit.

3. The power supply circuit according to claim 2, wherein The first anti-backflow circuit further includes a second switching unit and a second control unit; the input end of the second switching unit is connected to the control end of the first switching unit, and the output end of the second switching unit is connected to the output end of the first switching unit; the first end of the second control unit is connected to the input end of the first switching unit, the second end of the second control unit is connected to the output end of the first switching unit, and the output end of the second control unit is connected to the control end of the second switching unit.

4. The power supply circuit according to claim 2, wherein The first control unit includes a first comparison unit, and the voltage acquisition terminals of the first comparison unit are respectively connected to the input end and the output end of the first switching unit to acquire a first voltage difference between the input end and the output end of the first switching unit. The output end of the first comparison unit is connected to the control end of the first switching unit, and the first comparison unit is configured to compare the magnitude of the first voltage difference with a first reference voltage to control the on / off of the first switching unit.

5. The power supply circuit according to claim 3, wherein The second control unit includes a second comparison unit, and the voltage acquisition terminals of the second comparison unit are respectively connected to the input end and the output end of the second switching unit to acquire a second voltage difference between the input end and the output end of the second switching unit. The output end of the second comparison unit is connected to the control end of the second switching unit, and the second comparison unit is configured to compare the magnitude of the second voltage difference with a second reference voltage to control the on / off of the second switching unit.

6. The power supply circuit according to claim 1, wherein The second anti-backflow circuit includes a third switch unit and a third control unit; the input end of the third switch unit is connected to the second end of the switch circuit, and the output end of the third switch unit is connected to the power output end; the first end of the third control unit is connected to the output end of the third switch unit, the second end of the third control unit is connected to the input end of the third switch unit, and the output end of the third control unit is connected to the control end of the third switch unit.

7. The power supply circuit according to claim 6, characterized in that, The switch circuit includes a first MOS transistor and a fifth control unit. The drain of the first MOS transistor is connected to a second auxiliary power supply, and the source of the first MOS transistor is connected to the input end of the third switch unit; the first end of the fifth control unit is connected to the drain of the first MOS transistor, the second end of the fifth control unit is connected to the output end of the third switch unit, the output end of the fifth control unit is connected to the gate of the first MOS transistor, and the second end of the fifth control unit is also connected to the first auxiliary power supply.

8. The power supply circuit according to claim 7, wherein The fifth control unit includes a key switch, a first diode, a second diode, a first resistor, a second resistor, and a first driving chip; the first end of the key switch is connected to the drain of the first MOS transistor, and the second end of the key switch is connected to the positive electrode of the first diode; the negative electrode of the first diode is connected to the first end of the first resistor, and the negative electrode of the first diode is also connected to the negative electrode of the second diode; the second end of the first resistor is grounded through the second resistor, and the second end of the first resistor is also connected to the UVP pin of the first driving chip; the positive electrode of the second diode is connected to the power output end.

9. The power supply circuit according to claim 8, wherein The fifth control unit further includes a third resistor and a fourth resistor; the first end of the third resistor is connected to the first auxiliary power supply, the second end of the third resistor is grounded through the fourth resistor, and the second end of the third resistor is also connected to the OVP pin of the first driving chip.

10. An energy storage system, characterized in that, It includes a power supply circuit and a battery management system. The power supply circuit is the power supply circuit according to any one of claims 1-9, and the power output end of the power supply circuit is connected to the battery management system.

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