Ad hoc network communication circuit based on ZETA
By adopting the domestic ZETA communication chip ZTG1323B and improved circuit design, the supply chain instability and security risks of LoRa technology in the domestic market has been solved, and the domesticization of self-organized network communication has been achieved and signal stability has been improved.
Patent Information
- Application Number
- CN202422833434.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-11-20
AI Technical Summary
LoRa technology has supply chain instability and data security risks in the domestic market, and terminals and gateway chips are exclusively controlled by SEMTECH, resulting in domestic self-organized networking communications facing technological monopoly and security risks.
The domestic ZETA communication chip ZTG1323B is adopted, combined with RC filtering circuit and impedance matching network, designs an ad hoc network communication circuit, cancels the crystal oscillator circuit, uses the controller to output the clock signal, and improves the RF circuit to improve anti-interference and signal stability.
The domestic production of self-organized network communication has been realized, the stability and anti-interference of signal transmission have been improved, and the production cost has been reduced.
Smart Images
Figure CN223157082U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of communication, in particular to a self-organizing network communication circuit based on ZETA. Background Art
[0002] Self-organizing network communication is a network communication method that does not require fixed infrastructure, and nodes can self-organize, manage, and repair. It expands the coverage range through multi-hop transmission, supports dynamically changing network topologies, and is widely used in multiple fields such as military communication, emergency response, and the Internet of Things. It has the advantages of flexible deployment, high reliability, and wide application. As a mature LPWAN technology, LoRa has a wide application foundation in the domestic Internet of Things market. The LoRa technology is monopolized by the American company SEMTECH as an exclusive private technology, and the IP patents of the terminal and gateway chips are solely controlled by SEMTECH. Therefore, in the domestic market, the LoRa technology may face risk factors such as unstable supply chains, and there are also potential risks such as data theft and network control. Content of the Utility Model
[0003] Aiming at the defects of the prior art, the utility model provides a self-organizing network communication circuit based on ZETA. As a pure domestic LPWAN communication technology, ZETA realizes the full-stack localization of the communication module and can effectively address the problem of technology monopoly.
[0004] To solve the above technical problems, the technical solution adopted by the utility model is: a self-organizing network communication circuit based on ZETA, including a ZETA communication chip, an antenna interface, and a controller. The ZETA antenna is connected to the antenna interface. The transceiver interfaces of the ZETA communication chip are respectively connected to the antenna interface through signal processing circuits. The IO ports of the ZETA communication chip lead out SPI signal lines and interrupt lines to be connected to the controller.
[0005] Further, the signal processing circuit between the antenna interface and the sending interface of the ZETA communication chip includes a low-pass filter circuit and an impedance matching circuit. The low-pass filter circuit includes an inductor L6, capacitors C3 and C18. One end of the inductor L6 is connected to the antenna interface, and the other end of the inductor L6 is connected to the impedance matching circuit. The capacitor C3 is connected between one end of the inductor L6 and the ground, and the inductor C18 is connected between the other end of the inductor L6 and the ground. The impedance matching circuit includes inductors L8, L9, capacitors C17 and C19. The inductors L8, L9, and capacitor C17 are connected in series between the low-pass filter circuit and the ZETA communication sending interface, and a capacitor C19 is grounded between the inductor L8 and the inductor L9.
[0006] Furthermore, the signal processing circuit of the antenna interface and the receiving interface of the ZETA communication chip includes a low-pass filter circuit and a balun matching network. The low-pass filter circuit includes an inductor L6, a capacitor C3, and a capacitor C18. One end of the inductor L6 is connected to the antenna interface, and the other end of the inductor L6 is connected to the balun matching network. The balun matching network includes inductors L3, L4, L5 and capacitors C14, C16. The capacitor C14 is connected between the low-pass filter circuit and the receiving interface RXP of the ZETA communication chip. The inductor L5 is connected between the low-pass filter circuit and the receiving interface RXN of the ZETA communication chip. The inductor L4 is connected between the receiving interfaces RXP and RXN of the ZETA communication chip. The connection between the capacitor C14 and the inductor L4 is grounded through the inductor L3, and the connection between the inductor L5 and the inductor L4 is grounded through the capacitor C16.
[0007] Furthermore, 4 SPI signal lines are led out from the IO port of the ZETA communication chip, and the 4 SPI signal lines are respectively connected to the controller, and an RC filter circuit is provided between each of the 4 SPI signal lines and the controller.
[0008] Furthermore, the controller outputs a clock signal to the ZETA communication chip through an inverter.
[0009] Furthermore, the power supply VBAT is connected to the transmitting interface of the ZETA communication chip through an inductor L10, and the power supply VBAT is grounded through two parallel capacitors C20 and C21.
[0010] Furthermore, 3 interrupt lines are led out from the IO port of the ZETA communication chip.
[0011] Furthermore, the model of the ZETA communication chip is ZTG1323B.
[0012] Furthermore, the signal of the controller chip is STM32F103VET6.
[0013] The beneficial effects of the present utility model: The present utility model designs a self-organizing network communication circuit based on ZETA, selects the domestic chip ZETG1233B, realizes the localization of the self-organizing network, and can effectively address the problem of technology monopoly. An RC filter circuit is added to the SPI connection line between the communication unit and the controller, effectively improving the anti-interference ability of the line and making the signal transmission more stable. The design of some circuits is modified, greatly saving costs. Description of the Drawings
[0014] Figure 1 It is the circuit schematic diagram of the ZETA communication chip and its peripheral circuits;
[0015] Figure 2 It is the power supply schematic diagram of the controller and its peripheral circuits. Detailed Embodiments
[0016] In order to make the technical solution of the present utility model clearer and more understandable, the present utility model will be further described in detail through specific factual examples in conjunction with the accompanying drawings. The specific implementation cases described this time are only used to explain the present utility model and cannot be used to limit the present utility model.
[0017] Embodiment 1
[0018] This embodiment discloses a self-organizing network communication circuit based on ZETA, which includes a ZETA communication chip, an antenna interface, and a controller. The ZETA communication chip is used for signal transmission and reception. The domestic chip ZTG1323B is selected. The chip leads out 4 SPI signal lines and 3 interrupt lines and is connected to the controller through wires for data transmission and interrupt signal transmission. An RC filter circuit is connected in series at the SPI interface of the controller to improve anti-interference ability; the external crystal oscillator circuit of the ZETA chip is cancelled, and the control chip outputs a clock signal to the ZETA chip, and an inverter is connected in series, saving the cost of the crystal oscillator circuit; and part of the RF circuit is modified, and a Butterworth low-pass filter circuit is used, which can effectively remove high-frequency noise while impedance matching, improve the receiving sensitivity, and avoid interference from other frequency signals.
[0019] The specific structure of the ZETA communication chip and its peripheral circuit is as Figure 1 shown. The ZETA communication chip uses the domestic chip ZTG1323B, and the antenna is connected to the antenna interface RF1. Pins 15, 16, 17, and 18 of the ZETA communication chip U2 respectively lead out 4 SPI lines to connect to the controller U1 for SPI signal transmission, that is, the data collected by the ZETA communication chip is transmitted to the controller. Pins 13, 22, and 23 respectively lead out 3 interrupt lines to connect to the controller U1 for interrupt signal transmission, indicating the working state of the current communication chip.
[0020] Pins 1 and 2 (RXP, RXN) of the ZETA communication chip are data receiving interfaces, which are connected to the antenna interface RF1 through a signal processing circuit for receiving RF signals. Pin 4 (TX) of the ZETA communication chip is a data sending interface, which is also connected to the antenna interface RF1 through a signal processing circuit for outputting RF signals.
[0021] Specifically, the signal processing circuit of the antenna interface and the ZETA communication chip transmission interface includes a low-pass filter circuit and an impedance matching circuit. The low-pass filter circuit includes an inductor L6, a capacitor C3, and a capacitor C18. One end of the inductor L6 is connected to the antenna interface, and the other end of the inductor L6 is connected to the impedance matching circuit. The capacitor C3 is connected between one end of the inductor L6 and the ground, and the inductor C18 is connected between the other end of the inductor L6 and the ground. The impedance matching circuit includes an inductor L8, an inductor L9, a capacitor C17, and a capacitor C19. The inductor L8, the inductor L9, and the capacitor C17 are connected in series between the low-pass filter circuit and the ZETA communication transmission interface, and the capacitor C19 is grounded between the inductor L8 and the inductor L9.
[0022] The signal processing circuit of the antenna interface and the ZETA communication chip receiving interface includes a low-pass filter circuit and a balun matching network. The low-pass filter circuit includes an inductor L6, a capacitor C3, and a capacitor C18. One end of the inductor L6 is connected to the antenna interface, and the other end of the inductor L6 is connected to the balun matching network. The balun matching network includes an inductor L3, an inductor L4, an inductor L5, and capacitors C14 and C16. The capacitor C14 is connected between the low-pass filter circuit and the ZETA communication chip receiving interface RXP, the inductor L5 is connected between the low-pass filter circuit and the ZETA communication chip receiving interface RXN, the inductor L4 is connected between the ZETA communication chip receiving interfaces RXP and RXN, the capacitor C14 and the inductor L4 are grounded through the inductor L3, and the inductor L5 and the inductor L4 are grounded through the capacitor C16.
[0023] In this embodiment, the data generation and data reception share a low-pass filter circuit, that is, the low-pass filter circuit composed of the capacitors C3, C18, and the inductor L6. The low-pass filter circuit and the impedance matching circuit can remove high-frequency noise, improve the receiving sensitivity, and avoid the interference of other frequency signals while meeting the impedance matching. The balun matching network is also for impedance matching to make the signal amplitudes received by pins 1 and 2 of the ZETA communication chip U2 equal. At the same time, the power supply VBAT is connected to the ZETA communication chip transmission interface through the inductor L10, and the power supply VBAT is grounded through two parallel capacitors C20 and C21. The capacitors C20 and C21 are used to reduce the influence of the TX output on the power supply VBAT. A pull-down resistor circuit is added to pin 8 of the ZETA communication chip U2 for the selection of the working mode. The crystal oscillator circuit of pins 19 and 20 of the ZETA communication chip U2 is removed and replaced with a clock signal output by the control chip U1. The controller is connected to pin 19 of the ZETA communication chip U2 through an inverter U3 to provide a clock signal, saving the production cost.
[0024] Figure 2It is the partial circuit diagram of the controller. The controller U1 selects STM32F103VET6. The 51st pin of U1 is connected to the 18th pin of U2 through a series-connected 10Ω resistor R8, and a 10pF capacitor C28 is externally connected to the 18th pin of U2. The resistor and the capacitor form an RC filter circuit. Similarly, the 52nd and 54th pins of U1 are connected to the 15th and 17th pins of the ZETA communication chip U2, and RC filter circuits are also provided. A capacitor C29 is externally connected to the 53rd pin of U3, and the 16th pin of U2 is connected to the 53rd pin of U1 through a series-connected resistor R9. The RC filter circuit in the SPI communication line can effectively reduce the interference or jitter in the signal line and improve the anti-interference ability of the SPI interface. The controller is externally connected with a 16MHz crystal oscillator circuit. The PA8 pin of U1 outputs a clock signal. The controller selects an external high-speed clock and uses the external high-speed clock as the input clock source of the phase-locked loop (located inside the controller U1). The 32MHz signal is output through frequency doubling by the phase-locked loop and is connected to the 19th pin of U2 through an inverter U3.
[0025] The above description is only the basic principle and preferred embodiments of the present invention. Those skilled in the art can make improvements and substitutions to the present invention, which fall within the protection scope of the present invention.
Claims
1. A self-organizing network communication circuit based on ZETA, characterized in that: It includes a ZETA communication chip, an antenna interface, and a controller. The ZETA antenna is connected to the antenna interface. The transceiver interfaces of the ZETA communication chip are respectively connected to the antenna interface through signal processing circuits. The IO ports of the ZETA communication chip lead out SPI signal lines and interrupt lines and are connected to the controller.
2. The ZETA-based ad-hoc communication circuit according to claim 1, characterized in that: The signal processing circuit of the antenna interface and the transmit interface of the ZETA communication chip includes a low-pass filter circuit and an impedance matching circuit. The low-pass filter circuit includes an inductor L6, capacitors C3 and C18. One end of the inductor L6 is connected to the antenna interface, and the other end of the inductor L6 is connected to the impedance matching circuit. The capacitor C3 is connected between one end of the inductor L6 and the ground, and the inductor C18 is connected between the other end of the inductor L6 and the ground. The impedance matching circuit includes inductors L8, L9, capacitors C17 and C19. The inductors L8, L9 and capacitor C17 are connected in series between the low-pass filter circuit and the ZETA communication transmit interface. A capacitor C19 is grounded between the inductor L8 and the inductor L9.
3. The ZETA-based ad-hoc communication circuit according to claim 1, characterized in that: The signal processing circuit of the antenna interface and the receive interface of the ZETA communication chip includes a low-pass filter circuit and a balun matching network. The low-pass filter circuit includes an inductor L6, capacitors C3 and C18. One end of the inductor L6 is connected to the antenna interface, and the other end of the inductor L6 is connected to the balun matching network. The balun matching network includes inductors L3, L4, L5 and capacitors C14, C16. The capacitor C14 is connected between the low-pass filter circuit and the receive interface RXP of the ZETA communication chip. The inductor L5 is connected between the low-pass filter circuit and the receive interface RXN of the ZETA communication chip. The inductor L4 is connected between the receive interfaces RXP and RXN of the ZETA communication chip. The capacitor C14 and the inductor L4 are grounded through the inductor L3, and the inductor L5 and the inductor L4 are grounded through the capacitor C16.
4. The self-organizing network communication circuit based on ZETA according to claim 1, wherein: The IO ports of the ZETA communication chip lead out 4 SPI signal lines. The 4 SPI signal lines are respectively connected to the controller, and RC filter circuits are provided between the 4 SPI signal lines and the controller.
5. The self-organizing network communication circuit based on ZETA according to claim 1, characterized in that: The controller outputs a clock signal to the ZETA communication chip through an inverter.
6. The ZETA-based ad-hoc communication circuit according to claim 1, wherein: The power supply VBAT is connected to the transmit interface of the ZETA communication chip through an inductor L10, and the power supply VBAT is grounded through two parallel capacitors C20 and C21.
7. The ZETA-based ad-hoc communication circuit according to claim 1, wherein: The IO ports of the ZETA communication chip lead out 3 interrupt lines.
8. The self-organizing network communication circuit based on ZETA according to claim 1, characterized in that: The model of the ZETA communication chip is ZTG1323B.
9. The ZETA-based ad-hoc communication circuit according to claim 1, wherein: The signal of the controller chip is STM32F103VET6.