High-reliability Ethernet switching device

Abstract

The utility model discloses a high reliability Ethernet switching device relates to computer interconnection technical field, including Ethernet switching module, including microprocessing unit, Switch unit and PHY unit group, microprocessing unit and Switch unit both include at least one UART interface, the UART interface of Switch unit is connected with the UART interface of microprocessing unit, the PHY unit group includes PHY unit group, and the PHY unit group includes PHY unit group. The PHY unit group comprises a plurality of PHY units which are adaptively connected with the Switch unit; and the power supply module comprises a voltage conversion unit group, and the power supply module supplies power to the micro-processing unit, the Switch unit and the plurality of PHY units through the voltage conversion unit group based on the power supply time sequence. The Ethernet switching device has relatively high stability and reliability.

Description

Technical Field

[0001] The utility model relates to the technical field of computer interconnection, in particular to a highly reliable Ethernet switching device. Background Art

[0002] With the rapid development of computers and their interconnection technologies, Ethernet has become the most popular short-distance layer-2 computer network so far, and the core component of Ethernet is the Ethernet switch.

[0003] Generally, the basic components of Ethernet switches are mainly foreign brand switching chips and CPUs. The switching chips are mainly represented by foreign manufacturers such as Broadcom and Marvell, and adopt an open structure. The main considerations are non-security factors such as switching performance, reliability, and power consumption, resulting in many security vulnerabilities, enabling lawbreakers to easily implant monitoring and surveillance devices to steal national secret information, such as a series of security threats including computer technology defects, viruses, information garbage, hackers, and information extortion.

[0004] With the further development of informatization in China, information security issues have attracted increasing attention, and the demand for domestic switching solutions has become more and more urgent. At the same time, since the switching chip requires multiple power supplies and has high requirements for the power-on sequence, how to design a power supply scheme for domestic Ethernet switches, improve the power supply stability of the switches, and meet the power supply requirements of domestic switches is also an urgent problem to be solved. In addition, existing Ethernet switches also have problems such as a small number of interfaces and low reliability, and cannot meet the actual application requirements. Summary of the Utility Model

[0005] The inventor of the present utility model proposed a highly reliable Ethernet switching device in view of the above problems and technical requirements.

[0006] The technical solution of the present utility model is as follows:

[0007] A highly reliable Ethernet switching device, characterized by comprising:

[0008] An Ethernet switching module, including a microprocessing unit, a Switch unit, and a group of PHY units, wherein,

[0009] Both the microprocessing unit and the Switch unit each include at least one UART interface. The UART interface of the Switch unit is connected to the UART interface of the microprocessing unit. The group of PHY units includes a plurality of PHY units adaptively connected to the Switch unit;

[0010] The power supply module includes a voltage conversion unit group, and the power supply module supplies power to the microprocessing unit, the Switch unit, and multiple PHY units through the voltage conversion unit group based on the power supply timing.

[0011] A further technical solution thereof is that the Switch unit includes a Switch chip of model NF5120. The Switch chip includes a SerDes0 interface and a SerDes1 interface, and both the SerDes0 interface and the SerDes1 interface are configured in the QSGMII mode;

[0012] Both the SerDes0 interface and the SerDes1 interface are connected to the first PHY unit in the PHY unit group, and each of the SerDes0 interface and the SerDes1 interface is connected to a signal switching unit.

[0013] A further technical solution thereof is that the signal switching unit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a diode D1, a diode D2, an NPN transistor Q1, and an NMOS transistor Q2. Among them,

[0014] The microprocessing unit is connected to one end of the resistor R1 and the resistor R2 and the base of the NPN transistor Q1. The other end of the resistor R2 is grounded. The collector of the NPN transistor Q1 is connected to one end of the resistor R3 and one end of the capacitor C1. The other end of the resistor R3 is connected to the positive electrode of the diode D1. The other end of the capacitor C1 is connected to the negative electrode of the diode D1;

[0015] The positive electrode of the diode D2 is connected to the negative electrode of the diode D1. The negative electrode of the diode D2 is connected to one end of the capacitor C2 and one end of the resistor R4. The other end of the resistor R4 is connected to the gate of the NMOS transistor Q2. The other end of the capacitor C2 is grounded. The other end of the resistor R4 is grounded through the resistor R5.

[0016] A further technical solution thereof is that the voltage conversion unit group includes a voltage regulator chip U1, a voltage regulator chip U2, a voltage regulator chip U3, a voltage regulator chip U4, a voltage regulator chip U5, a voltage regulator chip U6, and a voltage regulator chip U7. Among them,

[0017] The input ends of the voltage regulator chip U1, the voltage regulator chip U2, the voltage regulator chip U3, the voltage regulator chip U4, the voltage regulator chip U5, the voltage regulator chip U6, and the voltage regulator chip U7 are all connected to the power supply voltage VCC;

[0018] The voltage regulator chip U1 is used to provide the required operating voltage for the microprocessing unit;

[0019] The voltage regulator chips U2, U3, U5, and U6 are used to provide the required operating voltage for the Switch unit.

[0020] A further technical solution thereof is that the power supply module further includes a delay unit, and the delay unit includes a first delay sub-unit, a second delay sub-unit, a third delay sub-unit, and a fourth delay sub-unit, wherein,

[0021] The first delay sub-unit includes a resistor R426, a resistor R443, a resistor R444, a resistor R445, a resistor R446, a capacitor C492, a capacitor C493, an NPN transistor Q15, and an NPN transistor Q16;

[0022] The output terminal of the voltage regulator chip U2 is connected to one end of the capacitor C492 and the base of the NPN transistor Q16 through the resistor R446. The other end of the capacitor C492 and the emitter of the NPN transistor Q16 are grounded. The output terminal of the voltage regulator chip U1 is connected to one end of the resistor R445 and the resistor R426. The other end of the resistor R445 is connected to the base of the NPN transistor Q15 through the resistor R443. The other end of the resistor R426 is connected to the collector of the NPN transistor Q15 and is connected to the voltage regulator chip U3 through the resistor R444. One end of the capacitor C493 is connected to the base of the NPN transistor Q15, and the other end of the capacitor C493 is grounded.

[0023] A further technical solution thereof is that the second delay sub-unit includes a resistor R427, a resistor R428, a resistor R429, a resistor R430, a resistor R431, a resistor R432, a capacitor C486, a capacitor C487, an NPN transistor Q19, and an NPN transistor Q10;

[0024] The output terminal of the voltage regulator chip U2 is connected to one end of the capacitor C487 and the base of the NPN transistor Q10 through the resistor R431. The output terminal of the voltage regulator chip U3 is connected to one end of the capacitor C487 and the base of the NPN transistor Q10 through the resistor R432;

[0025] The other end of the capacitor C487 and the emitter of the NPN transistor Q10 are grounded. The output terminal of the voltage regulator chip U1 is connected to one end of the resistor R429 and the resistor R427. The other end of the resistor R429 is connected to the base of the NPN transistor Q9 through the resistor R428. The other end of the resistor R427 is connected to the collector of the NPN transistor Q9 and is connected to the voltage regulator chip U4 through the resistor R430. One end of the capacitor C486 is connected to the base of the NPN transistor Q9, and the other end of the capacitor C486 is grounded.

[0026] A further technical solution thereof is that the third delay sub-unit includes a resistor R433, a resistor R434, a resistor R435, a resistor R436, a resistor R437, a capacitor C488, a capacitor C489, an NPN transistor Q11, and an NPN transistor Q12;

[0027] The output terminal of the voltage regulator chip U3 is connected to one end of the capacitor C488 and the base of the NPN transistor Q12 through the resistor R437. The other end of the capacitor C488 and the emitter of the NPN transistor Q12 are grounded. The output terminal of the voltage regulator chip U1 is connected to one end of the resistor R436 and the resistor R433. The other end of the resistor R436 is connected to the base of the NPN transistor Q11 through the resistor R435. The other end of the resistor R433 is connected to the collector of the NPN transistor Q11 and is connected to the voltage regulator chip U5 through the resistor R434. One end of the capacitor C489 is connected to the base of the NPN transistor Q11, and the other end of the capacitor C489 is grounded;

[0028] The fourth delay sub-unit includes a resistor R438, a resistor R439, a resistor R440, a resistor R441, a resistor R442, a capacitor C490, a capacitor C491, an NPN transistor Q13, and an NPN transistor Q14;

[0029] The output terminal of the voltage regulator chip U5 is connected to one end of the capacitor C491 and the base of the NPN transistor Q14 through the resistor R442. The other end of the capacitor C491 and the emitter of the NPN transistor Q14 are grounded. The output terminal of the voltage regulator chip U1 is connected to one end of the resistor R440 and the resistor R438. The other end of the resistor R440 is connected to the base of the NPN transistor Q13 through the resistor R439. The other end of the resistor R438 is connected to the collector of the NPN transistor Q13 and is connected to the voltage regulator chip U6 through the resistor R441. One end of the capacitor C490 is connected to the base of the NPN transistor Q13, and the other end of the capacitor C490 is grounded.

[0030] A further technical solution thereof is that the Ethernet switching device further includes a DDR4 chip connected to the Switch unit, and the power supply module further includes a DDR4 power supply unit;

[0031] The DDR4 power supply unit includes an operational amplifier, an under-voltage lockout UVLO1, an under-voltage lockout UVLO2, an AND gate AND1, an AND gate AND2, and a voltage regulator chip U8, where

[0032] The output terminal of the voltage regulator chip U3 is connected to the first input terminal of the under-voltage lockout UVLO1 and the non-inverting input terminal of the operational amplifier. The second input terminal of the under-voltage lockout UVLO1 is connected to a first reference voltage. The output terminal of the under-voltage lockout UVLO1 is connected to the first input terminal of the AND gate AND1;

[0033] The output terminal of the voltage regulator chip U7 is connected to the first input terminal of the under-voltage lockout UVLO2. The second input terminal of the under-voltage lockout UVLO2 is connected to a second reference voltage. The output terminal of the under-voltage lockout UVLO2 is connected to the second input terminal of the AND gate AND1;

[0034] The output terminal of the AND gate AND1 is connected to the first input terminal of the AND gate AND2. The second input terminal of the AND gate AND2 is connected to the microprocessing unit. The output terminal of the AND gate AND2 is connected to the positive power supply terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the second input terminal of the voltage regulator chip U8. The second output terminal of the voltage regulator chip U8 is connected to the DDR4 chip.

[0035] A further technical solution thereof is that the DDR4 power supply unit further includes a delay element Delay1, a delay element Delay2, an under-voltage lockout UVLO3, an under-voltage lockout UVLO4, and an AND gate AND3, wherein,

[0036] The second output terminal of the voltage regulator chip U8 is connected to the input terminal of the delay element Delay1. The output terminal of the delay element Delay1 is connected to the first input terminal of the under-voltage lockout UVLO3, the first input terminal of the under-voltage lockout UVLO4, and the inverting input terminal of the operational amplifier. The second input terminal of the under-voltage lockout UVLO3 is connected to a third reference voltage. The second input terminal of the under-voltage lockout UVLO4 is connected to a fourth reference voltage;

[0037] The output terminal of the under-voltage lockout UVLO3 is connected to the first input terminal of the AND gate AND3. The output terminal of the under-voltage lockout UVLO4 is connected to the second input terminal of the AND gate AND3. The output terminal of the AND gate AND3 is connected to the negative power supply terminal of the operational amplifier and the input terminal of the delay element Delay2. The output terminal of the delay element Delay2 is connected to the microprocessing unit.

[0038] A further technical solution thereof is that it further includes a connection module. The connection module includes a connector and a connection base plate. The Ethernet switching module is connected to the connection base plate through the connector, wherein,

[0039] The connection base plate includes a plurality of RJ45 interfaces, a plurality of SFP+ sockets, and a plurality of signal transformers corresponding to the RJ45 interfaces one by one.

[0040] The beneficial technical effects of the present utility model are as follows:

[0041] The present utility model provides a highly reliable Ethernet switching device, including a power supply module. The power supply module supplies power to a microprocessing unit, a Switch unit, and multiple PHY units through a voltage conversion unit group based on a power supply timing sequence. The microprocessing unit can monitor the power supply timing sequence during the power supply process, providing a highly stable power supply solution for the Ethernet switching device and improving the reliability of the Ethernet switching device. At the same time, through the selection and cooperation of the microprocessing unit, Switch unit, and PHY unit in the Ethernet switching module of the present application, the information security of the Ethernet switching device is effectively improved. The present application also expands the interface quantity of the Ethernet switching device through the cooperation of a high-speed signal switch and a PHY chip to meet the actual application requirements. Description of the Drawings

[0042] Figure 1 It is a schematic block diagram of an embodiment of the Ethernet switching device provided by the present utility model.

[0043] Figure 2 It is a schematic block diagram of an embodiment of the single-chip microcomputer provided by the present utility model.

[0044] Figure 3 It is an interface diagram of an embodiment of the single-chip microcomputer provided by the present utility model.

[0045] Figure 4 It is a schematic block diagram of an embodiment of the Switch chip provided by the present utility model.

[0046] Figure 5 It is a schematic block diagram of the SerDes interface configuration of the Switch chip in an embodiment of the present utility model.

[0047] Figure 6 It is a circuit schematic diagram of an embodiment of the signal switch unit provided by the present utility model.

[0048] Figure 7 It is a schematic diagram of an embodiment of the power supply module provided by the present utility model.

[0049] Figure 8 It is a power supply timing diagram of an embodiment of the power supply module provided by the present utility model.

[0050] Figure 9 It is a circuit schematic diagram of an embodiment of the first delay sub-unit provided by the present utility model.

[0051] Figure 10 It is a circuit schematic diagram of an embodiment of the second delay sub-unit provided by the present utility model.

[0052] Figure 11It is the circuit schematic diagram of an embodiment of the third delay sub-unit provided by the present utility model.

[0053] Figure 12 It is the circuit schematic diagram of an embodiment of the fourth delay sub-unit provided by the present utility model.

[0054] Figure 13 It is the circuit schematic diagram of an embodiment of the DDR4 power supply unit provided by the present utility model.

[0055] Figure 14 It is the connection schematic diagram of the Switch chip control bus in an embodiment of the present utility model.

[0056] Figure 15 It is the connection schematic diagram of the Switch chip and the PHY chip in an embodiment of the present utility model.

[0057] Figure 16 It is the schematic diagram of an embodiment of the connection module provided by the present utility model.

[0058] Figure 17 It is the connection schematic diagram of an embodiment of the reset module provided by the present utility model.

[0059] Figure 18 It is the circuit schematic diagram of an embodiment of the power input filter circuit of the SVDDL pin.

[0060] Figure 19 It is the circuit schematic diagram of an embodiment of the power input filter circuit of the SVDDH pin.

[0061] Figure 20 It is the circuit schematic diagram of an embodiment of the power input filter circuit of the PLLVDDL pin.

[0062] Figure 21 It is the circuit schematic diagram of an embodiment of the power input filter circuit of the AVDDH pin.

[0063] Figure 22 It is the circuit schematic diagram of an embodiment of the power input filter circuit of the DVDDIO pin.

[0064] Figure 23 It is the circuit schematic diagram of an embodiment of the power input filter circuit of the AVDDL pin.

[0065] Figure 24 It is the circuit schematic diagram of an embodiment of the power input filter circuit of the DVDDL pin. Detailed implementation manners

[0066] The following further describes the detailed implementation manners of the present utility model with reference to the accompanying drawings.

[0067] The present utility model provides a highly reliable Ethernet switching device, comprising:

[0068] An Ethernet switching module, including a microprocessing unit, a Switch unit, and a group of PHY (Physical Layer) units. Among them,

[0069] Both the microprocessing unit and the Switch unit each include at least one UART interface. The UART interface of the Switch unit is connected to the UART interface of the microprocessing unit. The group of PHY units includes multiple PHY units adaptively connected to the Switch unit;

[0070] A power supply module, including a group of voltage conversion units. The power supply module supplies power to the microprocessing unit, the Switch unit, and multiple PHY units through the group of voltage conversion units based on a power supply timing sequence.

[0071] In an embodiment of the present utility model, the microprocessing unit may select a single-chip microcomputer, i.e., an MCU, of model STC32G12K128. Figure 2 The principle block diagram of the single-chip microcomputer is shown. Figure 3 The interface diagram of the single-chip microcomputer is shown. The peripheral circuit of the single-chip microcomputer includes a power input filtering circuit, a 25MHz passive crystal oscillator for providing the system clock for the single-chip microcomputer, and a RESET reset chip for providing the reset signal for the single-chip microcomputer. Among them, the form of the power input filtering circuit can refer to the following description, and the specific forms of the passive crystal oscillator and the reset chip can be consistent with the prior art. To improve information security, the Switch unit adopts a domestic Switch chip of model NF5120 for realizing the Ethernet switching function. The Switch chip can provide 6 UART interfaces, namely UART0 - UART5 interfaces. In this embodiment, the UART0 interface is used as the default debugging serial port, and the UART2 interface is connected to the UART interface of the single-chip microcomputer to realize data communication. The specific connection method between the PHY units in the group of PHY units and the Switch chip can refer to the following description.

[0072] Since the Switch chip requires multiple power supplies and has complex power-on timing requirements, in order to achieve stable power supply for the device, in this application, a power supply module is used to supply power to the microprocessing unit, the Switch unit, and multiple PHY units through a voltage conversion unit group based on the power supply timing. The voltage conversion unit group includes multiple voltage regulator chips, which are used to convert the total power supply voltage of 12V into multiple power supply voltages and supply power to the microprocessing unit, the Switch unit, and multiple PHY units based on the power supply timing. At the same time, the microprocessing unit can also monitor the power supply timing during the power supply process and output a warning message when the power supply timing is incorrect, further improving the stability of the power supply of the Ethernet switch device. The specific form and working method of the power supply module can also be referred to the following description.

[0073] Further, the Switch unit includes a Switch chip of model NF5120. The Switch chip includes a SerDes0 interface and a SerDes1 interface, and both the SerDes0 interface and the SerDes1 interface are configured in the QSGMII mode;

[0074] Both the SerDes0 interface and the SerDes1 interface are connected to the first PHY unit in the PHY unit group, and each of the SerDes0 interface and the SerDes1 interface is connected to a signal switch unit.

[0075] Specifically, the Switch chip of model NF5120 provides a total of 8 SerDes interfaces, namely, SerDes0 interface - SerDes07 interface. Among them, the SerDes0 interface, the SerDes1 interface, the SerDes6 interface, and the SerDes7 interface can be configured in the SGMII or QSGMII mode, and the SerDes2 interface, the SerDes3 interface, the SerDes4 interface, and the SerDes5 interface can be configured in the SGMII mode, the QSGMII mode, the USGMII mode, or the 10GBase-R mode.

[0076] Such as Figure 5As shown in the figure, in this embodiment, the SerDes0 interface, SerDes1 interface, SerDes6 interface, and SerDes7 interface are all set to the QSGMII mode. The SerDes0 interface and SerDes1 interface are connected to the first PHY unit, and the SerDes6 interface and SerDes7 interface are connected to the second PHY unit. Both the first PHY unit and the second PHY unit are PHY chips of model NF1008, which are used to provide 16 Gigabit Ethernet ports. At the same time, the SerDes2 interface, SerDes3 interface, SerDes4 interface, and SerDes5 interface are configured in the 10GBase-R mode to provide 4 10 Gigabit SFP+ optical ports. The Switch chip has a total of 2 clock requirements. Among them, the system clock requires a 25MHz single-ended clock, which is provided by a passive crystal oscillator in this embodiment, and the Serdes clock requires a 156.25MHz differential clock, which is provided by an active crystal oscillator in this embodiment.

[0077] At the same time, in order to expand the ports to meet the application requirements, the SerDes0 interface and the SerDes1 interface are each connected to a signal switching unit to multiplex the QSGMII signals output by the SerDes0 interface and the SerDes1 interface. Optionally, the SerDes0 interface is connected to the third PHY unit through the signal switching unit, and the SerDes1 interface is connected to the fourth PHY unit through the signal switching unit. Both the third PHY unit and the fourth PHY unit use QSGMII PHY chips of model YT8614Q, and each QSGMII PHY chip can provide 4 Gigabit optical ports to increase the number of optical ports of the Ethernet device.

[0078] Further, the signal switching unit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a diode D1, a diode D2, an NPN transistor Q1, and an NMOS transistor Q2, where

[0079] The microprocessing unit is connected to one end of the resistor R1, the resistor R2, and the base of the NPN transistor Q1 through the resistor R1. The other end of the resistor R2 is grounded. The collector of the NPN transistor Q1 is connected to one end of the resistor R3 and one end of the capacitor C1. The other end of the resistor R3 is connected to the positive electrode of the diode D1. The other end of the capacitor C1 is connected to the negative electrode of the diode D1;

[0080] The positive electrode of the diode D2 is connected to the negative electrode of the diode D1. The negative electrode of the diode D2 is connected to one end of the capacitor C2 and one end of the resistor R4. The other end of the resistor R4 is connected to the gate of the NMOS transistor Q2. The other end of the capacitor C2 is grounded, and the other end of the resistor R4 is grounded through the resistor R5.

[0081] Figure 6 The circuit schematic diagram of an embodiment of the signal switching unit is shown. The signal switching unit is used to multiplex QSGMII signals. Since QSGMII signals are high-speed differential signals with a bandwidth of 2.5 GHz, there are relatively high requirements for the on-resistance, return loss, and insertion loss of the switch. Therefore, conventional signal switch circuits cannot meet the requirements. In this embodiment, diodes D1, D2, capacitors C1, and C2 in the signal switching unit form a charge pump circuit. One end of resistor R3 and the positive electrode of diode D1 are connected to the power supply module to access a 3.3V power supply. When it is necessary to expand the optical port, the MCU outputs a PWM wave to drive the charge pump circuit to work, causing NMOS transistor Q2 to conduct. The QSGMII signal is input from the drain of NMOS transistor Q2 and output from the source to the corresponding QSGMII PHY chip to achieve the expansion of the optical port. To prevent insufficient drive current output from the MCU pin, resistors R1, R2, and NPN transistor Q1 form a switch circuit, and the 3.3V power supply provides the drive current to improve the drive ability of the PWM wave to drive the charge pump circuit to work.

[0082] In this embodiment, the threshold voltage Vgs(th) of NMOS transistor Q2 is 4.2V. When the charge pump circuit is not working, capacitor C1 is charged by the 3.3V power supply voltage until the voltage across both ends is 3.3V, with the polarity being positive on the upper side and negative on the lower side. At this time, after voltage division by resistors R4 and R5, the gate voltage of NMOS transistor Q2 is less than 4.2V, which is less than the threshold voltage, and NMOS transistor Q2 is turned off. When the MCU outputs a PWM wave to drive the charge pump circuit to work, when the PWM wave is at a high level, capacitor C1 discharges quickly, and the voltage across capacitor C1 is superimposed with the 3.3V power supply voltage to charge capacitor C2 at the same time. After being fully charged, the voltage across capacitor C2 is 6.6V; when the PWM wave is at a low level, capacitor C2 discharges, and after voltage division by resistors R4 and R5, the gate voltage of NMOS transistor Q2 is stably greater than the threshold voltage, and NMOS transistor Q2 conducts to achieve the signal switching function. The resistance values of resistors R4 and R5 can be set according to the threshold voltage of NMOS transistor Q2. This signal switch circuit has a small on-resistance, and the return loss and insertion loss are also small, meeting the application requirements of QSGMII signals.

[0083] Further, the voltage conversion unit group includes voltage regulator chips U1, U2, U3, U4, U5, U6, and U7, where

[0084] the input terminals of voltage regulator chips U1, U2, U3, U4, U5, U6, and U7 are all connected to the power supply voltage VCC;

[0085] The voltage regulator chip U1 is used to provide the required operating voltage for the microprocessing unit;

[0086] The voltage regulator chips U2, U3, U5, and U6 are used to provide the required operating voltage for the Switch unit.

[0087] Specifically, in this embodiment, the MCU requires a 3.3V power supply voltage, the PHY chip with the model NF1008 requires power supply voltages of 3.3V and 1.1V, and the Switch chip with the model NF5120 requires power supply voltages of 0.9V, 1.2V, 1.8V, and 3.3V. At the same time, the Ethernet switching device further includes a DDR4 chip connected to the Switch chip. The DDR4 chip needs to be connected to a first power supply voltage VDD of 1.2V, a second power supply voltage VDDQ of 1.2V, a reference power supply voltage Vref of 1.2V, an activation power supply voltage VPP of 2.5V, and a matching power supply voltage VTT with a voltage value of VDDQ / 2. Among them, the Switch chip and the PHY chip have power supply timing requirements. The power supply timing of different power supply voltages of the Switch chip is in sequence: 0.9V, 1.2V, 1.8V, 3.3V. The power supply timing of the PHY chip requires that the 1.1V power supply voltage is supplied before the 3.3V power supply voltage.

[0088] In this embodiment, the power supply voltage VCC is 12V. The voltage regulator chip U1 converts VCC into a 3.3V power supply voltage to supply power to the MCU preferentially, and controls the voltage regulator chips U2 - U7 to supply power according to the power supply timing through the enable signal output by the MCU. The voltage regulator chip U2 converts VCC into a 0.9V power supply voltage to supply power to the Switch chip, and the voltage regulator chip U3 converts VCC into a 1.2V power supply voltage to supply power to the Switch chip and the DDR4 chip. The voltage regulator chip U4 converts VCC into a 1.1V power supply voltage to supply power to the PHY chip, the voltage regulator chip U5 converts VCC into a 1.8V power supply voltage to supply power to the Switch chip, the voltage regulator chip U6 converts VCC into a 3.3V power supply voltage to supply power to the Switch chip and the PHY chip, and the voltage regulator chip U7 converts VCC into a 2.5V power supply voltage to supply power to the DDR4 chip. In this embodiment, the models of the voltage regulator chips U1, U3, U5, and U6 are JW5393HF, the models of the voltage regulator chips U2 and U4 are JWH5083, the model of the voltage regulator chip U7 is JWH7821, and the model of the voltage regulator chip U8 is XSC51200.

[0089] Figure 8The power supply timing diagram of the power supply module is shown. To distinguish the power supply voltage of the MCU 3.3V and the power supply voltage of the Switch chip 3.3V, the power supply voltage of the MCU 3.3V is represented by 3.3V_STBY, as Figure 8 shown, the power supply timing of the power supply module in this embodiment is as follows: 3.3V_STBY, 0.9V, 1.2V, 1.1V, 1.8V, 3.3V / 2.5V means that the power supply voltage of the Switch chip 3.3V and the power supply voltage of the DDR4 chip 2.5V are supplied simultaneously. The power supply interval is set to 20ms through the MCU. Specifically, the power supply interval and power supply timing can be set according to the actual situation. At the same time, power supply parameters are preset in the MCU, including the number of power supply voltages, power supply timing, and power supply interval. The MCU detects the real-time power supply timing and compares it with the set power supply timing. If the timing is incorrect, the MCU outputs an alarm message through the serial port, indicating that the power-on timing of the board is incorrect, and locates the faulty power supply for the debugging personnel to troubleshoot.

[0090] At the same time, for the convenience of fault debugging, the power supply module is also provided with a delay unit. The delay unit is a hardware timing control circuit that can sequentially output the enable signals of each voltage regulator chip according to the above power supply timing. In actual application, the enable signal can be output by the MCU or by the delay unit.

[0091] The delay unit includes a first delay sub-unit, a second delay sub-unit, a third delay sub-unit, and a fourth delay sub-unit, as Figure 9 shown, the first delay sub-unit includes resistor R426, resistor R443, resistor R444, resistor R445, resistor R446, capacitor C492, capacitor C493, NPN transistor Q15, and NPN transistor Q16. The output terminal of the voltage regulator chip U2 is connected to one end of the capacitor C492 and the base of the NPN transistor Q16 through the resistor R446. The other end of the capacitor C492 and the emitter of the NPN transistor Q16 are grounded. The output terminal of the voltage regulator chip U1 is connected to one end of the resistor R445 and the resistor R426. The other end of the resistor R445 is connected to the base of the NPN transistor Q15 through the resistor R443. The other end of the resistor R426 is connected to the collector of the NPN transistor Q15 and is connected to the voltage regulator chip U3 through the resistor R444. One end of the capacitor C493 is connected to the base of the NPN transistor Q15, and the other end of the capacitor C493 is grounded.

[0092] As Figure 10As shown, the second delay sub-unit includes resistor R427, resistor R428, resistor R429, resistor R430, resistor R431, resistor R432, capacitor C486, capacitor C487, NPN transistor Q19, and NPN transistor Q10. The output terminal of the voltage regulator chip U2 is connected to one end of capacitor C487 and the base of NPN transistor Q10 through resistor R431. The output terminal of the voltage regulator chip U3 is connected to one end of capacitor C487 and the base of NPN transistor Q10 through resistor R432. The other end of capacitor C487 and the emitter of NPN transistor Q10 are grounded. The output terminal of the voltage regulator chip U1 is connected to one end of resistor R429 and resistor R427. The other end of resistor R429 is connected to the base of NPN transistor Q9 through resistor R428. The other end of resistor R427 is connected to the collector of NPN transistor Q9 and is connected to the voltage regulator chip U4 through resistor R430. One end of capacitor C486 is connected to the base of NPN transistor Q9, and the other end of capacitor C486 is grounded.

[0093] As Figure 11 shown, the third delay sub-unit includes resistor R433, resistor R434, resistor R435, resistor R436, resistor R437, capacitor C488, capacitor C489, NPN transistor Q11, and NPN transistor Q12. The output terminal of the voltage regulator chip U3 is connected to one end of capacitor C488 and the base of NPN transistor Q12 through resistor R437. The other end of capacitor C488 and the emitter of NPN transistor Q12 are grounded. The output terminal of the voltage regulator chip U1 is connected to one end of resistor R436 and resistor R433. The other end of resistor R436 is connected to the base of NPN transistor Q11 through resistor R435. The other end of resistor R433 is connected to the collector of NPN transistor Q11 and is connected to the voltage regulator chip U5 through resistor R434. One end of capacitor C489 is connected to the base of NPN transistor Q11, and the other end of capacitor C489 is grounded.

[0094] As Figure 12As shown, the fourth delay sub-unit includes resistor R438, resistor R439, resistor R440, resistor R441, resistor R442, capacitor C490, capacitor C491, NPN transistor Q13 and NPN transistor Q14; the output terminal of the voltage regulator chip U5 is connected to one end of capacitor C491 and the base of NPN transistor Q14 through resistor R442, the other end of capacitor C491 and the emitter of NPN transistor Q14 are grounded, the output terminal of the voltage regulator chip U1 is connected to one end of resistor R440 and resistor R438, the other end of resistor R440 is connected to the base of NPN transistor Q13 through resistor R439, the other end of resistor R438 is connected to the collector of NPN transistor Q13 and is connected to the voltage regulator chip U6 through resistor R441, one end of capacitor C490 is connected to the base of NPN transistor Q13, and the other end of capacitor C490 is grounded.

[0095] As can be seen from the above description, the DDR4 chip needs to be connected to the first power supply voltage VDD of 1.2V, the second power supply voltage VDDQ of 1.2V, the reference power supply voltage Vref of 1.2V, the activation power supply voltage VPP of 2.5V, and the matching power supply voltage VTT with a voltage value of VDDQ / 2. Among them, VDD and VDDQ are provided by the voltage regulator chip U3, and VPP is provided by the voltage regulator chip U7. Since the matching power supply voltage VTT has relatively high requirements for the power supply current, the power supply current provided by the conventional voltage regulator chip cannot meet the requirements. Therefore, the present invention provides a DDR4 power supply unit to provide the matching power supply voltage VTT for the DDR4 chip and simultaneously provide undervoltage and overvoltage detection for the DDR4 chip.

[0096] As Figure 13 As shown, the DDR4 power supply unit includes an operational amplifier, undervoltage lockout UVLO1, undervoltage lockout UVLO2, undervoltage lockout UVLO3, undervoltage lockout UVLO4, AND gate AND1, AND gate AND2, AND gate AND3, voltage regulator chip U8, delay unit Delay1 and delay unit Delay2. Among them, the output terminal of the voltage regulator chip U3 is connected to the first input terminal of the undervoltage lockout UVLO1 and the non-inverting input terminal of the operational amplifier, the second input terminal of the undervoltage lockout UVLO1 is connected to the first reference voltage, and the output terminal of the undervoltage lockout UVLO1 is connected to the first input terminal of the AND gate AND1;

[0097] The output terminal of the voltage regulator chip U7 is connected to the first input terminal of the undervoltage lockout UVLO2, the second input terminal of the undervoltage lockout UVLO2 is connected to the second reference voltage, and the output terminal of the undervoltage lockout UVLO2 is connected to the second input terminal of the AND gate AND1;

[0098] The output terminal of the AND gate AND1 is connected to the first input terminal of the AND gate AND2. The second input terminal of the AND gate AND2 is connected to the microprocessing unit. The output terminal of the AND gate AND2 is connected to the positive power supply terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the second input terminal of the voltage regulator chip U8. The second output terminal of the voltage regulator chip U8 is connected to the DDR4 chip;

[0099] The second output terminal of the voltage regulator chip U8 is also connected to the input terminal of the delay device Delay1. The output terminal of the delay device Delay1 is connected to the first input terminal of the under-voltage lockout UVLO3, the first input terminal of the under-voltage lockout UVLO4, and the inverting input terminal of the operational amplifier. The second input terminal of the under-voltage lockout UVLO3 is connected to a third reference voltage. The second input terminal of the under-voltage lockout UVLO4 is connected to a fourth reference voltage;

[0100] The output terminal of the under-voltage lockout UVLO3 is connected to the first input terminal of the AND gate AND3. The output terminal of the under-voltage lockout UVLO4 is connected to the second input terminal of the AND gate AND3. The output terminal of the AND gate AND3 is connected to the negative power supply terminal of the operational amplifier and the input terminal of the delay device Delay2. The output terminal of the delay device Delay2 is connected to the microprocessing unit.

[0101] In this embodiment, the model of the voltage regulator chip U8 is XSC51200, which includes a VREF_IN pin, a VREF_O pin, and a VO pin. The VREF_IN pin is the first input terminal of the voltage regulator chip U8. The VIN pin is the second input terminal of the voltage regulator chip U8. The VREF_O pin is the first output terminal of the voltage regulator chip U8, which outputs a reference power supply voltage of 1.2V. The VO pin is the second output terminal of the voltage regulator chip U8, which outputs a matching voltage VTT of 0.6V.

[0102] In this embodiment, the first reference voltage is set to 1.1V, and the second reference voltage is set to 2.25V. The under-voltage lockout UVLO1 detects whether the VDDQ provided by the voltage regulator chip U8 is lower than 1.1V. If VDDQ is lower than 1.1V, it outputs a low level. The under-voltage lockout UVLO2 detects whether the VPP provided by the voltage regulator chip U7 is lower than 2.25V. If VPP is lower than 2.25V, it outputs a low level. The results output by the under-voltage lockout UVLO1 and the under-voltage lockout UVLO2 are output through the dual-input AND gate AND1. If VDDQ and VPP are normal, that is, both the under-voltage lockout UVLO1 and the under-voltage lockout UVLO2 output high levels, the AND gate AND1 outputs a high level. At the same time, to meet the timing control requirements, the MCU outputs an ENABLE signal to the AND gate AND2 to control the operation amplifier to turn on. That is, when the AND1 outputs a high level and the MCU outputs an ENABLE signal is also a high level, the operation amplifier turns on.

[0103] The 0.6V power supply voltage output by the voltage regulator chip U8 is input to the inverting input terminal of the operational amplifier through the delay device Delay1, and VDDQ is input to the non-inverting input terminal of the operational amplifier. After the operational amplifier is turned on, the operational amplifier outputs VDDQ to the voltage regulator chip U8, and the voltage regulator chip U8 Figure 13 The LDO module shown outputs a matching voltage VTT of 0.6V and a maximum power supply current of 6A to the DDR4 chip by the voltage regulator chip U8. At the same time, the VTT output by the voltage regulator chip U8 is also input to the inverting input terminal of the operational amplifier through the delay device Delay1 to form a feedback circuit. This application uses the under-voltage lockout UVLO3 and the under-voltage lockout UV LO4 to detect the matching voltage VTT to prevent overvoltage or undervoltage of the matching voltage VTT. The third reference voltage is set to 1.2×VTT, that is, 0.72V, and the fourth reference voltage is set to 0.8×VTT, that is, 0.48V. The results output by the under-voltage lockout UVLO3 and the under-voltage lockout UVLO4 are output through the dual-input AND gate AND3. If VTT is normal, the AND gate AND3 outputs a high level and outputs it to the MCU through the delay device Delay2 as the Power good signal of the MCU. All the voltage regulator chips use domestic chips.

[0104] Furthermore, the Ethernet switching device further includes a NOR Flash chip, a NAND Flash chip, and an IIC expansion chip connected to the Switch unit.

[0105] Specifically, as Figure 14 shown, the Ethernet switching device uses a total of three types of control buses, namely SMI, IIC, and SFC. The Switch chip manages the PHY chip and the QSGMII PHY chip through the SMI bus to achieve the switching function. The IIC bus is used to connect the IIC expansion chip and the EEPROM (Electrically Erasable Programmable read only memory). The IIC expansion chip is used to connect the RTC clock, the optical module, that is, the SFP / SFP+ module shown in the figure, and the temperature sensor, that is, the THERMAL module shown in the figure to read information. The Switch chip also connects the off-chip NOR Flash chip and the NAND Flash chip through the SFC bus.

[0106] Figure 15The specific connection method between the Switch chip and the PHY chip is shown. The SMI interface of the Switch chip is connected to the SMI interface of the PHY chip through the SMI bus, and the PHY chip is managed through the SMI interface of the PHY chip. From the above description, it can be seen that each PHY chip can provide 8 network ports, and each network port is connected to the RJ45 interface through a signal transformer. At the same time, each PHY chip also provides a serial LED signal, and the serial LED signal is converted into a parallel LED signal through a serial-to-parallel conversion chip of model 74HC164 to indicate the working status of each network port.

[0107] Furthermore, the Ethernet switching module further includes a connection module, and the connection module includes a connector and a connection base plate. The Ethernet switching module is connected to the connection base plate through the connector, where,

[0108] the connection base plate includes a plurality of RJ45 interfaces, a plurality of SFP+ sockets, and a plurality of signal transformers corresponding one-to-one to the RJ45 interfaces.

[0109] As Figure 16 shown, the Ethernet switching module does not set physical interfaces, but sets physical interfaces on the connection panel for transmitting MDI signals, SerDes signals (corresponding to Figure 16 the 10GBase-R signal and QSGMII signal in

[0110] ), SMI signals, IIC signals, LED signals, and UART signals. The Ethernet switching module is connected to the connection panel through the connector, and the connector can be a pin header and female header, that is, the Ethernet switching module is connected to the connection base plate through the pin header and female header to facilitate the installation and disassembly of the Ethernet switching module. Specifically in implementation, the form of the connector can be flexibly selected according to actual needs.

[0111] The Ethernet switching device is also provided with a reset module. The reset module includes a first reset chip connected to the single-chip microcomputer and a second reset chip connected to the Switch chip. The model of the reset chip can be CN8090S. After the MCU is powered on, the first reset chip provides a reset signal for the MCU. After the MCU is initialized and started, it controls the PHY chip and the Switch chip to be powered on. After the PHY chip and the Switch chip are powered on, the second reset chip provides a reset signal for the Switch chip, and then the Switch chip controls the PHY chip, the RTC clock chip, and the IIC expansion chip to be reset. At the same time, to facilitate the reset of the Switch chip, a reset button, namely BUTTON shown in the figure, is connected to the second reset chip to actively control the second reset chip to provide a reset signal for the Switch chip.

[0112] The MCU, Switch chip, and PHY chip have relatively high requirements for the power supply voltage ripple value and noise value. Therefore, power input filter circuits are provided in the peripheral circuits of the MCU, Switch chip, and PHY chip. Each power input filter circuit is provided with a plurality of decoupling capacitors, and the plurality of decoupling capacitors need to be designed by combining low-frequency filter capacitors and high-frequency filter capacitors to filter out high-frequency noise and low-frequency noise at the same time. The low-frequency filter capacitor can be a ceramic capacitor with a relatively large capacitance value. This type of capacitor has a large energy storage capacity, a large package, and a low resonance frequency. This type of filter capacitor is usually placed around the chip, within a distance of no more than 1 cm from the pad. Generally, ceramic capacitors with small ESR values such as 10 μF, 22 μF, or 47 μF are selected. In this embodiment, 10 μF, 22 μF, and 47 μF capacitors are combined and used as the low-frequency filter capacitors. The high-frequency filter capacitor is a ceramic capacitor with a small capacitance value and a small package (0402 specification and below). This type of capacitor has a fast frequency response and small ERS and is used to filter out high-frequency noise. The decoupling capacitors are placed as close as possible to the pins to reduce the influence of parasitic parameters caused by the wiring. Since this device is applied to an industrial-grade usage environment, in order to prevent low-temperature crystallization and short circuit, capacitors with a 0201 package specification cannot be selected. In this embodiment, 0.1 μF and 0.01 μF ceramic capacitors with a 0402 package specification are combined and used as the high-frequency filter capacitors.

[0113] The power input filter circuit of the MCU includes capacitors C46, C47, 48, and C50 connected in parallel. One end of capacitors C46, C47, 48, and C50 is grounded, and the other end is connected to the output end of the voltage regulator chip U1 and the power input end of the MCU. In this embodiment, the capacitance values of capacitors C47 and 48 are both 0.1 μF, the capacitance value of capacitor C46 is 47 μF, and the capacitance value of capacitor C50 is 22 μF, filtering out high-frequency noise and low-frequency noise at the same time to achieve the decoupling effect of high-frequency noise and low-frequency noise.

[0114] The PHY chip of model NF1008 is provided with multiple power input pins, including AVDDL pin, DVDDL pin, SVDDL pin, AVDDH pin, DVDDIO pin, PLLVDDL pin and SVDDH pin. The above multiple power input pins need to be filtered for power input respectively.

[0115] The power input filter circuit of the SVDDL pin is as Figure 18 shown. The output terminal of the voltage regulator chip U4 is grounded through the capacitor C342 and connected to one end of the capacitor C343 through the bead FB12. The capacitors C344, C345, C346, C347, C348, C349 and C350 are connected in parallel with the capacitor C343. The capacitance values of the capacitors C342, C346, C347 and C348 are 0.1 μF, the capacitance value of the capacitor C343 is 47 μF, the capacitance values of the capacitors C344 and C345 are 4.7 μF, and the capacitance values of the capacitors C349 and C350 are 100 pF.

[0116] The power input filter circuit of the SVDDH pin is as Figure 19 shown. The output terminal of the voltage regulator chip U6 is grounded through the capacitor C364 and connected to one end of the capacitor C365 through the bead FB14. The capacitors C366 and C367 are connected in parallel with the capacitor C365. The capacitance values of the capacitors C364 and C367 are 0.1 μF, the capacitance value of the capacitor C365 is 10 μF, and the capacitance value of the capacitor C366 is 100 pF. The power input filter circuit of the PLLVDDL pin is as Figure 20 shown. The output terminal of the voltage regulator chip U4 is grounded through the capacitor C397 and connected to one end of the capacitor C398 through the bead FB17. The capacitors C399 and C400 are connected in parallel with the capacitor C398. The capacitance values of the capacitors C397 and C3400 are 0.1 μF, the capacitance value of the capacitor C398 is 1000 pF, and the capacitance value of the capacitor C399 is 2.2 μF.

[0117] The power input filter circuit of the AVDDH pin is as Figure 21As shown, the output terminal of the voltage regulator chip U6 is grounded through the capacitor C351 and connected to one end of the capacitor C354 through the bead FB13. The capacitors C352 and C353 are in parallel with the capacitor C351. The capacitors C354, C355, C356, C357, C358, C359, C360, C361, C362, and C363 are in parallel with the capacitor C354. The capacitance values of the capacitors C351, C352, and C354 are 47 μF. The capacitance values of the capacitors C353, C361, C362, and C363 are 0.1 μF. The capacitance values of the capacitors C355, C356, C357, C358, C359, and C360 are 1 μF.

[0118] The power input filtering circuit of the DVDDIO pin is as Figure 22 As shown, the output terminal of the voltage regulator chip U6 is grounded through the capacitor C368 and connected to one end of the capacitor C369 through the bead FB15. The capacitors C369, C370, C371, and C372 are in parallel with the capacitor C369. The capacitance values of the capacitors C368, C370, C371, and C372 are 0.1 μF. The capacitance value of the capacitor C369 is 10 μF.

[0119] The power input filtering circuit of the AVDDL pin is as Figure 23 As shown, the output terminal of the voltage regulator chip U4 is grounded through the capacitor C382 and connected to one end of the capacitor C385 through the bead FB16. The capacitors C383 and C384 are in parallel with the capacitor C382. The capacitors C386, C387, C388, C389, C390, C391, C392, C393, C394, C395, and C396 are in parallel with the capacitor C385. The capacitance values of the capacitors C382, C383, C385, and C386 are 47 μF. The capacitance values of the capacitors C384, C393, C394, C395, and C396 are 0.1 μF. The capacitance values of the capacitors C387, C388, C389, C390, C391, and C392 are 1 μF.

[0120] The power input filtering circuit of the DVDDL pin is as Figure 24As shown, the output end of the voltage regulator chip U4 is grounded through capacitor C401 and connected to one end of capacitor C402 through magnetic bead FB18. Capacitors C403, C404, C405 and C406 are connected in parallel with capacitor C402. The capacitance of capacitors C401, C405 and C406 is 0.1μF, the capacitance of capacitor C402 is 4.7μF, and the capacitance of capacitors C403 and C404 is 1μF. The form of the power input filter circuit of the Switch chip can be consistent with the prior art.

[0121] The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A highly reliable Ethernet switching device, characterized in that, Comprising: An Ethernet switch module, including a microprocessing unit, a Switch unit, and a group of PHY units. Among them, The microprocessing unit and the Switch unit each include at least one UART interface. The UART interface of the Switch unit is connected to the UART interface of the microprocessing unit. The group of PHY units includes multiple PHY units adaptively connected to the Switch unit; A power supply module, including a group of voltage conversion units. The power supply module supplies power to the microprocessing unit, the Switch unit, and multiple PHY units through the group of voltage conversion units based on a power supply timing sequence.

2. The highly reliable Ethernet switching device according to claim 1, wherein The Switch unit includes a Switch chip of model NF5120. The Switch chip includes a SerDes0 interface and a SerDes1 interface, and both the SerDes0 interface and the SerDes1 interface are configured in the QSGMII mode; Both the SerDes0 interface and the SerDes1 interface are connected to the first PHY unit in the group of PHY units, and each of the SerDes0 interface and the SerDes1 interface is connected to a signal switching unit.

3. The highly reliable Ethernet switching device according to claim 2, characterized in that, The signal switching unit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a diode D1, a diode D2, an NPN transistor Q1, and an NMOS transistor Q2. Among them, The microprocessing unit is connected to one end of the resistor R1, one end of the resistor R2, and the base of the NPN transistor Q1. The other end of the resistor R2 is grounded. The collector of the NPN transistor Q1 is connected to one end of the resistor R3 and one end of the capacitor C1. The other end of the resistor R3 is connected to the positive electrode of the diode D1. The other end of the capacitor C1 is connected to the negative electrode of the diode D1; The positive electrode of the diode D2 is connected to the negative electrode of the diode D1. The negative electrode of the diode D2 is connected to one end of the capacitor C2 and one end of the resistor R4. The other end of the resistor R4 is connected to the gate of the NMOS transistor Q2. The other end of the capacitor C2 is grounded. The other end of the resistor R4 is grounded through the resistor R5.

4. The highly reliable Ethernet switching device according to claim 3, wherein The group of voltage conversion units includes a voltage regulator chip U1, a voltage regulator chip U2, a voltage regulator chip U3, a voltage regulator chip U4, a voltage regulator chip U5, a voltage regulator chip U6, and a voltage regulator chip U7. Among them, The input terminals of the voltage regulator chip U1, the voltage regulator chip U2, the voltage regulator chip U3, the voltage regulator chip U4, the voltage regulator chip U5, the voltage regulator chip U6, and the voltage regulator chip U7 are all connected to the power supply voltage VCC; The voltage regulator chip U1 is used to provide the required operating voltage for the microprocessing unit; The voltage regulator chips U2, U3, U5, and U6 are used to provide the required operating voltage for the Switch unit.

5. The highly reliable Ethernet switching device according to claim 4, wherein The power supply module further includes a delay unit. The delay unit includes a first delay sub-unit, a second delay sub-unit, a third delay sub-unit, and a fourth delay sub-unit. Among them, The first delay sub-unit includes resistor R426, resistor R443, resistor R444, resistor R445, resistor R446, capacitor C492, capacitor C493, NPN transistor Q15, and NPN transistor Q16; The output terminal of the voltage regulator chip U2 is connected to one end of capacitor C492 and the base of NPN transistor Q16 through resistor R446. The other end of capacitor C492 and the emitter of NPN transistor Q16 are grounded. The output terminal of the voltage regulator chip U1 is connected to one end of resistor R445 and resistor R426. The other end of resistor R445 is connected to the base of NPN transistor Q15 through resistor R443. The other end of resistor R426 is connected to the collector of NPN transistor Q15 and is connected to the voltage regulator chip U3 through resistor R444. One end of capacitor C493 is connected to the base of NPN transistor Q15, and the other end of capacitor C493 is grounded.

6. The highly reliable Ethernet switching device according to claim 5, characterized in that, The second delay sub-unit includes resistor R427, resistor R428, resistor R429, resistor R430, resistor R431, resistor R432, capacitor C486, capacitor C487, NPN transistor Q19, and NPN transistor Q10; The output terminal of the voltage regulator chip U2 is connected to one end of capacitor C487 and the base of NPN transistor Q10 through resistor R431. The output terminal of the voltage regulator chip U3 is connected to one end of capacitor C487 and the base of NPN transistor Q10 through resistor R432; The other end of capacitor C487 and the emitter of NPN transistor Q10 are grounded. The output terminal of the voltage regulator chip U1 is connected to one end of resistor R429 and resistor R427. The other end of resistor R429 is connected to the base of NPN transistor Q9 through resistor R428. The other end of resistor R427 is connected to the collector of NPN transistor Q9 and is connected to the voltage regulator chip U4 through resistor R430. One end of capacitor C486 is connected to the base of NPN transistor Q9, and the other end of capacitor C486 is grounded.

7. The highly reliable Ethernet switching device according to claim 5, wherein The third delay sub-unit includes resistor R433, resistor R434, resistor R435, resistor R436, resistor R437, capacitor C488, capacitor C489, NPN transistor Q11, and NPN transistor Q12; The output terminal of the voltage regulator chip U3 is connected to one end of capacitor C488 and the base of NPN transistor Q12 through resistor R437. The other end of capacitor C488 and the emitter of NPN transistor Q12 are grounded. The output terminal of the voltage regulator chip U1 is connected to one end of resistor R436 and resistor R433. The other end of resistor R436 is connected to the base of NPN transistor Q11 through resistor R435. The other end of resistor R433 is connected to the collector of NPN transistor Q11 and is connected to the voltage regulator chip U5 through resistor R434. One end of capacitor C489 is connected to the base of NPN transistor Q11, and the other end of capacitor C489 is grounded; The fourth delay sub-unit includes a resistor R438, a resistor R439, a resistor R440, a resistor R441, a resistor R442, a capacitor C490, a capacitor C491, an NPN transistor Q13, and an NPN transistor Q14; The output terminal of the voltage-regulating chip U5 is connected to one end of the capacitor C491 and the base of the NPN transistor Q14 through the resistor R442. The other end of the capacitor C491 and the emitter of the NPN transistor Q14 are grounded. The output terminal of the voltage-regulating chip U1 is connected to one end of the resistor R440 and the resistor R438. The other end of the resistor R440 is connected to the base of the NPN transistor Q13 through the resistor R439. The other end of the resistor R438 is connected to the collector of the NPN transistor Q13 and is connected to the voltage-regulating chip U6 through the resistor R441. One end of the capacitor C490 is connected to the base of the NPN transistor Q13, and the other end of the capacitor C490 is grounded.

8. The highly reliable Ethernet switching device according to claim 4, wherein The Ethernet switching device further includes a DDR4 chip connected to the Switch unit, and the power supply module further includes a DDR4 power supply unit; The DDR4 power supply unit includes an operational amplifier, an under-voltage lockout UVLO1, an under-voltage lockout UVLO2, an AND gate AND1, an AND gate AND2, and a voltage-regulating chip U8, where The output terminal of the voltage-regulating chip U3 is connected to the first input terminal of the under-voltage lockout UVLO1 and the non-inverting input terminal of the operational amplifier. The second input terminal of the under-voltage lockout UVLO1 is connected to a first reference voltage. The output terminal of the under-voltage lockout UVLO1 is connected to the first input terminal of the AND gate AND1; The output terminal of the voltage-regulating chip U7 is connected to the first input terminal of the under-voltage lockout UVLO2. The second input terminal of the under-voltage lockout UVLO2 is connected to a second reference voltage. The output terminal of the under-voltage lockout UVLO2 is connected to the second input terminal of the AND gate AND1; The output terminal of the AND gate AND1 is connected to the first input terminal of the AND gate AND2. The second input terminal of the AND gate AND2 is connected to the microprocessing unit. The output terminal of the AND gate AND2 is connected to the positive power supply terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the second input terminal of the voltage-regulating chip U8. The second output terminal of the voltage-regulating chip U8 is connected to the DDR4 chip.

9. The highly reliable Ethernet switching device according to claim 8, wherein The DDR4 power supply unit further includes a delay unit Delay1, a delay unit Delay2, an under-voltage lockout UVLO3, an under-voltage lockout UVLO4, and an AND gate AND3, where The second output terminal of the voltage-regulating chip U8 is connected to the input terminal of the delay unit Delay1. The output terminal of the delay unit Delay1 is connected to the first input terminal of the under-voltage lockout UVLO3, the first input terminal of the under-voltage lockout UVLO4, and the inverting input terminal of the operational amplifier. The second input terminal of the under-voltage lockout UVLO3 is connected to a third reference voltage. The second input terminal of the under-voltage lockout UVLO4 is connected to a fourth reference voltage; The output terminal of the undervoltage lockout UVLO3 is connected to the first input terminal of the AND gate AND3. The output terminal of the undervoltage lockout UVLO4 is connected to the second input terminal of the AND gate AND3. The output terminal of the AND gate AND3 is connected to the negative power supply terminal of the operational amplifier and the input terminal of the delay unit Delay2. The output terminal of the delay unit Delay2 is connected to the microprocessing unit.

10. The highly reliable Ethernet switching device according to claim 1, characterized in that, It further includes a connection module. The connection module includes a connector and a connection base plate. The Ethernet switching module is connected to the connection base plate through the connector. Among them, the connection base plate includes a plurality of RJ45 interfaces, a plurality of SFP+ sockets, and a plurality of signal transformers corresponding to the RJ45 interfaces one by one.

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