LED video processor

Abstract

The utility model provides an LED video processor, comprising a video processing circuit used for video zooming and video windowing, an FPGA bridge circuit used for video cutting and video rotation, an MCU control circuit and a sending card circuit, the MCU control circuit is respectively connected with the video processing circuit, the FPGA bridge circuit and the sending card circuit; the input end of the video processing circuit is connected with at least one video input interface, and the output end of the video processing circuit is connected with the FPGA bridging circuit through the multi-path LVDS interface; the FPGA bridge circuit comprises a first FPGA chip and a plurality of first PSRAMs, the input end of the first FPGA chip is connected with the LVDS interface, the input end of the first FPGA chip is connected with the first PSRAM, and the output end of the first PSRAM is connected with the sending card circuit; the sending card circuit comprises at least one second FPGA chip, a plurality of second PSRAMs and a plurality of PHY chips which are connected in sequence. According to the utility model, the core function of video processing is dispersed to the video processing circuit and the FPGA bridge circuit, so that the performance requirement on a video processing chip is reduced, and the cost is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of display screens, and particularly relates to an LED video processor. Background Art

[0002] With the development of LED display technology, the LED video processor market is developing towards diversification and personalization. For LED display screens with different resolutions and structures, the functional requirements for LED video processors are also increasing.

[0003] Existing LED video processors usually use FPGAs to complete all core functions of video processing, which requires extremely high FPGA performance and results in a substantial increase in cost. Summary of the Utility Model

[0004] The utility model provides an LED video processor to solve the defect that existing LED video processors usually use FPGAs to complete all core functions of video processing, which requires extremely high FPGA performance and results in a substantial increase in cost.

[0005] The utility model provides an LED video processor, which includes a video processing circuit for video scaling and video windowing, an FPGA bridging circuit for video cutting and video rotation, an MCU control circuit, and a sending card circuit. The MCU control circuit is respectively connected to the video processing circuit, the FPGA bridging circuit, and the sending card circuit. The input end of the video processing circuit is connected to at least one video input interface, and the output end is connected to the FPGA bridging circuit through a multi-channel LVDS interface. The FPGA bridging circuit includes a first FPGA chip and multiple first PSRAMs. The input end of the first FPGA chip is connected to the LVDS interface, the input end of the first FPGA chip is connected to the first PSRAM, and the output end of the first PSRAM is connected to the sending card circuit. The sending card circuit includes at least one second FPGA chip, multiple second PSRAMs, and multiple PHY chips. The second FPGA chip, the second PSRAM, and the PHY chip are connected in sequence. The output end of the sending card circuit is also connected to several network transformers and a video output interface.

[0006] Preferably, the video input interface includes HDMI, DVI, VGA, and DP interfaces, and the video processing circuit is also connected to an AUDIO audio input and output interface.

[0007] Preferably, the FPGA bridging circuit includes a first FPGA chip and four first PSRAMs. Two of the first PSRAMs form a group, and all the first PSRAMs form a ping-pong structure.

[0008] Preferably, the first PSRAM outputs video data to the sending card circuit based on the RGB24 interface.

[0009] Preferably, the MCU control circuit is connected to an external control device based on a USB interface or an RJ45 interface.

[0010] Preferably, the MCU control circuit is also provided with a USB interface for cascading the LED video processor.

[0011] Preferably, the MCU control circuit is also connected to a matrix keyboard and an LCD display screen.

[0012] Preferably, the sending card circuit includes at least one second FPGA chip, four second PSRAMs, and four PHY chips. The second PSRAMs send video data to the PHY chips based on four RGM interfaces, and the PHY chips output to the video output interface through the network transformers.

[0013] Preferably, the video output interface is an RJ45 interface.

[0014] The LED video processor provided by the present utility model includes a video processing circuit for video scaling and video windowing, an FPGA bridging circuit for video cutting and video rotation, an MCU control circuit, and a sending card circuit. The MCU control circuit is respectively connected to the video processing circuit, the FPGA bridging circuit, and the sending card circuit. The input end of the video processing circuit is connected to at least one video input interface, and the output end is connected to the FPGA bridging circuit through a plurality of LVDS interfaces; the FPGA bridging circuit includes a first FPGA chip and a plurality of first PSRAMs. The input end of the first FPGA chip is connected to the LVDS interface, the input end of the first FPGA chip is connected to the first PSRAM, and the output end of the first PSRAM is connected to the sending card circuit; the sending card circuit includes at least one second FPGA chip, a plurality of second PSRAMs, and a plurality of PHY chips. The second FPGA chip, the second PSRAMs, and the PHY chips are connected in sequence, and the output end of the sending card circuit is also connected to a plurality of network transformers and a video output interface. The present utility model disperses the core functions of video processing into the video processing circuit and the FPGA bridging circuit, reducing the performance requirements for the video processing chip and reducing costs. Description of the Drawings

[0015] To more clearly illustrate the technical solutions in the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0016] Figure 1 It is the principle block diagram of the LED video processor provided by the present utility model.

[0017] Figure 2 It is the circuit schematic diagram of the LED video processor provided by the present utility model.

[0018] Figure 3 It is the circuit schematic diagram of the EG4S20BG256 chip provided by the present utility model.

[0019] Figure 4a It is one of the circuit schematic diagrams of the power supply circuit provided by the present utility model. Figure 4b It is the second circuit schematic diagram of the power supply circuit provided by the present utility model.

[0020] Figure 5a It is one of the circuit schematic diagrams of the MCU control circuit provided by the present utility model. Figure 5b It is the second circuit schematic diagram of the MCU control circuit provided by the present utility model.

[0021] In the figure, 1 - video processing circuit, 2 - FPGA bridging circuit, 3 - MCU control circuit, 4 - sending card circuit. Detailed implementation manners

[0022] To make the purpose, technical solutions and advantages of the present utility model clearer, the following will clearly and completely describe the technical solutions in the present utility model in conjunction with the drawings in the present utility model. Obviously, the described embodiments are some embodiments of the present utility model, rather than all embodiments. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present utility model.

[0023] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0024] Figure 1 is the principle block diagram of the LED video processor provided by the present utility model. Figure 2 is the circuit schematic diagram of the LED video processor provided by the present utility model. As Figure 1 Figure 2 shown, the present utility model provides an LED video processor, which includes a video processing circuit 1 for video scaling and video windowing, an FPGA bridging circuit 2 for video cutting and video rotation, an MCU control circuit 3, and a sending card circuit 4. The MCU control circuit 3 is respectively connected to the video processing circuit 1, the FPGA bridging circuit 2, and the sending card circuit 4. The input end of the video processing circuit 1 is connected to at least one video input interface, and the output end is connected to the FPGA bridging circuit 2 through a plurality of LVDS interfaces; the FPGA bridging circuit 2 includes a first FPGA chip and multiple first PSRAMs. The input end of the first FPGA chip is connected to the LVDS interface, the input end of the first FPGA chip is connected to the first PSRAM, and the output end of the first PSRAM is connected to the sending card circuit 4; the sending card circuit 4 includes at least one second FPGA chip, multiple second PSRAMs, and multiple PHY chips. The second FPGA chip, the second PSRAM, and the PHY chip are connected in sequence. The output end of the sending card circuit 4 is also connected with a plurality of network transformers and a video output interface.

[0025] Preferably, the video input interface includes HDMI\DVI\VGA\DP interfaces, and the video processing circuit 1 is also connected with an AUDIO audio input and output interface.

[0026] Preferably, the FPGA bridging circuit 2 includes a first FPGA chip and four first PSRAMs. Two of the first PSRAMs are in a group, and all the first PSRAMs form a ping-pong structure.

[0027] Preferably, the first PSRAM outputs video data to the sending card circuit 4 based on the RGB24 interface.

[0028] Preferably, the MCU control circuit 3 is connected to an external control device based on a USB interface or an RJ45 interface.

[0029] Preferably, the MCU control circuit 3 is also provided with a USB interface for cascading the LED video processor.

[0030] Preferably, the MCU control circuit 3 is also connected to a matrix keyboard and an LCD display screen.

[0031] Preferably, the sending card circuit 4 includes at least one second FPGA chip, four second PSRAMs, and four PHY chips. The second PSRAMs send video data to the PHY chips based on four RGM interfaces, and the PHY chips output to the video output interface through the network transformer.

[0032] Preferably, the video output interface is an RJ45 interface.

[0033] The present utility model designs a two-in-one LED video processor, which incorporates the functions of video processing and an LED sending card. The sending card circuit 4 is built using a core board module, making the application more flexible and reducing the R & D cycle.

[0034] The video processing circuit 1 can be composed of an MST9104QT chip. MST9104QT is a high-quality video scaling and windowing video processing chip that supports multiple video input interfaces such as HDMI, DVI, VGA, and DP, and also supports AUDIO audio input and output interfaces, meeting the application requirements of most interfaces in the market. It outputs 4 LVDS interfaces and can support up to 1920*1080@144Hz.

[0035] The FPGA bridging circuit 2 can be composed of an EG4S20BG256 chip from Anlu. The FPGA bridging circuit 2 has approximately 20K of logic resources and a relatively low price. The EG4S20BG256 chip is mainly composed of one FPGA and 4 PSRAMs (two in a group, divided into two groups, and the two groups of PSRAMs are used in parallel to form a ping-pong structure for caching the received image data). The main function of the FPGA bridging circuit 2 is to process and segment the video data input by the MST9104QT chip through the LVDS interface, and then send it to the sending card circuit 4 through the RGB24 interface.

[0036] Figure 3 is the circuit schematic diagram of the EG4S20BG256 chip provided by the present utility model, as Figure 3As shown, the sending card circuit 4 can use the EG4S20BG256 chip of Anlu, which is mainly composed of FPGA, 4 PSRAMs and 4 PHY chips. The basic principle of the core board of the sending card circuit 4 is that the image data is sent to the FPGA through the RGB24 interface, and the FPGA processes the image data, and then sends the video data to the PHY chip through the 4-way RGM interface, and then the PHY chip sends the display data out.

[0037] Figure 4a This is one of the circuit diagrams of the power supply circuit provided by the utility model. Figure 4b This is the second circuit diagram of the power supply circuit provided by the utility model, such as Figure 4a and Figure 4b As shown, the utility model also includes a power module, which supplies power to the video processing circuit 1, the FPGA bridge circuit 2, the MCU control circuit 3, and the sending card circuit 4 respectively.

[0038] Figure 5a This is one of the circuit diagrams of the MCU control circuit provided by the utility model. Figure 5b This is the second circuit diagram of the MCU control circuit provided by the utility model, such as Figure 5a and Figure 5b As shown, the MCU control circuit 3 can use the AT32F407VGT7 model of Artly. The module is connected to the external PC via USB or RJ45, and the PC software sends commands and various control signals to the video processor. A new USB interface is also added for cascading between video processors. The MCU control circuit 3 controls each module of the video processor, and can be connected to a matrix keyboard and an LCD display externally. It can independently control the configuration of related commands to achieve various customized functions.

[0039] In summary, the advantage of the utility model is that the core processing uses the MST9104QT chip, which is responsible for important functions such as video scaling and windowing, and the FPGA bridge circuit 2 is only responsible for auxiliary functions such as video cutting and rotation, which reduces the resource requirements of the FPGA. Since the FPGA performance resource requirements are reduced, a lower-cost FPGA can be selected, thereby reducing the overall BOM cost and improving market competitiveness. High-speed memory chips such as DDR are required, the PCB circuit design is simplified, the number of layers required is reduced, and the PCB cost is reduced. FPGA does not need to implement complex algorithms, shortens the software development cycle, and can respond to market demand more quickly.

[0040] It should be noted that the present invention only improves the circuit structure and connection relationship, and the core functions of the video processing mentioned are all existing technologies and will not be described in detail.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An LED video processor, characterized in that, It includes a video processing circuit for video scaling and video windowing, an FPGA bridging circuit for video cutting and video rotation, an MCU control circuit, and a sending card circuit. The MCU control circuit is respectively connected to the video processing circuit, the FPGA bridging circuit, and the sending card circuit. The input end of the video processing circuit is connected to at least one video input interface, and the output end is connected to the FPGA bridging circuit through a multi-channel LVDS interface; the FPGA bridging circuit includes a first FPGA chip and multiple first PSRAMs. The input end of the first FPGA chip is connected to the LVDS interface, the input end of the first FPGA chip is connected to the first PSRAM, and the output end of the first PSRAM is connected to the sending card circuit; the sending card circuit includes at least one second FPGA chip, multiple second PSRAMs, and multiple PHY chips. The second FPGA chip, the second PSRAM, and the PHY chip are connected in sequence, and the output end of the sending card circuit is also connected with several network transformers and a video output interface.

2. An LED video processor according to claim 1, characterized in that, The video input interface includes HDMI\DVI\VGA\DP interfaces, and the video processing circuit is also connected with an AUDIO audio input and output interface.

3. An LED video processor according to claim 1, characterized in that The FPGA bridging circuit includes a first FPGA chip and four first PSRAMs. Two of the first PSRAMs form a group, and all the first PSRAMs form a ping-pong structure.

4. An LED video processor according to claim 1 or 3, characterized in that, The first PSRAM outputs video data to the sending card circuit based on the RGB24 interface.

5. An LED video processor according to claim 1, characterized in that, The MCU control circuit is connected to an external control device based on a USB interface or an RJ45 interface.

6. An LED video processor according to claim 1 or 5, characterized in that, The MCU control circuit also has a USB interface for cascading the LED video processor.

7. An LED video processor according to claim 6, characterized in that, The MCU control circuit is also connected with a matrix keyboard and an LCD display screen.

8. An LED video processor according to claim 1, wherein, The sending card circuit includes at least one second FPGA chip, four second PSRAMs, and four PHY chips. The second PSRAM sends video data to the PHY chip based on a four-way RGM interface, and the PHY chip outputs to the video output interface through the network transformer.

9. An LED video processor according to claim 8, characterized in that, The video output interface is an RJ45 interface.

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