Semiconductor structure and display device

Abstract

The utility model relates to the technical field of display, in particular to a semiconductor structure and a display device. The semiconductor structure includes: a substrate; the multiple light-emitting structures are arranged on one side of the substrate at intervals; the electrode layer comprises a first grid electrode, a first electrode and a second electrode, the first grid electrode extends along the side wall of the light-emitting structure, the first electrode is located on the substrate between the adjacent light-emitting structures, the second electrode is located on the surface, away from the substrate, of the light-emitting structure, one of the first electrode and the second electrode is the source electrode of the first transistor, and the other electrode is the drain electrode of the second transistor. The other transistor is a drain electrode of the first transistor; the active layer is located between the electrode layer and the light-emitting structure and covers the light-emitting structure and the substrate, and the first electrode and the second electrode are connected with the active layer. The first transistor is formed on one side of the light-emitting structure, so that when the display device is prepared, the first transistor does not need to be prepared on the driving substrate, and the preparation process complexity of the driving substrate is simplified.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a semiconductor structure and a display device. Background Art

[0002] Currently, display devices (e.g., Micro LED micro-displays) have a series of high-performance requirements such as high pixel density per unit, high refresh rate, as many gray levels as possible, and high brightness uniformity. To meet the above requirements, thin film transistors (TFTs) are often used to drive a light-emitting structure to emit light, so as to achieve a display effect with high speed response, high brightness, and high contrast.

[0003] Correspondingly, this requires a large number of thin film transistors and suitable wiring to be provided on the driving substrate of the display device. However, this makes the manufacturing process of the driving substrate very complex. Summary of the Utility Model

[0004] Based on this, it is necessary to provide a semiconductor structure and a display device for solving the problem that the manufacturing process of the driving substrate in the prior art is very complex.

[0005] To achieve the above object, on the one hand, a semiconductor structure is provided, including:

[0006] A substrate;

[0007] A light-emitting structure, with a plurality of the light-emitting structures arranged at intervals on one side of the substrate;

[0008] An electrode layer, including a first gate, a first electrode, and a second electrode, the first gate extending along the sidewall of the light-emitting structure, the first electrode being located on the substrate between adjacent light-emitting structures, the second electrode being located on the surface of the light-emitting structure away from the substrate, and one of the first electrode and the second electrode being the source electrode of a first transistor, and the other being the drain electrode of the first transistor;

[0009] An active layer, located between the electrode layer and the light-emitting structure, covering the light-emitting structure and the substrate, and the first electrode and the second electrode are connected to the active layer.

[0010] In one embodiment, the first electrode and / or the first gate is in a ring shape.

[0011] In one embodiment, the first gate extends from the sidewall of the light-emitting structure to the substrate between adjacent light-emitting structures and the surface of the light-emitting structure away from the substrate respectively on both sides;

[0012] The semiconductor structure further includes:

[0013] The first bit line interconnection structure is located on the surface of the second electrode away from the substrate.

[0014] The first word line interconnection structure is located on the surface of the first gate between adjacent light-emitting structures away from the substrate.

[0015] In one embodiment, the electrode layer further includes a second gate, a third electrode, and a fourth electrode located between adjacent light-emitting structures. The second gate is connected to the first electrode, the third electrode and the fourth electrode are connected to the active layer, and one of the third electrode and the fourth electrode is the source electrode of the second transistor, and the other is the drain electrode of the second transistor.

[0016] In one embodiment, in the first direction, the second gate is connected to the first electrode, and in the second direction, the third electrode and the fourth electrode are respectively located on both sides of the second gate, and the first direction intersects with the second direction.

[0017] In one embodiment, the light-emitting structure includes a stacked N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer. The N-type semiconductor layer is located on the substrate, the light-emitting layer is located on the N-type semiconductor layer, and the P-type semiconductor layer is located on the light-emitting layer.

[0018] In one embodiment, the semiconductor structure includes:

[0019] A transparent conductive layer, located on the side of the P-type semiconductor layer away from the substrate.

[0020] In one embodiment, the semiconductor structure includes:

[0021] An interlayer dielectric layer, located on the side of the light-emitting structure away from the substrate.

[0022] In one embodiment, the semiconductor structure includes:

[0023] A first device electrode, located on the side of the light-emitting structure away from the substrate, and the first device electrode penetrates through the interlayer dielectric layer;

[0024] A barrier layer, located between the first device electrode and the interlayer dielectric layer.

[0025] On the one hand, a display device is provided, including:

[0026] A driving substrate;

[0027] Light-emitting structures, and a plurality of the light-emitting structures are arranged at intervals on one side of the driving substrate;

[0028] The electrode layer includes a first gate, a first electrode, and a second electrode. The first gate extends along the sidewall of the light-emitting structure. The first electrode is located between adjacent light-emitting structures, and the second electrode is located on the surface of the light-emitting structure close to the driving substrate.

[0029] The active layer is located between the first gate and the light-emitting structure. The first electrode and the second electrode are connected to the active layer. One of the first electrode and the second electrode is the source electrode of the first transistor, and the other is the drain electrode of the first transistor.

[0030] The semiconductor structure and the display device of this specification have the following beneficial effects: By forming the first gate on the sidewall of the light-emitting structure, forming the first source electrode on the active layer between adjacent light-emitting structures, and forming the first drain electrode on the surface of the light-emitting structure away from the substrate, the first transistor can be formed on one side of the light-emitting structure. Further, when manufacturing the display device, there is no need to manufacture the first transistor on the driving substrate, which simplifies the manufacturing process complexity of the driving substrate. Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 It is a flowchart of a manufacturing method of a semiconductor structure provided in an embodiment.

[0033] Figures 2 to 8 It is a cross-sectional view of an intermediate structure obtained by the manufacturing methods of semiconductor structures provided in different embodiments.

[0034] Figures 9 to 14 It is a top view of an intermediate structure obtained by the manufacturing methods of semiconductor structures provided in different embodiments.

[0035] Figure 15 It is a schematic diagram of an SN junction provided in an embodiment.

[0036] Figure 16 It is a flowchart of a manufacturing method of a display device provided in an embodiment.

[0037] Description of reference numerals: semiconductor structure 100; substrate 110; light emitting structure 120; N-type semiconductor layer 121; light emitting layer 122; P-type semiconductor layer 123; active layer 130; electrode layer 140; first gate 141; first electrode 142; second electrode 143; second gate 144; third electrode 145; fourth electrode 146; interlayer dielectric layer 150; gate dielectric layer 160; planarization dielectric layer 161; 170; first device electrode-180; first word line interconnection structure-181; first bit line interconnection structure-182; channel opening-200; first opening-210; second opening-220; third opening-230; fourth opening-240; first through hole-250; second through hole-260; third through hole-270; write word line terminal-300; write bit line terminal-310; read word line terminal-320; read bit line terminal-330; SN junction-340.

[0038] In order to better describe and illustrate the embodiments and / or examples mentioned in this specification disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed embodiments, the presently described embodiments and / or examples, and the best mode of these embodiments currently understood. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0041] In each embodiment, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in each embodiment can be understood according to the specific situation.

[0042] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" another element or layer, it can be directly on, adjacent to, or connected to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of this embodiment, the first element, component, region, layer, doping type, or portion discussed below may be denoted as the second element, component, region, layer, or portion.

[0043] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under", "beneath", or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. Additionally, the device may also have other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0044] As used herein, the singular forms "a", "an", and "the" may also include the plural, unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups are not excluded from being present or added. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0045] Embodiments of the present invention are described with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present specification. It is contemplated that variations in the shapes shown may result from, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present specification should not be limited to the specific shapes of the regions shown herein, but include shape deviations resulting from, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present embodiments.

[0046] Please refer to Figure 1 , in one embodiment, a method for preparing a semiconductor structure 100 is provided. Figures 2 to 8 A cross-sectional view of an intermediate structure obtained by the method for preparing a semiconductor structure, Figures 8 to 14 is a top view of the corresponding intermediate structure. The method for preparing a semiconductor structure 100 includes the following steps:

[0047] Step S100: Provide a substrate 110, and a plurality of spaced-apart light-emitting structures 120 are provided on one side of the substrate 110.

[0048] Step S200: Form an active layer 130 covering the light-emitting structures 120 and the substrate 110.

[0049] Step S400: Form an electrode layer 140 covering the active layer 130. The electrode layer 140 includes a first gate 141, a first electrode 142, and a second electrode 143. The first gate 141 extends along the sidewalls of the light-emitting structures 120. The first electrode 142 and the second electrode 143 are connected to the active layer 130. The first electrode 142 is located between adjacent light-emitting structures 120, and the second electrode 143 is located on the surface of the light-emitting structures 120 away from the substrate 110. One of the first electrode 142 and the second electrode 143 is the source electrode of the first transistor, and the other is the drain electrode of the first transistor.

[0050] In step S100, please refer to Figure 2 , the substrate 110 may be made of a semiconductor material, an insulating material, or any combination thereof. For example, the substrate 110 may be a silicon substrate, a silicon germanium substrate, a silicon germanium carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium arsenide substrate, an indium phosphide substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates.

[0051] The light-emitting structure 120 may include an N-type semiconductor layer 121, a light-emitting layer 122, and a P-type semiconductor layer 123. The N-type semiconductor layer 121 may be formed on a substrate 110, the light-emitting layer 122 is formed on the N-type semiconductor layer 121, and the P-type semiconductor layer 123 is formed on the light-emitting layer 122. As an example, the material of the P-type semiconductor layer 123 may include GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with P-type dopants such as Mg, Zn, Ca, Sr, Ba, etc. The material of the N-type semiconductor layer 121 may include GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with N-type dopants such as Si, Ge, Sn, etc. The N-type semiconductor layer 121, the light-emitting layer 122, and the P-type semiconductor layer 123 can all be formed by epitaxial growth. The specific form of the light-emitting structure 120 is not limited in this embodiment, that is, the light-emitting structure 120 can have a flip-chip or vertical form.

[0052] The light-emitting structure 120 can form a MESA step. For example, an N-type semiconductor material layer, a light-emitting material layer, and a P-type semiconductor material layer can be sequentially formed on one side of the substrate 110 first, and then dry etching can be used to pattern the N-type semiconductor material layer, the light-emitting material layer, and the P-type semiconductor material layer to form the light-emitting structure 120. Specifically, the dry etching includes at least any one of reactive ion etching, inductively coupled plasma etching, or high-density plasma etching.

[0053] In a possible example, the cross-sectional view of the light-emitting structure 120 can be trapezoidal, so that it can have inclined sidewalls. In another possible example, the top view of the light-emitting structure 120 can be a regular octagon, or the top view of the light-emitting structure 120 can be a rectangle or a circle, etc. In yet another possible example, please refer to Figure 9 , a plurality of light-emitting structures 120 can be formed on the substrate 110, and the plurality of light-emitting structures 120 can be arranged in an array.

[0054] In addition, a transparent conductive layer can be formed on the side of the P-type semiconductor layer 123 away from the substrate 110. Specifically, a whole-surface indium tin oxide (ITO) can be formed by electron beam evaporation, and the transparent conductive layer can form a good ohmic contact with the P-type semiconductor layer 123. Or, a nickel layer, a platinum layer, etc. can also be formed on the side of the P-type semiconductor layer 123 away from the substrate 110, and a good ohmic contact can also be formed with the P-type semiconductor layer 123.

[0055] In step S200, please refer to Figure 4, as an example, the active material layer can be formed by sputtering, and then, through steps such as exposing, developing, and etching the active material layer, the active layer 130 with the channel opening 200 can be formed, so that each transistor structure can be separated. As an example, please refer to Figure 11 , the channel opening 200 can expose the top surface of the light-emitting structure 120 away from the substrate 110.

[0056] The material of the active layer 130 can include indium gallium zinc oxide (IGZO), etc.

[0057] In addition, before forming the active layer 130, please refer to Figure 3 and Figure 10 , the interlayer dielectric layer 150 (Inter Layer Dielectric, ILD) covering the light-emitting structure 120 and the substrate 110 can be formed first. The interlayer dielectric layer 150 can protect the light-emitting structure 120 from being damaged in subsequent processes. The interlayer dielectric layer 150 can be formed by means such as plasma-enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), and the material of the interlayer dielectric layer 150 can include silicon oxide, etc.

[0058] In step S400, please refer to Figure 6 , for example, the electrode material layer can be formed by chemical vapor deposition or physical vapor deposition or sputtering, and the material of the electrode material layer can include metal materials. Then, through steps such as exposing, developing, and etching the electrode material layer, the first gate 141, the first electrode 142, and the second electrode 143 are formed. At this time, the first gate 141 extends along the sidewall of the light-emitting structure 120, the first electrode 142 and the second electrode 143 are connected to the active layer 130, the first electrode 142 is located between adjacent light-emitting structures 120, and the second electrode 143 is located on the surface of the light-emitting structure 120 away from the substrate 110.

[0059] One of the first electrode 142 and the second electrode 143 is the source electrode of the first transistor, and the other is the drain electrode of the first transistor. For example, the first electrode 142 is the source electrode of the first transistor, and the second electrode 143 is the drain electrode of the first transistor.

[0060] The first gate 141 can not only be located on the sidewall of the light-emitting structure 120, but also extend from the sidewall of the light-emitting structure 120 to both sides to the substrate 110 between adjacent light-emitting structures 120 and the top surface of the light-emitting structure 120 away from the substrate 110 respectively.

[0061] In this embodiment, by forming a first gate 141 on the sidewall of the light-emitting structure 120, forming a first electrode 142 on the active layer 130 between adjacent light-emitting structures 120, and forming a second electrode 143 on the surface of the light-emitting structure 120 away from the substrate 110, a first transistor can be formed on one side of the light-emitting structure 120. Further, when manufacturing a display device, there is no need to manufacture the first transistor on the driving substrate, which simplifies the manufacturing process complexity of the driving substrate.

[0062] In one embodiment, please refer to Figure 5 , after step S200, it includes:

[0063] Step S300: Form a gate dielectric layer 160 covering the light-emitting structure 120 and the substrate 110 between adjacent light-emitting structures 120. The gate dielectric layer 160 has a first opening 210 and a second opening 220. The first opening 210 and the second opening 220 surround the corresponding light-emitting structure 120. The first opening 210 exposes the active layer 130 on the side of the light-emitting structure 120 away from the substrate 110, and the second opening 220 exposes the active layer 130 between adjacent light-emitting structures 120.

[0064] As an example, methods such as plasma-enhanced chemical vapor deposition can be used to form a gate dielectric material layer over the entire surface. The material of the gate dielectric material layer can include silicon oxide, etc. After that, a gate dielectric layer 160 having a first opening 210 and a second opening 220 is formed through exposure, etching, and development.

[0065] Please refer to Figure 12 , the first opening 210 and the second opening 220 surround the corresponding light-emitting structure 120. In a top view of the semiconductor structure 100, the first electrode 142 and / or the first gate 141 are in a ring shape. The first opening 210 exposes the active layer 130 on the side of the light-emitting structure 120 away from the substrate 110, and the second opening 220 exposes the active layer 130 between adjacent light-emitting structures 120. In a cross-sectional view, there can be two second openings 220 between adjacent light-emitting structures 120.

[0066] Correspondingly, both the first opening 210 and the second opening 220 expose the active layer 130. Therefore, when forming the second electrode 143 and the first electrode 142, the second electrode 143 can be at least partially located within the first opening 210, and the first electrode 142 can be at least partially located within the second opening 220. Of course, the second electrode 143 can also cover the upper surface of the first opening 210, the first electrode 142 can be located within two adjacent second openings 220, and can also cover the gate dielectric layer 160 between two adjacent second openings 220.

[0067] In this embodiment, by forming a gate dielectric layer 160 having a first opening 210 and a second opening 220, the first electrode 142 and the first gate 141 are formed in a ring shape. By increasing the contact area between the first electrode 142, the first gate 141 and the active layer 130, the control of the first transistor is increased.

[0068] In one embodiment, refer to Figure 12 , the gate dielectric layer 160 further has a third opening 230 and a fourth opening 240, and the third opening 230 and the fourth opening 240 are arranged at intervals in the second direction between adjacent light-emitting structures 120.

[0069] Correspondingly, step S400 includes:

[0070] Step S410: Form a second gate 144, a third electrode 145 and a fourth electrode 146. In the first direction, the second gate 144 is connected to the first electrode 142, and the third electrode 145 and the fourth electrode 146 respectively fill the third opening 230 and the fourth opening 240. The first direction intersects the second direction, and one of the third electrode 145 and the fourth electrode 146 is the source electrode of the second transistor, and the other is the drain electrode of the second transistor.

[0071] Refer to Figure 13 , the first direction may be the X direction, and the second direction may be the Y direction. The first direction and the second direction may be perpendicular.

[0072] As an example, the second transistor may be a read transistor, and correspondingly, the first transistor may be a write transistor. Refer to Figure 15 , the write word line terminal 300 may include the first gate 141, the write bit line terminal 310 may include the second electrode 143, the second gate 144 is connected to the first electrode 142, so as to form an SN junction 340, and the read word line terminal 320 may include any one of the third electrode 145 and the fourth electrode 146, and the read bit line terminal 330 may include the other of the third electrode 145 and the fourth electrode 146.

[0073] In this embodiment, first, the second transistor can also be formed on one side of the light-emitting structure 120, further simplifying the complexity of the manufacturing process of the driving substrate. Secondly, in this embodiment, the first electrode 142 can be located in two adjacent second openings 220 and can also cover the gate dielectric layer 160 between two adjacent second openings 220, which increases the area of the first electrode 142, is beneficial to the connection between the second gate 144 and the first electrode 142, and further facilitates the formation of the SN junction 340. Finally, the second transistor is located between adjacent light-emitting structures 120, increasing the utilization rate of the film layer on one side of the light-emitting structure 120.

[0074] In one embodiment, after step S400, it includes:

[0075] Step S500: Form a planarized dielectric layer 170 covering the electrode layer 140. The planarized dielectric layer 170 has a first through-hole 250, a second through-hole 260, and a third through-hole 270. The first through-hole 250 exposes the light-emitting structure 120, the second through-hole 260 exposes the first gate 141, and the third through-hole 270 exposes the second electrode 143.

[0076] Step S600: Fill the first through-hole 250, the second through-hole 260, and the third through-hole 270 to form a first device electrode 180, a first word-line interconnect structure 181, and a first bit-line interconnect structure 182, respectively.

[0077] In step S500, refer to Figure 7 and Figure 14 , for example, a whole-surface dielectric material layer can be first formed by plasma-enhanced chemical vapor deposition, and then the dielectric material layer is subjected to chemical mechanical polishing to make the surface of the dielectric material layer away from the substrate 110 flat. The material of the dielectric material layer can be selected as silicon oxide. After that, the first through-hole 250, the second through-hole 260, and the third through-hole 270 can be formed in the dielectric material layer. The remaining dielectric material layer forms the planarized dielectric layer 170.

[0078] The first through-hole 250, the second through-hole 260, and the third through-hole 270 can be formed in a single patterning process or step by step. The first through-hole 250 exposes the light-emitting structure 120, the second through-hole 260 exposes the first gate 141, and the third through-hole 270 exposes the second electrode 143. Of course, a fourth through-hole, a fifth through-hole, etc. can also be formed in the planarized dielectric layer 170, and the fourth through-hole and the fifth through-hole can expose the second transistor.

[0079] In step S600, for example, refer to Figure 8 , an electroplating copper process can be used to deposit metallic copper on the inside and the upper surface of the first through-hole 250, the second through-hole 260, and the third through-hole 270. After that, the metallic copper is planarized, and the copper located inside the first through-hole 250, the second through-hole 260, and the third through-hole 270 is retained to form a first device electrode 180, a first word-line interconnect structure 181, and a first bit-line interconnect structure 182, respectively. The first device electrode 180 can be an anode. The specific materials of the first device electrode 180, the first word-line interconnect structure 181, and the first bit-line interconnect structure 182 are not limited in this embodiment, and the materials of the first device electrode 180, the first word-line interconnect structure 181, and the first bit-line interconnect structure 182 can also include other conductive metals.

[0080] In addition, before forming metallic copper, a barrier layer may be formed inside the first through-hole 250, the second through-hole 260, and the third through-hole 270. For example, the barrier layer may be formed by a chemical vapor deposition method. The material of the barrier layer may be selected from titanium, tantalum, or the like.

[0081] In this embodiment, by separately forming the first device electrode 180, the first word-line interconnect structure 181, and the first bit-line interconnect structure 182, it is convenient to connect to the driving substrate. At this time, the structure of the driving substrate is simple and easy to fabricate.

[0082] Based on the same concept, in one embodiment, please refer to Figure 16 , a method for manufacturing a display device is provided, including the following steps:

[0083] Step S10: Provide the semiconductor structure 100 provided in any one of the foregoing embodiments.

[0084] Step S20: Remove the substrate 110, and form a second device electrode on the surface of the light-emitting structure 120 exposed after removing the substrate 110.

[0085] Step S30: Form a driving substrate on the surface of the electrode layer 140 away from the light-emitting structure 120.

[0086] In step S10 and step S20, the substrate 110 on the side of the N-type semiconductor layer 121 may be removed, so as to expose the N-type semiconductor layer 121. For example, the substrate 110 may be removed by a laser lift-off or grinding method. After that, a second device electrode may be formed on the side of the N-type semiconductor layer 121 away from the light-emitting layer 122. The second device electrode may be a cathode.

[0087] In step S30, the driving substrate may be bonded on the side of the planarization dielectric layer 170 away from the light-emitting structure 120, and the driving substrate covers and connects the first device electrode 180, the first word-line interconnect structure 181, and the first bit-line interconnect structure 182.

[0088] The driving substrate may be provided with traces or the like. The traces can not only connect the first device electrode 180, the first word-line interconnect structure 181, and the first bit-line interconnect structure 182, but also electrically connect the second transistor and the second electrode, etc. After forming the driving substrate, it can be packaged into a display device.

[0089] In this embodiment, the structure of the driving substrate is simple and easy to fabricate. After bonding the driving substrate, a display device can be formed.

[0090] It should be understood that although Figure 1 and Figure 16The steps in the flowchart are shown sequentially according to the arrows, but these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless explicitly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 and Figure 16 At least some of the steps in can include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0091] Please continue to refer to Figure 8 , in one embodiment, a semiconductor structure 100 is provided. The semiconductor structure 100 includes a substrate 110, a light-emitting structure 120, an electrode layer 140, and an active layer 130.

[0092] The substrate 110 can be made of a semiconductor material, an insulating material, or any combination thereof. For example, the substrate 110 can be a silicon substrate, a silicon-germanium substrate, a silicon-germanium-carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium arsenide substrate, an indium phosphide substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates.

[0093] The light-emitting structure 120 can include an N-type semiconductor layer 121, a light-emitting layer 122, and a P-type semiconductor layer 123. The N-type semiconductor layer 121 can be formed on the substrate 110, the light-emitting layer 122 is formed on the N-type semiconductor layer 121, and the P-type semiconductor layer 123 is formed on the light-emitting layer 122.

[0094] In one possible example, the cross-sectional view of the light-emitting structure 120 can be trapezoidal, so it can have inclined sidewalls. In another possible example, the top view of the light-emitting structure 120 can be a regular octagon, or the top view of the light-emitting structure 120 can be rectangular or circular, etc. In yet another possible example, multiple light-emitting structures 120 can be formed on the substrate 110, and the multiple light-emitting structures 120 can be arranged in an array.

[0095] In addition, a transparent conductive layer can be formed on the side of the P-type semiconductor layer 123 away from the substrate 110. The transparent conductive layer can form a good ohmic contact with the P-type semiconductor layer 123.

[0096] The electrode layer 140 can include a first gate 141, a first electrode 142, and a second electrode 143. The first gate 141 extends along the sidewall of the light-emitting structure 120. The first electrode 142 is located on the substrate 110 between adjacent light-emitting structures 120, and the second electrode 143 is located on the surface of the light-emitting structure 120 away from the substrate 110.

[0097] One of the first electrode 142 and the second electrode 143 is the source electrode of the first transistor, and the other is the drain electrode of the first transistor. For example, the first electrode 142 is the source electrode of the first transistor, and the second electrode 143 is the drain electrode of the first transistor.

[0098] In a top view of the semiconductor structure 100, the first electrode 142 and / or the first gate 141 are in a ring shape. By increasing the contact area between the first electrode 142, the first gate 141 and the active layer 130, the control of the first transistor is increased.

[0099] The first gate 141 extends from the substrate 110 between adjacent light-emitting structures 120 to the surface of the light-emitting structure 120 away from the substrate 110. Correspondingly, the semiconductor structure 100 further includes a first bit line interconnecting structure 182 and a first word line interconnecting structure 181. The first bit line interconnecting structure 182 may be located on the surface of the second electrode 143 away from the substrate 110. The first word line interconnecting structure 181 may be located on the surface of the first gate 141 away from the substrate 110 between adjacent light-emitting structures 120. The first bit line interconnecting structure 182 and the first word line interconnecting structure 181 may extend along the thickness direction of the semiconductor structure 100.

[0100] The active layer 130 may be located between the first gate 141 and the light-emitting structure 120, and the first electrode 142 and the second electrode 143 are connected to the active layer 130. The material of the active layer 130 may include indium gallium zinc oxide, etc.

[0101] In addition, the semiconductor structure 100 may further include an interlayer dielectric layer 150. The interlayer dielectric layer 150 may be located on the side of the light-emitting structure 120 away from the substrate 110. The material of the interlayer dielectric layer 150 may include silicon oxide, etc.

[0102] In this embodiment, by forming the first gate 141 on the sidewall of the light-emitting structure 120, forming the first electrode 142 on the active layer 130 between adjacent light-emitting structures 120, and forming the second electrode 143 on the surface of the light-emitting structure 120 away from the substrate 110, the first transistor can be formed on one side of the light-emitting structure 120. Further, when manufacturing a display device, there is no need to manufacture the first transistor on the driving substrate, which simplifies the manufacturing process complexity of the driving substrate.

[0103] In one embodiment, the electrode layer 140 further includes a second gate 144, a third electrode 145, and a fourth electrode 146.

[0104] The second gate 144 is connected to the first electrode 142. The third electrode 145 and the fourth electrode 146 are connected to the active layer 130 and are located between adjacent light-emitting structures 120. One of the third electrode 145 and the fourth electrode 146 is the source of the second transistor, and the other is the drain of the second transistor. As an example, the second transistor can be a read transistor, and correspondingly, the first transistor can be a write transistor. The second gate 144 is connected to the first electrode 142 to form an SN junction 340. Specifically, in the first direction, the second gate 144 is connected to the first electrode 142. In the second direction, the third electrode 145 and the fourth electrode 146 are respectively located on both sides of the second gate 144, and the first direction intersects the second direction. The first direction can be the X direction, and the second direction can be the Y direction. The first direction and the second direction can be perpendicular.

[0105] In this embodiment, first, the second transistor can also be formed on one side of the light-emitting structure 120, which further simplifies the complexity of the manufacturing process of the driving substrate. Second, in this embodiment, the first electrode 142 can be located in two adjacent second openings 220 and can also cover the gate dielectric layer 160 between the two adjacent second openings 220, which increases the area of the first electrode 142, is beneficial to the connection between the second gate 144 and the first electrode 142, and thus facilitates the formation of the SN junction 340. Finally, the second transistor is located between adjacent light-emitting structures 120, which increases the utilization rate of the film layer on one side of the light-emitting structure 120.

[0106] Based on the same concept, in one embodiment, a display device is provided. The display device includes a driving substrate, a light-emitting structure 120, an electrode layer 140, and an active layer 130.

[0107] Trace lines or the like can be provided on the driving substrate. The trace lines can be electrically connected to the electrode layer 140 and the light-emitting structure 120 to drive the light-emitting structure 120 to emit light.

[0108] A plurality of light-emitting structures 120 are arranged at intervals on one side of the driving substrate. The electrode layer 140 includes a first gate 141, a first electrode 142, and a second electrode 143. The first gate 141 extends along the side wall of the light-emitting structure 120. The first electrode 142 is located between adjacent light-emitting structures 120. The second electrode 143 is located on the surface of the light-emitting structure 120 close to the driving substrate. The active layer 130 is located between the first gate 141 and the light-emitting structure 120. The first electrode 142 and the second electrode 143 are connected to the active layer 130. One of the first electrode 142 and the second electrode 143 is the source of the first transistor, and the other is the drain of the first transistor. For example, the first electrode 142 is the source of the first transistor, and the second electrode 143 is the drain of the first transistor.

[0109] For structures such as the light-emitting structure 120, the electrode layer 140, and the active layer 130, please refer to the descriptions of the light-emitting structure 120, the electrode layer 140, and the active layer 130 in one or more of the foregoing embodiments. In addition, the display device may further include a second transistor, a first bit-line interconnection structure 182, a first word-line interconnection structure 181, and other structures. These structures will not be elaborated in this embodiment.

[0110] In this embodiment, only traces and the like may be provided on the driving substrate, and the first transistor and the like are not provided, so that the manufacturing process of the driving substrate is relatively simple.

[0111] In the description of this specification, the descriptions with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. In addition, these specific features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that the "present embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment.

[0112] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0113] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims. The above is only the preferred implementation manner of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made by using the content of the specification and drawings of the present disclosure under the concept of the present disclosure, or directly / indirectly applied to other related technical fields, is included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, Comprising: Substrate; Light-emitting structures, a plurality of the light-emitting structures are spaced apart and disposed on one side of the substrate; Electrode layer, including a first gate, a first electrode and a second electrode, the first gate extends along the sidewall of the light-emitting structure, the first electrode is located on the substrate between adjacent light-emitting structures, the second electrode is located on the surface of the light-emitting structure away from the substrate, and one of the first electrode and the second electrode is the source electrode of the first transistor, and the other is the drain electrode of the first transistor; Active layer, located between the electrode layer and the light-emitting structure, covering the light-emitting structure and the substrate, and the first electrode and the second electrode are connected to the active layer.

2. The semiconductor structure according to claim 1, wherein The first electrode and / or the first gate is in a ring shape.

3. The semiconductor structure according to claim 1, wherein The first gate extends from the sidewall of the light-emitting structure to the substrate between adjacent light-emitting structures and the surface of the light-emitting structure away from the substrate on both sides respectively; The semiconductor structure further includes: First bit line interconnecting structure, located on the surface of the second electrode away from the substrate; First word line interconnecting structure, located on the surface of the first gate away from the substrate between adjacent light-emitting structures.

4. The semiconductor structure according to claim 1, wherein The electrode layer further includes a second gate, a third electrode and a fourth electrode located between adjacent light-emitting structures, the second gate is connected to the first electrode, the third electrode and the fourth electrode are connected to the active layer, and one of the third electrode and the fourth electrode is the source electrode of the second transistor, and the other is the drain electrode of the second transistor.

5. The semiconductor structure according to claim 4, wherein, In a first direction, the second gate is connected to the first electrode, and in a second direction, the third electrode and the fourth electrode are respectively located on both sides of the second gate, and the first direction intersects with the second direction.

6. The semiconductor structure according to claim 1, wherein The light-emitting structure includes a stacked N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer, the N-type semiconductor layer is located on the substrate, the light-emitting layer is located on the N-type semiconductor layer, and the P-type semiconductor layer is located on the light-emitting layer.

7. The semiconductor structure according to claim 6, wherein, The semiconductor structure includes: Transparent conductive layer, located on the side of the P-type semiconductor layer away from the substrate.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes: Interlayer dielectric layer, located on the side of the light-emitting structure away from the substrate.

9. The semiconductor structure according to claim 8, wherein, The semiconductor structure includes: First device electrode, located on the side of the light-emitting structure away from the substrate, and the first device electrode penetrates through the interlayer dielectric layer; Barrier layer, located between the first device electrode and the interlayer dielectric layer.

10. A display device, characterized in that, Comprising: Drive substrate; Light-emitting structures, a plurality of the light-emitting structures are spaced apart and disposed on one side of the drive substrate; Electrode layer, including a first gate, a first electrode and a second electrode, the first gate extends along the sidewall of the light-emitting structure, the first electrode is located between adjacent light-emitting structures, and the second electrode is located on the surface of the light-emitting structure close to the drive substrate; Active layer, located between the first gate and the light-emitting structure, the first electrode and the second electrode are connected to the active layer, and one of the first electrode and the second electrode is the source electrode of the first transistor, and the other is the drain electrode of the first transistor.

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