Display panel and display device

Abstract

The utility model discloses a display panel and a display device. The display panel comprises a substrate, a gate drive circuit and a plurality of sub-pixel circuits. A grid driving circuit of the display panel comprises a plurality of driving units which are arranged in a cascade mode, effective driving units in the driving units are electrically connected with sub-pixel circuits, virtual driving units in the driving units are disconnected with the sub-pixel circuits, and the virtual driving units do not have an output function. The dummy driving units may input shift signals to the corresponding active driving units. Therefore, the partial structure of the virtual driving unit is similar to that of the effective driving unit, so that the etching uniformity of the gate driving circuit can be improved, the deviation of the line width and the thickness of the lines formed by etching in different areas of the gate driving circuit is reduced, and the reliability of the gate driving circuit is improved. And the load uniformity of the shift signals accessed by the plurality of effective driving units can be improved, so that the stability of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] A display panel is a device with a display function.

[0003] The display panel drives multiple sub-pixel circuits to emit light through a gate driving circuit to achieve a display function. The current gate driving circuit includes multiple cascaded driving units. Before the multiple cascaded driving units, some circuit structures are usually provided to input shift signals to some driving units.

[0004] However, the above-mentioned circuit structure is quite different from the structure of the driving unit, which easily leads to poor etching uniformity of the gate driving circuit, that is, there are large deviations in the line width and thickness of the traces etched in different regions of the gate driving circuit, resulting in poor stability of the display panel. Summary of the Utility Model

[0005] Embodiments of the present application provide a display panel and a display device. The technical solutions are as follows:

[0006] According to one aspect of the present application, a display panel is provided. The display panel includes: a substrate, a gate driving circuit located on the substrate, and multiple sub-pixel circuits;

[0007] The gate driving circuit includes multiple cascaded driving units. The multiple driving units include multiple effective driving units and at least one virtual driving unit. Each effective driving unit is electrically connected to at least one of the sub-pixel circuits. The virtual driving unit is disconnected from the sub-pixel circuits. Each virtual driving unit includes a shift signal output terminal. Each effective driving unit includes at least one shift signal input terminal. Each shift signal input terminal corresponds to and is electrically connected to a shift signal output terminal;

[0008] Both the effective driving unit and the virtual driving unit include a shift register module and an output module. At least part of the structures of the output modules of the effective driving unit and the virtual driving unit are different.

[0009] Optionally, the structure of the shift register module of the effective driving unit is the same as the structure of the shift register module of the virtual driving unit. The output module of the virtual driving unit includes multiple transistors, and all the multiple transistors of the output module of the virtual driving unit are in a cut-off state.

[0010] Optionally, the multiple transistors of the output module of the virtual driving unit include a first pole, a second pole, and an active layer, one of the first pole and the second pole is a source electrode, and the other is a drain electrode;

[0011] The active layer of the transistor includes a first part connected to the first pole and a second part connected to the second pole, and the first part is disconnected from the second part.

[0012] Optionally, the multiple transistors of the output module of the virtual driving unit include a first pole, a second pole, and an active layer, one of the first pole and the second pole is a source electrode, and the other is a drain electrode;

[0013] The active layer of the transistor is connected to the first pole, and the active layer of the transistor is disconnected from the second pole.

[0014] Optionally, the multiple transistors of the output module of the virtual driving unit include a first pole, a second pole, and an active layer, one of the first pole and the second pole is a source electrode, and the other is a drain electrode;

[0015] The active layer of a part of the multiple transistors includes a first part connected to the first pole and a second part connected to the second pole, and the first part is disconnected from the second part;

[0016] The active layer of the other part of the multiple transistors is connected to the first pole, and the active layer of the other part of the multiple transistors is disconnected from the second pole.

[0017] Optionally, the display panel further includes a DC signal line located on the substrate, and the active layers of the multiple transistors of the output module of the virtual driving unit are all electrically connected to the DC signal line.

[0018] Optionally, the display panel further includes at least one target structure, and the target structure and the active layer are of the same layer structure;

[0019] The target structure satisfies at least one of the following conditions:

[0020] The target structure is located between the first part and the second part of one of the multiple transistors;

[0021] The orthographic projection of the target structure on the substrate is located on the side where the first orthographic projection is far from the second orthographic projection, the first orthographic projection is the orthographic projection of the active layer of one of the multiple transistors on the substrate, and the second orthographic projection is the orthographic projection of the first pole of the one transistor on the substrate.

[0022] Optionally, the display panel further includes an insulating layer on a side of the active layer away from the substrate, the insulating layer having at least one first opening corresponding to the at least one target structure, and an orthographic projection of the target structure on the substrate overlaps with an orthographic projection of the corresponding first opening on the substrate.

[0023] Optionally, the multiple transistors of the output module of the virtual driving unit further include gates. In one of the multiple transistors, an orthographic projection of the active layer on the substrate does not overlap with an orthographic projection of the gate on the substrate.

[0024] Optionally, both the effective driving unit and the output module of the virtual driving unit include multiple devices, and a circuit layout of the multiple devices in the effective driving unit is the same as a circuit layout of the multiple devices in the virtual driving unit;

[0025] The display panel further includes a DC signal line and a shift signal line on the substrate. The multiple devices include target devices. The target device of the effective driving unit includes a first electrode plate and a second electrode plate arranged in a direction away from the substrate. The first electrode plate is connected to the DC signal line, the second electrode plate is connected to the shift signal line. The target device of the virtual driving unit and the second electrode plate are of the same layer structure. The target device of the virtual driving unit is connected to the shift signal line, and the target device of the virtual driving unit is disconnected from the DC signal line.

[0026] Optionally, the substrate includes a display area and a non-display area. The multiple sub-pixel circuits are located on the display area, and the gate driving circuit is located on the non-display area;

[0027] A distance between the virtual driving unit and the display area is equal to a distance between the effective driving unit and the display area.

[0028] Optionally, the display panel further includes multiple clock signal lines and multiple first electrodes. The sub-pixel circuit is electrically connected to the first electrode. The first electrode corresponds to and is electrically connected to two of the multiple clock signal lines. The first electrode has a second opening, and an orthographic projection of the second opening of the first electrode on the substrate overlaps with an orthographic projection of the corresponding clock signal line on the substrate.

[0029] Optionally, the display panel further includes a pixel defining layer located on the substrate. The pixel defining layer includes multiple openings respectively corresponding to the multiple first electrodes, and orthographic projections of the openings on the substrate respectively overlap with orthographic projections of the corresponding first electrodes on the substrate;

[0030] The multiple openings include a first opening and a second opening. The first electrode corresponding to the first opening is electrically connected to the clock signal line. The size of the first opening is smaller than that of the second opening, and the size of the second opening of the first electrode corresponding to the first opening is smaller than the size of the second opening of the first electrode corresponding to the second opening.

[0031] Optionally, in a first direction, the widths of the portions of the first electrode in contact with the corresponding two clock signal lines are the same. The first direction is a direction perpendicular to the extension direction of the clock signal line.

[0032] On the other hand, a display device is provided. The display device includes a housing and any one of the above-mentioned display panels.

[0033] The beneficial effects brought by the technical solutions provided in the embodiments of the present application at least include:

[0034] A display panel is provided. The gate driving circuit of the display panel includes a plurality of cascaded driving units. The effective driving units among the plurality of driving units are electrically connected to the sub-pixel circuit, and the virtual driving units among the plurality of driving units are disconnected from the sub-pixel circuit. Then, the virtual driving units do not have an output function, and the virtual driving units can input shift signals for the corresponding effective driving units. Therefore, the virtual driving units provided in the present application have a partial structure similar to that of the effective driving units. In this way, the etching uniformity of the gate driving circuit can be improved to reduce the deviation in the line width and thickness of the traces formed by etching in different regions of the gate driving circuit, and the load uniformity of the shift signals accessed by the plurality of effective driving units can be improved, thereby improving the stability of the display panel. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0036] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0037] Figure 2 is Figure 1 a schematic structural diagram of a partial structure in the provided display panel;

[0038] Figure 3 is a schematic diagram of a gate driving circuit provided by an embodiment of the present application;

[0039] Figure 4It is a schematic structural diagram of a part of another display panel provided by an embodiment of the present application;

[0040] Figure 5 It is a schematic structural diagram of a part of another display panel provided by an embodiment of the present application;

[0041] Figure 6 It is Figure 5 An enlarged schematic diagram of a part of the display panel provided;

[0042] Figure 7 It is Figure 6 A schematic cross-sectional structure diagram of a display panel provided;

[0043] Figure 8 It is Figure 6 Another schematic cross-sectional structure diagram of a display panel provided;

[0044] Figure 9 It is a schematic structural diagram of a part of another display panel provided by an embodiment of the present application;

[0045] Figure 10 It is a schematic structural diagram of a part of another display panel provided by an embodiment of the present application;

[0046] Figure 11 It is Figure 10 A top view schematic diagram of the active pattern in the display panel provided;

[0047] Figure 12 It is Figure 5 A top view schematic diagram of the active pattern in the display panel provided;

[0048] Figure 13 It is Figure 10 A top view schematic diagram of the first gate pattern in the display panel provided;

[0049] Figure 14 It is Figure 9 A top view schematic diagram of the first gate pattern in the display panel provided;

[0050] Figure 15 It is Figure 10 A top view schematic diagram of the second gate pattern in the display panel provided;

[0051] Figure 16 It is Figure 5 A top view schematic diagram of the insulating layer in the display panel provided;

[0052] Figure 17 It is Figure 5 A top view schematic diagram of the first source-drain pattern in the display panel provided;

[0053] Figure 18 It isFigure 5 A top view schematic diagram of a flat layer in the provided display panel;

[0054] Figure 19 is Figure 5 A top view schematic diagram of a second source-drain pattern in the provided display panel;

[0055] Figure 20 A schematic structural diagram of a part of the structure in another display panel provided by an embodiment of the present application;

[0056] Figure 21 A schematic structural diagram of a part of the structure in another display panel provided by an embodiment of the present application;

[0057] Figure 22 A schematic structural diagram of a part of the structure in another display panel provided by an embodiment of the present application;

[0058] Figure 23 A schematic structural diagram of a part of the structure in another display panel provided by an embodiment of the present application.

[0059] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and the textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed Embodiments

[0060] To make the objectives, technical solutions, and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with the drawings.

[0061] An embodiment of the present application provides a display panel. Please refer to Figure 1 and Figure 2 , Figure 1 which is a schematic structural diagram of a display panel provided by an embodiment of the present application, Figure 2 is Figure 1 A schematic structural diagram of a part of the structure in the provided display panel. The display panel 10 includes: a substrate 11, a gate driving circuit 12 located on the substrate 11, and a plurality of sub-pixel circuits 13.

[0062] The gate driving circuit 12 includes a plurality of cascaded driving units. The plurality of driving units include a plurality of effective driving units 121 and at least one virtual driving unit 122. Each effective driving unit 121 is electrically connected to at least one sub-pixel circuit 13. The virtual driving unit 122 is disconnected from the sub-pixel circuit 13. Each virtual driving unit 122 includes a shift signal output terminal G2. Each effective driving unit 121 includes at least one shift signal input terminal G1. Each shift signal input terminal G1 corresponds to and is electrically connected to a shift signal output terminal G2.

[0063] Both the effective driving unit 121 and the dummy driving unit 122 include a shift register module A1 and an output module A2, and at least part of the structures of the output modules A2 of the effective driving unit 121 and the dummy driving unit 122 are different.

[0064] It should be noted that the multiple sub-pixel circuits 13 can be the driving circuits corresponding to multiple sub-pixels in the display panel 10 respectively. Each effective driving unit 121 is electrically connected to at least one sub-pixel circuit 13, that is, each effective driving unit 121 can output signals to at least one sub-pixel circuit 13, and the dummy driving unit 122 is disconnected from the sub-pixel circuit 13, that is, the dummy driving unit 122 does not have the function of outputting signals to the sub-pixel circuit 13. The multiple cascaded driving units can include a first-stage driving unit, a second-stage driving unit, a third-stage driving unit,..., an nth-stage driving unit arranged in sequence, and n is the level of the nth-stage driving unit.

[0065] In summary, the embodiment of the present application provides a display panel. Among them, the gate driving circuit of the display panel includes multiple cascaded driving units. The effective driving units among the multiple driving units are electrically connected to the sub-pixel circuits, and the dummy driving units among the multiple driving units are disconnected from the sub-pixel circuits. Then the dummy driving unit does not have an output function, and the dummy driving unit can input a shift signal to the corresponding effective driving unit. Therefore, the dummy driving unit provided in the present application has a partial structure similar to that of the effective driving unit, so that the etching uniformity of the gate driving circuit can be improved, the deviation of the line width and thickness of the traces formed by etching in different regions of the gate driving circuit can be reduced, and the load uniformity of the shift signals accessed by multiple effective driving units can be improved, thereby improving the stability of the display panel.

[0066] Please refer to Figure 1 , in the display panel 10 provided by the embodiment of the present application, the substrate 11 can be used to carry the gate driving circuit 12 and the sub-pixel circuit 13. The substrate 11 can include a display area B1 and a non-display area B2. In addition, the shape of the substrate 11 can be Figure 1 the rectangle shown, and the shape of the substrate 11 can also be a rounded rectangle. The embodiment of the present application does not limit this.

[0067] The gate driving circuit 12 can be located on the non-display area B2 of the substrate 11. The display panel 10 provided by the embodiment of the present application adopts the gate on array (GOA) technology, that is, the gate driving circuit 12 is integrated on the array substrate, which can improve the integration degree of the display panel 10. The gate driving circuit 12 has two functions. One function is the output function, that is, the gate driving circuit 12 can output a gate scanning driving signal to the sub-pixel circuit 13, and the gate scanning driving signal can be used to drive the sub-pixel circuit 13, so as to achieve the effect of driving the sub-pixels to emit light. Another function is the shift register function. The driving circuit 12 includes a plurality of cascaded driving units, and then a plurality of effective driving units 121 can transmit the shift signal in a step-by-step shift manner from the first-stage driving unit downwards. The cascading relationship of the plurality of driving units can be specifically determined by the circuit structure of the driving unit, and the embodiment of the present application does not limit this.

[0068] The plurality of driving units include a plurality of effective driving units 121 and at least one virtual driving unit 122. Among them, each effective driving unit 121 is electrically connected to at least one sub-pixel circuit 13, and the virtual driving unit 122 is disconnected from the sub-pixel circuit 13. That is, the effective driving unit 121 has an output function and a shift register function, while the virtual driving unit 122 only has a shift register function. Exemplarily, a plurality of sub-pixels of the display panel 10 can be arranged in rows and columns, and each effective driving unit 121 can be electrically connected to the sub-pixel circuit 13 corresponding to the sub-pixels in the same row to transmit the gate scanning driving signal, so as to drive the sub-pixels in this row to emit light by controlling the on / off state of the sub-pixel circuit 13 in the same row. Since both the effective driving unit 121 and the virtual driving unit 122 have a shift register function, after the output of a gate scanning driving signal is completed, the output of the next gate scanning driving signal can be controlled by a clock signal, so as to achieve the effect of progressive scanning driving, and further enable the display panel 10 to display.

[0069] Each effective driving unit 121 includes at least one shift signal input terminal G1, including two cases: one case is that each effective driving unit 121 can include one shift signal input terminal G1. Since each shift signal input terminal G1 corresponds to and is electrically connected to a shift signal output terminal G2, each effective driving unit 121 is only electrically connected to the shift signal output terminal G2 of a previous-stage driving unit 12. Therefore, in this case, the maximum previous level is the difference between the level of the effective driving unit 121 and the level of the electrically connected virtual driving unit 122.

[0070] Another case is that each effective driving unit 121 may include a plurality of shift signal input terminals G1. Since each shift signal input terminal G1 corresponds to and is electrically connected to a shift signal output terminal G2, each effective driving unit 121 may correspond to a plurality of shift signal output terminals G2. The levels of the driving units 12 where the plurality of shift signal output terminals G2 are located may be different, that is, each effective driving unit 121 may be electrically connected to a plurality of pre-stage driving units 12 to receive shift signals. Therefore, in this case, the difference between the level of the effective driving unit 121 and the levels of the pre-stage driving units 12 connected thereto is multiple, and the maximum pre-stage level is the maximum value among the multiple differences.

[0071] In addition, in a related technology, the shift signals accessed by a part of the driving units among the plurality of driving units are accessed by a circuit structure, and the shift signals accessed by another part of the driving units among the plurality of driving units come from the pre-stage driving units. The structural differences between the driving units and the circuit structure are relatively large, which easily leads to poor etching uniformity of the gate driving circuit, and thus the stability of the formed gate driving circuit is poor. In the display panel provided by the embodiments of the present application, the number of virtual driving units 122 is the same as the maximum pre-stage level of the shift signal input terminals G1 of the effective driving units 121. Then, the shift signals accessed by each effective driving unit 121 come from the virtual driving units 122 or the effective driving units 121, and the virtual driving units 122 and the effective driving units 121 have similar structures. The manufacturing process of the gate driving circuit 12 may include an etching process. The similar structures of the virtual driving units 122 and the effective driving units 121 can ensure that the overall distribution of the patterns and the pattern density are similar. In this way, the difference in the etching rate and etching depth in different regions of the gate driving circuit 12 can be reduced. Therefore, the virtual driving units 122 provided by the embodiments of the present application can effectively improve the etching uniformity of the gate driving circuit 12, that is, the line width and thickness deviation of the traces in different regions of the gate driving circuit 12 are small, and the uniformity of the loads of the shift signals accessed by a plurality of effective driving units 121 can be improved, thereby improving the stability of the gate driving circuit 12 and further improving the stability of the display effect of the display panel.

[0072] The sub-pixel circuit 13 may be located on the display area B1 of the substrate 11, and the plurality of sub-pixel circuits 13 may respectively correspond to a plurality of sub-pixels in the display panel 10. The sub-pixel circuit 13 may include a plurality of transistors, and the transistors in the sub-pixel circuit 13 may be driven to turn on by the gate scanning driving signal, so that the effect of driving the corresponding sub-pixel to emit light can be achieved.

[0073] In an exemplary embodiment, both the effective driving unit and the virtual driving unit include a shift register module and an output module. Please refer to Figure 2If the structure of the shift register module A1 of the active driving unit 121 is the same as that of the shift register module A1 of the virtual driving unit 122, both the active driving unit 121 and the virtual driving unit 122 can implement the shift register function, and the structural similarity between the active driving unit 121 and the virtual driving unit 122 can be effectively improved, thereby improving the etching uniformity of the gate driving circuit 12. The output module A2 of the virtual driving unit 122 includes a plurality of transistors. All the transistors of the output module A2 of the virtual driving unit 122 are in the cut-off state, and at least part of the structure of the output module A2 of the active driving unit 121 and the virtual driving unit 122 is different, which can ensure that the output function of the virtual driving unit is invalidated, so the virtual driving unit 122 does not have an output function.

[0074] In another related technology, there is also a virtual driving unit. The virtual driving unit has the same structure as the active driving unit. The virtual driving unit is only used to fill the area with a large gap. The virtual driving unit in the related technology is not electrically connected to other circuit structures and is in a floating state, which is likely to cause the problem of electrostatic breakdown. However, the virtual driving unit 122 provided in this application is different from at least part of the structure of the output module A2 of the active driving unit 121, and the structure of the shift register module A1 is the same, that is, the virtual driving unit 122 of this application retains the shift register function but does not have an output function. In addition, the virtual driving unit 122 of this application is electrically connected to the active unit 121 to provide a shift signal, which can effectively prevent part of the structure in the virtual driving unit 122 from being in a floating state, thereby avoiding the problem of electrostatic breakdown of this part of the structure. Exemplarily, the shift register module A1 of the virtual driving unit 122 is not in a floating state, and among the multiple traces of the output module A2 of the virtual driving unit 122, the part of the traces connected to the shift register module A1 is also not in a floating state.

[0075] Figure 2 The specific structures of the active driving unit 121 and the virtual driving unit 122 are not shown, and the specific structures of the active driving unit 121 and the virtual driving unit 122 can be determined by the circuit schematic diagram. The circuit schematic diagrams of the active driving unit 121 and the virtual driving unit 122 can be the same to ensure that the circuit layouts of the active driving unit 121 and the virtual driving unit 122 are the same, thereby improving the structural similarity between the active driving unit 121 and the virtual driving unit 122.

[0076] For an exemplary circuit schematic diagram, please refer to Figure 3 , Figure 3It is a schematic diagram of a gate driving circuit provided by an embodiment of the present application. The gate driving circuit 12 includes fifteen transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15) and six capacitor structures (C1, C2, C3, C4, C5, C6), that is, the gate driving circuit 12 can be a 16T5C structure. Among them, the shift register module A1 includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the first capacitor structure C1 and the second capacitor structure C2, that is, the part of the shift register module A1 corresponding to 8T2C. The output module A2 includes the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the third capacitor structure C3, the fourth capacitor structure C4, the fifth capacitor structure C5 and the sixth capacitor structure C6, that is, the part of the output module A2 corresponding to 7T4C. Both the effective driving unit 121 and the virtual driving unit 122 can adopt Figure 3 The circuit schematic diagram shown. The ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 of the output module A2 of the virtual driving unit 122 are all in the cut-off state, so that it can be ensured that the virtual driving unit 122 does not have an output function.

[0077] In the shift register module A1, the gate of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first pole is electrically connected to the shift signal input terminal G1 to access the shift signal carry[N - 2], where the shift signal carry[N - 2] is the shift signal output by the driving unit two levels in advance, and the second pole is electrically connected to the first node N1. The gate of the second transistor T2 is connected to the second pole of the first transistor T1, the first pole is connected to the second clock signal CK2, and the second pole is electrically connected to the second node N2. The gate of the third transistor T3 is electrically connected to the second clock signal terminal CK2, the first pole is electrically connected to the low-level DC signal terminal VGL, and the second pole is electrically connected to the second node N2. The gate of the fourth transistor T4 is electrically connected to the second node N2, the first pole is electrically connected to the high-level DC signal terminal VGH, and the second pole is electrically connected to the shift signal output terminal G2. The gate of the fifth transistor T5 is electrically connected to the fourth node T4, the first pole is electrically connected to the third clock signal terminal CK3, and the second pole is electrically connected to the second capacitor structure C2 and the sixth capacitor structure C6. The gate of the sixth transistor T6 is electrically connected to the second node N2, the first pole is electrically connected to the high-level DC signal terminal VGH, and the second pole is electrically connected to the third node N3. The gate of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3, the first pole is electrically connected to the third node N3, and the second pole is electrically connected to the first node N1. The first capacitor structure C1 is electrically connected to the high-level DC signal terminal VGH and the third node N3 respectively. The second capacitor structure C2 is electrically connected to the sixth capacitor structure C6 and the fourth node N4 respectively.

[0078] In the output module A2, the gate of the ninth transistor T9 is electrically connected to the eighth node N8, the first pole is electrically connected to the drive signal output terminal Gout[N], and the second pole is electrically connected to the high-level DC signal terminal VGH. The gate of the tenth transistor T10 is electrically connected to the fifth node N5, the first pole is electrically connected to the third clock signal terminal CK3, and the second pole is electrically connected to the drive signal output terminal Gout[N]. The gate of the eleventh transistor T11 is electrically connected to the sixth node N6, the first pole is electrically connected to the gate of the fourth transistor T4, and the second pole is electrically connected to the eighth node N8. The gate of the twelfth transistor T12 is electrically connected to the sixth node N6, the first pole is electrically connected to the gate of the fifth transistor T5, and the second pole is electrically connected to the fifth node N5. The gate of the thirteenth transistor T13 is electrically connected to the shift signal input terminal G1 to access the shift signal carry[N-10], the first pole is electrically connected to the sixth node N6, and the second pole is electrically connected to the seventh node N7. The gate of the fourteenth transistor T14 is electrically connected to the shift signal input terminal G1 to access the shift signal carry[N-2], the first pole is electrically connected to the strobe signal terminal MS, and the second pole is electrically connected to the seventh node N7. The gate of the fifteenth transistor T15 is electrically connected to the voltage control terminal Eout, the first pole is electrically connected to the low-level DC signal terminal VGL, and the second pole is electrically connected to the sixth node N6. The third capacitor structure C3 is electrically connected to the high-level DC signal terminal VGH and the eighth node N8 respectively. The fourth capacitor structure C4 is electrically connected to the fifth node N5 and the drive signal output terminal Gout[N] respectively. The fifth capacitor structure C5 is electrically connected to the fifth node N5 and the sixth node N6 respectively. The sixth capacitor structure C6 is electrically connected to the high-level DC signal terminal VGH and the shift signal output terminal G2 respectively.

[0079] In addition, Figure 3 Three shift signals are shown: Carry[N], Carry[N-2], and Carry[N-10], where N is the level of the driving unit. Exemplarily, Carry[N] is the shift signal output from the shift signal output terminal G2 of the nth-level driving unit, that is, the shift signal output from the shift register module A1. Carry[N-2] and Carry[N-10] are the shift signals input to the shift signal input terminal G1 of the nth-level driving unit. Carry[N-2] is the shift signal output from the (n-2)th-level driving unit. The source of the first transistor T1 and the gate of the fourteenth transistor T14 are both connected to the Carry[N-2] shift signal. Carry[N-10] is the shift signal output from the (n-10)th-level driving unit, and the gate of the thirteenth transistor T13 is connected to the Carry[N-10] shift signal. Since the maximum pre-stage level among these three shift signals is 10 levels, the number of virtual driving units in the gate driving circuit is at least 10.

[0080] Figure 3The structure of a display panel corresponding to the shown circuit schematic diagram can be referred to Figure 4 , Figure 4 is a schematic structural diagram of a part of another display panel provided by an embodiment of the present application (for clearly showing the arrangement of multiple driving units, Figure 4 the connection relationship between the effective driving unit 121 and the virtual driving unit 122 is not shown). The gate driving circuit 12 includes multiple driving units, Figure 3 only part of the driving units are shown. The first-stage driving unit to the tenth-stage driving unit are virtual driving units 122, and the eleventh-stage driving unit to the fifteenth-stage driving unit are effective driving units 121. In this way, it can be ensured that the shift signals accessed by the effective driving unit 121 come from the virtual driving unit 122 and the effective driving unit 121, thereby improving the stability of the shift signals. The display panel may further include a gate scanning driving signal line 151. The effective driving unit 121 can be electrically connected to the sub-pixel circuit through the gate scanning driving signal line 151. The gate scanning driving signal line 151 can be used to transmit the gate scanning driving signal, so that the effective driving unit 121 can control the sub-pixels to emit light. The virtual driving unit 122 is not connected to the gate scanning driving signal line 151 to ensure that the virtual driving unit 122 is disconnected from the sub-pixel circuit. In addition, Figure 4 the shape of the shown substrate 11 is a rounded rectangle, but Figure 4 only the rounded corner area of the substrate 11 and part of the structure on the rounded corner area are shown. Ten virtual driving units 122 are arranged on the rounded corner area, which can improve the space utilization rate.

[0081] Optionally, please refer to Figure 1 and Figure 4 , the substrate 11 includes a display area B1 and a non-display area B2. Multiple sub-pixel circuits 13 are located on the display area B1, and the gate driving circuit 12 is located on the non-display area B2. The distance d2 between the virtual driving unit 122 and the display area B1 is equal to the distance d1 between the effective driving unit 121 and the display area B1. In this way, the uniformity of the pattern distribution of the gate driving circuit 12 can be improved, and thus the etching uniformity can be effectively improved. For Figure 1 the shown rectangular substrate 11, multiple driving units can be spaced apart, and the spacing distances can be the same, then the uniformity of the distribution of multiple driving units can be improved, and thus the etching uniformity can be further improved. For Figure 4 the shown rounded rectangular substrate 11, multiple driving units can be spaced apart. Since multiple virtual driving units 122 are spaced apart on the rounded corner area of the substrate 11, the spacing distances are not strictly required to be the same. Exemplarily, the deviation rate range of the distance between two adjacent virtual driving units 122 in the rounded corner area and the distance between two adjacent effective driving units 122 outside the rounded corner area can be 0 to 10%.

[0082] In an exemplary embodiment, the active layer of the transistor can be disconnected to turn the transistor off. Please refer to Figure 5 and Figure 6 , Figure 5 which is a schematic structural diagram of a part of another display panel provided by an embodiment of the present application ( Figure 5 corresponding to Figure 3 the circuit schematic diagram shown, Figure 5 and can be a top view structural diagram of a virtual driving unit), Figure 6 is Figure 5 an enlarged schematic diagram of a part of the display panel provided by Figure 6 which can be Figure 5 an enlarged schematic diagram of the Q2 area of the display panel provided by . The multiple transistors of the output module of the virtual driving unit include a first pole 161, a second pole 162, and an active layer 163. One of the first pole 161 and the second pole 162 is the source electrode, and the other is the drain electrode. The first pole 161 and the second pole 162 can be of the same layer structure.

[0083] The structure of the active layer 163 of the transistor includes at least one of the following structures:

[0084] 1) For one structure, please refer to Figure 6 and Figure 7 , Figure 7 which is Figure 6 a schematic cross-sectional structure diagram of a display panel provided by Figure 7 which can be Figure 6 a schematic cross-sectional structure diagram of the display panel at E1 - E1 provided by . The active layer 163 of the transistor includes a first part 1631 connected to the first pole 161 and a second part 1632 connected to the second pole 162. The first part 1631 and the second part 1632 are disconnected. There is a gap between the first part 1631 and the second part 1632. Exemplarily, corresponding to Figure 3 the circuit schematic diagram shown, the structure of the fifteenth transistor T15 of the virtual driving unit can be Figure 7 the structure shown. Since the active layer 163 of the fifteenth transistor T15 is disconnected into the first part 1631 and the second part 1632, the fifteenth transistor T15 of the virtual driving unit cannot form a channel, so that the fifteenth transistor T15 can be made inoperative.

[0085] 2) For another structure, please refer to Figure 6 and Figure 8 , Figure 8 which is Figure 6 another schematic cross-sectional structure diagram of the display panel provided by Figure 8 which can be Figure 6(Schematic cross-sectional structure diagram of the provided display panel at E2-E2), the active layer 163 of the transistor is connected to the first electrode 161, and the active layer 163 of the transistor is disconnected from the second electrode 162. There is a gap on the side of the active layer 163 away from the first electrode 161. Exemplarily, corresponding to Figure 3 the circuit schematic diagram shown, the structures of the thirteenth transistor T13 and the fourteenth transistor T14 of the virtual driving unit can be Figure 8 the structures shown. The thirteenth transistor T13 is connected to the second electrode 162 of the fourteenth transistor T14. Since the active layer 163 of the thirteenth transistor T13 and the fourteenth transistor T14 is disconnected into a first part 1631 and a third part 1633, wherein the first part 1631 of the active layer 163 corresponding to the thirteenth transistor T13 is only connected to the first electrode 161 and is disconnected from the second electrode 162, and the third part 1633 of the active layer 163 corresponding to the fourteenth transistor T14 is only connected to the first electrode 161 and is disconnected from the second electrode 162, then neither the thirteenth transistor T13 nor the fourteenth transistor T14 of the virtual driving unit can form a channel, so that the thirteenth transistor T13 and the fourteenth transistor T14 can be made inoperative.

[0086] Both of the above two structures can prevent conduction between the first electrode 161 and the second electrode 162, so that the transistor can be made inoperative. The structures of the multiple transistors of the output module of the virtual driving unit can be any one of the above two structures, so that the output function of the virtual driving unit 122 can be invalidated.

[0087] In addition, the embodiments of the present application can also remove the first electrode 161 or the second electrode 162 of the transistor of the output module of the virtual driving unit, so that the transistor can also be made inoperative, thereby invalidating the output function of the virtual driving unit 122.

[0088] Optionally, please refer to Figure 9 , Figure 9FIG. 0 is a schematic structural diagram of a partial structure in another display panel provided by an embodiment of the present application. The display panel further includes a DC signal line 152 located on a substrate 11, and active layers 163 of multiple transistors in an output module of a virtual driving unit are all electrically connected to the DC signal line 152. The DC signal line 152 can access a DC signal to the disconnected active layer 163, thereby avoiding the floating state of the disconnected active layer 163, and further avoiding the problem of electrostatic breakdown. The disconnected active layers 163 of multiple transistors can be electrically connected to the same DC signal line 152, that is, the whole accesses the same DC signal, which is convenient for manufacturing, and while maintaining the circuit stability, it is beneficial to the layout of the traces and saves the wiring space. Exemplarily, the DC signal line 152 can be used to transmit a high-level DC signal. Additionally, the DC signal line 152 can be located on a side of the first electrode 161 or the second electrode 162 away from the substrate 11, then the disconnected active layers 163 of multiple transistors can be transferred through the first electrode 161 or the second electrode 162 connected to the active layer 163 to achieve the effect of being electrically connected to the DC signal line 152, so as to access the DC signal.

[0089] Optionally, please refer to Figure 7 , multiple transistors in an output module A2 of the virtual driving unit 122 further include a gate 164. In one transistor among multiple transistors, the orthographic projection of the active layer 163 on the substrate 11 does not overlap with the orthographic projection of the gate 164 on the substrate 11. Additionally, there can be a certain distance between the orthographic projection of the active layer 163 on the substrate 11 and the orthographic projection of the gate 164 on the substrate 11, so as to ensure that the active layer 163 is disconnected and facilitate the electrical connection between the active layer 163 and the DC signal line 152. Exemplarily, the distance between the orthographic projection of the active layer 163 on the substrate 11 and the orthographic projection of the gate 164 on the substrate 11 can be greater than 0.8 micrometers.

[0090] Optionally, corresponding to Figure 3 the circuit schematic diagram shown, both the effective driving unit and the output module A2 of the virtual driving unit include multiple devices, and the specific structure can be referred to Figure 5 and Figure 10 , Figure 10 FIG. 16 is a schematic structural diagram of a partial structure in another display panel provided by an embodiment of the present application ( Figure 10 can be a top view structural schematic diagram of the effective driving unit), the effective driving unit 121 and the virtual driving unit 122 include active patterns P1, first gate patterns P2, second gate patterns P3, insulating layers P4, first source-drain patterns P5, planarization layers P6, and second source-drain patterns P7 located on different layers.

[0091] The active pattern P1 includes active layers of multiple transistors. For the active layers of the effective driving unit 121, please refer to Figure 11 ,Figure 11 For Figure 10 A top view schematic diagram of the active pattern in the provided display panel. The first sub-pattern P101 of the active pattern P1 is the active layer of the first transistor T1, the second sub-pattern P102 of the active pattern P1 is the active layer of the second transistor T2, the third sub-pattern P103 of the active pattern P1 is the active layer of the third transistor T3, the fourth sub-pattern P104 of the active pattern P1 is the active layer shared by the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, the fifth sub-pattern P105 of the active pattern P1 is the active layer of the ninth transistor T9, the sixth sub-pattern P106 of the active pattern P1 is the active layer of the tenth transistor T10, the seventh sub-pattern P107 of the active pattern P1 is the active layer of the eleventh transistor T11, the eighth sub-pattern P108 of the active pattern P1 is the active layer of the twelfth transistor T12, and the ninth sub-pattern P109 of the active pattern P1 is the active layer shared by the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15.

[0092] In addition, for the active layer of the virtual driving unit 122, please refer to Figure 12 , Figure 12 is Figure 5 A top view schematic diagram of the active pattern in the provided display panel. In the shift register module A1 of the effective driving unit 121 and the virtual driving unit 122, the structures of the active layers of the first transistor T1 to the eighth transistor T8 are the same, so that the structural similarity between the effective driving unit 121 and the virtual driving unit 122 can be improved. In the output module A2 of the virtual driving unit 122, for the disconnection method of the active layers of the ninth transistor T9, the tenth transistor T10, and the fifteenth transistor T15, please refer to Figure 7 , that is, the active layer 163 of the ninth transistor T9 and the tenth transistor T10 includes a first part 1631 connected to the first pole 161 and a second part 1632 connected to the second pole 162, and the first part 1631 is disconnected from the second part 1632. For the disconnection method of the active layers of the eleventh transistor T11 to the fourteenth transistor T14, please refer to Figure 8 , that is, the active layer 163 of the eleventh transistor T11 to the fourteenth transistor T14 is connected to the first pole 161 and is disconnected from the second pole 162.

[0093] The first gate pattern P2 includes the gates of multiple transistors and the first electrodes of multiple capacitive structures. For the first gate pattern P2 of the effective driving unit 121, please refer to Figure 13 , Figure 13 is Figure 10A top view schematic diagram of the first gate pattern in the provided display panel. The first sub-pattern P201 of the first gate pattern P2 is the gate of the first transistor T1, the second sub-pattern P202 of the first gate pattern P2 is the gate of the second transistor T2, the third sub-pattern P203 of the first gate pattern P2 is the gate of the third transistor T3, the fourth sub-pattern P204 of the first gate pattern P2 is the common gate of the fourth transistor T4 and the sixth transistor T6 and the first electrode plate of the first capacitor structure C1, the fifth sub-pattern P205 of the first gate pattern P2 is the gate of the eighth transistor T8, the sixth sub-pattern P206 of the first gate pattern P2 is the gate of the fifth transistor T5 and the first electrode plate of the second capacitor structure C2 and the sixth capacitor structure C6, the seventh sub-pattern P207 of the first gate pattern P2 is the gate of the seventh transistor T7, the eighth sub-pattern P208 of the first gate pattern P2 is the gate of the ninth transistor T9 and the first electrode plate of the third capacitor structure C3, the ninth sub-pattern P209 of the first gate pattern P2 is the gate of the tenth transistor T10 and the first electrode plate of the fourth capacitor structure C4 and the fifth capacitor structure C5, the tenth sub-pattern P210 of the first gate pattern P2 is the common gate of the eleventh transistor T11 and the twelfth transistor T12, the eleventh sub-pattern P211 of the first gate pattern P2 is the common gate of the thirteenth transistor T13 and the fourteenth transistor T14, and the twelfth sub-pattern P212 of the first gate pattern P2 is the gate of the fifteenth transistor T15.

[0094] In addition, for the first gate pattern P2 of the virtual driving unit 122, please refer to Figure 14 , Figure 14 which Figure 5 is a top view schematic diagram of the first gate pattern in the provided display panel. In the shift register modules A1 of the effective driving unit 121 and the virtual driving unit 122, the gate structures of the first transistor T1 to the eighth transistor T8 are the same, and the structures of the first capacitor structure C1 and the second capacitor structure C2 are the same, so that the structural similarity of the effective driving unit 121 and the virtual driving unit 122 can be improved. In the output module A2 of the virtual driving unit 122, since only the part connected to the first pole of the active layers of the eleventh transistor T11 and the twelfth transistor T12 is retained, there is no need to set the gates of the eleventh transistor T11 and the twelfth transistor T12, that is, the tenth sub-pattern P210 of the first gate pattern P2 can be not included in the output module A2 of the virtual driving unit 122, saving the etching process. In addition, the sixth sub-pattern P206 of the first gate pattern P2 is the gate of the fifth transistor T5 and the first electrode plate of the second capacitor structure C2, that is, the first electrode plate of the sixth capacitor structure C6 of the virtual driving unit 122 is not set, so that the sixth capacitor structure C6 of the virtual driving unit 122 can be prevented from accessing a DC signal.

[0095] The second gate pattern P3 includes second electrodes of a plurality of capacitor structures. For the second gate pattern P3 of the active driving unit 121 and the dummy driving unit 122, please refer to Figure 15 , Figure 15 is Figure 10 a top view schematic diagram of the second gate pattern in the provided display panel. The first sub-pattern P301 of the second gate pattern P3 is the second electrode of the first capacitor structure C1, the second sub-pattern P303 of the second gate pattern P3 is the second electrode of the second capacitor structure C2 and the sixth capacitor structure C6, the third sub-pattern P303 of the second gate pattern P3 is the second electrode of the third capacitor structure C3, the fourth sub-pattern P304 of the second gate pattern P3 is the second electrode of the fourth capacitor structure C4, and the fifth sub-pattern P305 of the second gate pattern P3 is the second electrode of the fifth capacitor structure C5. The second gate pattern P3 of the active driving unit 121 and the dummy driving unit 122 has the same structure, so that the structural similarity between the active driving unit 121 and the dummy driving unit 122 can be improved.

[0096] Optionally, the display panel further includes a DC signal line and a shift signal line located on the substrate. The plurality of devices include a target device. Please refer to Figure 3 , and the target device is the sixth capacitor structure C6. Please refer to Figure 13 and Figure 15 , the target device of the active driving unit 121 includes a first electrode and a second electrode arranged in a direction away from the substrate 11. The first electrode is connected to the DC signal line to access a DC signal, and the second electrode is connected to the shift signal line to output a shift signal. Please refer to Figure 14 and Figure 15 , the target device of the dummy driving unit and the second electrode of the sixth capacitor structure C6 are of the same layer structure. The target device of the dummy driving unit 122 is connected to the shift signal line, and the target device of the dummy driving unit is disconnected from the DC signal line, so as to avoid the target device of the dummy driving unit 122 accessing the DC signal, and further ensure that the output function of the dummy driving unit 122 is invalidated.

[0097] The insulating layer P4 can be an interlayer dielectric layer between the second gate pattern P3 and the first source-drain pattern P5 to play an insulating role. Please refer to Figure 16 , Figure 16 is Figure 5 a top view schematic diagram of the insulating layer in the provided display panel. The insulating layer P4 can include a plurality of vias H3, and the structures in the active pattern P1, the first gate pattern P2, and the second gate pattern P3 can be electrically connected to the structures in the first source-drain pattern P5 and the second source-drain pattern P7 through these vias H3.

[0098] The first source-drain pattern P5 may include the sources and drains of multiple transistors. For the first source-drain pattern P5 of the virtual driving unit 122, please refer to Figure 17 , Figure 17 is Figure 5 a top view schematic diagram of the first source-drain pattern in the provided display panel. In the output module A2 of the virtual driving unit 122, since the active layers of some transistors are disconnected from the second pole, the second pole corresponding to the active layers of some transistors may not be provided. Additionally, as Figure 16 shown by the first sub-pattern P501 of the first source-drain pattern P5, in the output module A2 of the virtual driving unit 122, the sources or drains of multiple transistors may be connected, thereby facilitating access to the same DC signal and facilitating manufacturing.

[0099] The planarization layer P6 can play an insulating role between the first source-drain pattern P5 and the second source-drain pattern P7. Please refer to Figure 18 , Figure 18 is Figure 5 a top view schematic diagram of the planarization layer in the provided display panel. The planarization layer P6 may include multiple vias H4, and the structures in the first source-drain pattern P5 can be electrically connected to the structures in the second source-drain pattern P7 through these vias H4. Additionally, the planarization layer P6 can also improve the flatness of the second source-drain pattern P7.

[0100] The second source-drain pattern P7 may include multiple traces. Please refer to Figure 3 and Figure 19 , Figure 19 is Figure 5 a top view schematic diagram of the second source-drain pattern in the provided display panel. The first trace P701 and the eighth trace P708 are low-level DC signal lines (VGL) for transmitting low-level DC signals, the second trace P702 is the first clock signal line (CK1) for transmitting the first clock signal, the third trace P703 is the second clock signal line (CK2) for transmitting the second clock signal, the fourth trace P704 is the third clock signal line (CK3) for transmitting the third clock signal, the fifth trace P705 is the fourth clock signal line (CK4) for transmitting the fourth clock signal, the sixth trace P706 and the ninth trace P709 are high-level DC signal lines (VGH) for transmitting high-level DC signals, the seventh trace P707 is the power supply line for transmitting the power supply signal, and the tenth trace P710 is the start signal line for transmitting the start signal, the eleventh trace P711 is the reset signal line for transmitting the first reset signal, the second trace P712 is the reset signal line for transmitting the second reset signal, and the thirteenth trace P713 is the reset signal line for transmitting the third reset signal.

[0101] Optionally, multiple devices of the driving unit are Figure 3The transistor and capacitor structures shown have the same circuit layout for the multiple devices in the effective driving unit 121 as that of the multiple devices in the virtual driving unit 122. The circuit layout of the multiple devices may include the relative positions and dimensions of the patterns of each layer of the multiple devices. The circuit layout of the multiple devices may further include the connection relationships of the patterns of other layers except for the active pattern P1, the first sub-pattern P501 of the first source-drain pattern P5, and the sixth capacitor structure C6 in the output module A2. In this way, the structural similarity between the effective driving unit 121 and the virtual driving unit 122 can be further improved, thereby improving the etching uniformity of the gate driving circuit 12.

[0102] In an exemplary embodiment, the display panel may further include at least one target structure to improve the etching uniformity. Please refer to Figure 20 , Figure 20 which is a schematic structural diagram of a part of another display panel provided by an embodiment of the present application. The display panel further includes at least one target structure 17, and the target structure 17 and the active layer 163 are of the same layer structure.

[0103] The target structure 17 satisfies at least one of the following conditions:

[0104] 1) For the setting position of a target structure 17, please refer to Figure 20 , and the orthographic projection of the target structure 17 on the substrate 11 is located between the orthographic projection of the first part 1631 of one transistor among the multiple transistors on the substrate 11 and the orthographic projection of the second part 1632 on the substrate 11.

[0105] 2) For the setting position of another target structure 17, please refer to Figure 21 , Figure 21 which is a schematic structural diagram of a part of another display panel provided by an embodiment of the present application. The orthographic projection of the target structure 17 on the substrate 11 is located on the side away from the second orthographic projection of the first orthographic projection. The first orthographic projection is the orthographic projection of the active layer 163 of one transistor among the multiple transistors on the substrate 11, and the second orthographic projection is the orthographic projection of the first pole 161 of the one transistor on the substrate 11.

[0106] The above two cases of the setting positions of the target structure 17 respectively correspond to Figure 7 and Figure 8 the two structures of the active layer 163 shown. The target structure 17 in both cases can fill the voids existing in the active layer, avoiding the influence of the voids on the pattern density, thereby improving the etching uniformity.

[0107] For different circuit structures, the cases of the setting positions of the target structure 17 are different. Corresponding to the circuit schematic diagram shown in Figure 3 , please refer to Figure 22 ,Figure 22 It is a schematic structural diagram of some structures in another display panel provided by an embodiment of the present application. The target structure 17 can be disposed on the side of the eighth sub-pattern P108 of the active pattern P1 close to the shift register module A1. This is because only a part of the eighth sub-pattern P108 (the active layer of the twelfth transistor T12) connected to the first pole is retained. Therefore, the gap Q1 formed by the active layer of the twelfth transistor T12 has a relatively large size. Exemplarily, the distance between the center of the target structure 17 and the adjacent active pattern P1 is greater than 1.5 micrometers, so that manufacturing can be facilitated. Moreover, there are gaps in the regions corresponding to the gap Q1 formed by the active layer of the twelfth transistor T12 in other layer patterns, so that the target structure 17 can be prevented from affecting the arrangement of other layer patterns, and the target structure 17 can be conveniently electrically connected to the DC signal line through the first source-drain pattern P5.

[0108] Optionally, please refer to Figure 22 , the display panel further includes an insulating layer P4 on the side of the active layer 163 away from the substrate 11. The insulating layer P4 has at least one first opening H1 corresponding to at least one target structure 17. The orthographic projection of the target structure 17 on the substrate 11 overlaps with the orthographic projection of the corresponding first opening H1 on the substrate 11. Since the number of openings in the corresponding insulating layer P4 also decreases when the active layer of the transistor is disconnected, setting the first opening H1 can improve the etching uniformity of the insulating layer P4. In addition, the DC signal line can be electrically connected to the target structure 17 through the first opening H1 and access a DC signal to the target structure 17, thereby reducing the risk of electrostatic breakdown of the target structure 17.

[0109] In an exemplary embodiment, the display panel further includes a plurality of clock signal lines and a plurality of first electrodes. Please refer to Figure 23 , Figure 23 It is a schematic structural diagram of some structures in another display panel provided by an embodiment of the present application. Figure 23It can be a partial structure on the display area of the substrate 11. The sub-pixel circuit 13 is electrically connected to the first electrode 131. The first electrode 131 corresponds to and is electrically connected to two of the plurality of clock signal lines 154. The first electrode 131 has a second opening H2. The orthographic projection of the second opening H2 of the first electrode 131 on the substrate 11 overlaps with the orthographic projection of the corresponding clock signal line 154 on the substrate 11. The plurality of first electrodes 131 are respectively anodes of a plurality of sub-pixels. The sub-pixel circuit 13 can be used to control the voltage of the first electrode 131. The plurality of clock signal lines 154 can be used to transmit clock signals to the first electrode 131. There is an organic layer between the first electrode 131 and the clock signal line 154 to play an insulating role. During the manufacturing process of the organic layer, there will be gases, such as water vapor or oxygen. The gases will cause the organic layer to bulge. By providing the second opening H2 on the first electrode 131, the second opening H2 can discharge these gases, thereby avoiding the influence of the bulging of the organic layer on the transmission of the clock signal by the clock signal line 154. In addition, a filling structure can be provided to fill the second opening H2, thereby increasing the flatness of the first electrode 131.

[0110] Optionally, the display panel further includes a pixel defining layer 18. The pixel defining layer 18 is located on the substrate 11. The pixel defining layer 18 includes a plurality of openings 181. The plurality of openings 181 respectively correspond to the plurality of first electrodes 131. The orthographic projection of the opening 181 on the substrate 11 overlaps with the orthographic projection of the corresponding first electrode 131 on the substrate 11. The plurality of openings 181 include a first opening 181 and a second opening 182. The first electrode 1311 corresponding to the first opening 181 is electrically connected to the clock signal line 154. The size of the first opening 181 is smaller than the size of the second opening 182, and the size of the second opening H2 of the first electrode 1311 corresponding to the first opening 181 is smaller than the size of the second opening H2 of the first electrode 1312 corresponding to the second opening 182. This is because the clock signal lines 154 are arranged more densely. Therefore, by reducing the area of the first electrode 1311 corresponding to the clock signal line 154, it can be ensured that the clock signal line 154 can be electrically connected to the corresponding first electrode 1311. And by setting the size of the second opening H2 corresponding to the first opening 181 to be smaller than the size of the second opening H2 corresponding to the second opening 182, it can be ensured that the effective area of the first electrode 131 is not too small, thereby avoiding affecting the light-emitting area.

[0111] Optionally, in the first direction X, the widths d3 of the portions where the first electrode 1311 corresponding to the first opening 181 contacts the corresponding two clock signal lines 154 are the same. The first direction X is a direction perpendicular to the extending direction of the clock signal line 154. In this way, the load uniformity of the two clock signal lines 154 electrically connected to the first electrode 131 can be improved, thereby improving the stability of the transmitted clock signal.

[0112] Optionally, in the first direction X, the range of the minimum distance d4 between the edge of the clock signal line 154 and the edge of the second opening H2 of the corresponding first electrode 1311 is: 0.5 micrometer to 1.0 micrometer. In this way, not only can the effective overlap between the clock signal line 154 and the corresponding first electrode 1311 be ensured, but also the second opening H2 can effectively discharge gas, avoiding the influence of gas on the transmission of the clock signal by the clock signal line 154.

[0113] In summary, the embodiment of the present application provides a display panel. Among them, the gate driving circuit of the display panel includes a plurality of cascaded driving units. The effective driving units among the plurality of driving units are electrically connected to the sub-pixel circuit, and the virtual driving units among the plurality of driving units are disconnected from the sub-pixel circuit. Then, the virtual driving units do not have an output function, and the virtual driving units can input shift signals for the corresponding effective driving units. Therefore, the virtual driving units provided in the present application have a partial structure similar to that of the effective driving units. In this way, the etching uniformity of the gate driving circuit can be improved to reduce the deviation in the line width and thickness of the traces formed by etching in different regions of the gate driving circuit, and the load uniformity of the shift signals accessed by the plurality of effective driving units can be improved, thereby improving the stability of the display panel.

[0114] On the other hand, the embodiment of the present application further provides a display device. The display device includes a housing and any one of the display panels provided in the above embodiments, and the display panel can be located in the housing. The display device can be various devices including a display function, such as a display, a television, a vertical advertising machine, a painting screen device, a mobile phone, various intelligent wearable devices, etc.

[0115] Since the display device includes the display panel provided in the above embodiments, the display device can also have a similar effect, that is, the stability of the display device can be improved.

[0116] In the present application, the term "at least one of A and B" is merely a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, at least one of A and B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Similarly, "at least one of A, B, and C" represents that there can be seven relationships, which can represent: A exists alone, B exists alone, C exists alone, A and B exist simultaneously, A and C exist simultaneously, C and B exist simultaneously, and A, B, and C exist simultaneously.

[0117] It should be noted that in the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. Also, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there can be an intermediate layer. Additionally, it is understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there can be more than one intermediate layer or element. Further, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there can also be more than one intermediate layer or element. Like reference numerals throughout the specification indicate like elements.

[0118] In this application, the terms "first", "second", "third" and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "plurality" refers to two or more, unless otherwise clearly defined.

[0119] The above are only alternative embodiments of this application and are not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes: a substrate, a gate driving circuit located on the substrate, and a plurality of sub-pixel circuits; The gate driving circuit includes a plurality of cascaded driving units. The plurality of driving units include a plurality of effective driving units and at least one virtual driving unit. Each of the effective driving units is electrically connected to at least one of the sub-pixel circuits. The virtual driving unit is disconnected from the sub-pixel circuits. Each of the virtual driving units includes a shift signal output terminal. Each of the effective driving units includes at least one shift signal input terminal. Each of the shift signal input terminals corresponds to and is electrically connected to a shift signal output terminal; Both the effective driving unit and the virtual driving unit include a shift register module and an output module. At least part of the structures of the output modules of the effective driving unit and the virtual driving unit are different.

2. The display panel according to claim 1, wherein The structure of the shift register module of the effective driving unit is the same as the structure of the shift register module of the virtual driving unit. The output module of the virtual driving unit includes a plurality of transistors. All of the plurality of transistors in the output module of the virtual driving unit are in a cut-off state.

3. The display panel according to claim 2, wherein The plurality of transistors in the output module of the virtual driving unit include a first pole, a second pole, and an active layer. One of the first pole and the second pole is a source electrode, and the other is a drain electrode; The active layer of the transistor includes a first part connected to the first pole and a second part connected to the second pole. The first part is disconnected from the second part.

4. The display panel according to claim 2, wherein The plurality of transistors in the output module of the virtual driving unit include a first pole, a second pole, and an active layer. One of the first pole and the second pole is a source electrode, and the other is a drain electrode; The active layer of the transistor is connected to the first pole, and the active layer of the transistor is disconnected from the second pole.

5. The display panel according to claim 2, wherein The plurality of transistors in the output module of the virtual driving unit include a first pole, a second pole, and an active layer. One of the first pole and the second pole is a source electrode, and the other is a drain electrode; The active layers of some of the plurality of transistors include a first part connected to the first pole and a second part connected to the second pole. The first part is disconnected from the second part; The active layers of the other part of the plurality of transistors are connected to the first pole, and the active layers of the other part of the plurality of transistors are disconnected from the second pole.

6. The display panel according to any one of claims 3 to 5, characterized in that, The display panel further includes a DC signal line located on the substrate. The active layers of the plurality of transistors in the output module of the virtual driving unit are all electrically connected to the DC signal line.

7. The display panel according to any one of claims 3 to 5, characterized in that, The display panel further includes at least one target structure. The target structure and the active layer are of the same layer structure; The target structure satisfies at least one of the following conditions: The target structure is located between the first part and the second part of one of the plurality of transistors; The orthographic projection of the target structure on the substrate is located on the side of the first orthographic projection away from the second orthographic projection. The first orthographic projection is the orthographic projection of the active layer of one of the plurality of transistors on the substrate, and the second orthographic projection is the orthographic projection of the first pole of the one transistor on the substrate.

8. The display panel according to claim 7, wherein The display panel further includes an insulating layer located on the side of the active layer away from the substrate. The insulating layer has at least one first opening corresponding to the at least one target structure, and there is an overlap between the orthographic projection of the target structure on the substrate and the orthographic projection of the corresponding first opening on the substrate.

9. The display panel according to any one of claims 3 to 5, characterized in that, The plurality of transistors of the output module of the virtual driving unit further includes gates. In one of the plurality of transistors, there is no overlap between the orthographic projection of the active layer on the substrate and the orthographic projection of the gate on the substrate.

10. The display panel according to claim 2, characterized in that, Both the effective driving unit and the output module of the virtual driving unit include a plurality of devices. The circuit layout of the plurality of devices in the effective driving unit is the same as the circuit layout of the plurality of devices in the virtual driving unit. The display panel further includes a DC signal line and a shift signal line located on the substrate. The plurality of devices include target devices. The target device of the effective driving unit includes a first electrode plate and a second electrode plate arranged in a direction away from the substrate. The first electrode plate is connected to the DC signal line, and the second electrode plate is connected to the shift signal line. The target device of the virtual driving unit and the second electrode plate are of the same layer structure. The target device of the virtual driving unit is connected to the shift signal line, and the target device of the virtual driving unit is disconnected from the DC signal line.

11. The display panel according to claim 1, wherein, The substrate includes a display area and a non-display area. The plurality of sub-pixel circuits are located on the display area, and the gate driving circuit is located on the non-display area. The distance between the virtual driving unit and the display area is equal to the distance between the effective driving unit and the display area.

12. The display panel according to claim 1, wherein The display panel further includes a plurality of clock signal lines and a plurality of first electrodes. The sub-pixel circuit is electrically connected to the first electrode. The first electrode corresponds to and is electrically connected to two of the plurality of clock signal lines. The first electrode has a second opening, and there is an overlap between the orthographic projection of the second opening of the first electrode on the substrate and the orthographic projection of the corresponding clock signal line on the substrate.

13. The display panel according to claim 12, wherein The display panel further includes a pixel defining layer located on the substrate. The pixel defining layer includes a plurality of openings, and the plurality of openings respectively correspond to the plurality of first electrodes. There is an overlap between the orthographic projection of the opening on the substrate and the orthographic projection of the corresponding first electrode on the substrate. The plurality of openings include a first opening and a second opening. The first electrode corresponding to the first opening is electrically connected to the clock signal line. The size of the first opening is smaller than the size of the second opening, and the size of the second opening of the first electrode corresponding to the first opening is smaller than the size of the second opening of the first electrode corresponding to the second opening.

14. The display panel according to claim 12, wherein In a first direction, which is perpendicular to the extending direction of the clock signal lines, the widths of the portions where the first electrode contacts the corresponding two clock signal lines are the same.

15. A display device, characterized in that, The display device includes a housing and the display panel according to any one of claims 1 to 14.

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