Multi-system amplitude shift keying modulation energy and signal synchronous transmission system

Abstract

The utility model discloses a multi-system amplitude shift keying modulation energy and signal synchronous transmission system, which comprises a direct current source, an inverter, an energy transmission topological structure, a load, a demodulation circuit and a digital signal processor (DSP) chip, the direct current source is electrically connected with the energy transmission topological structure through the inverter, the energy transmission topological structure is connected with the load, and the load is connected with the demodulation circuit. The energy transmission topological structure is electrically connected with the DSP chip through the demodulation circuit, in the multi-system amplitude shift keying modulation energy and signal synchronous transmission system, a pre-transmission modulation signal generates a PWM variable through the DSP, the PWM variable is directly superposed to a control end of an MOSEFT tube in a full-bridge inverter, and the PWM variable is converted into a PWM variable through the DSP. The phase shift angle of the inverter is controlled through the control circuit, so that the voltage amplitude is changed, M kinds of amplitude transformation are generated, energy and signals are transmitted to the receiving coil through the transmitting coil at the same time, the energy is transmitted to a load through a circuit, and the signals are restored through the current Hall sensor, the demodulation circuit and the DSP.

Description

Technical Field

[0001] The utility model relates to the technical field of wireless power transmission, and particularly relates to a multi - level amplitude - shift keying modulation energy and signal synchronous transmission system. Background Art

[0002] Wireless power transmission technology can achieve electrical isolation and is a power transmission method that transmits electrical energy from the power supply end to the electrical equipment without relying on physical media. Due to its convenient and flexible power transmission, it has a very attractive broad prospect. However, in practical applications, wireless power transmission technology needs to have functions such as real - time control of output power, signal transmission between the primary side and the secondary side, that is, energy and signal synchronous transmission technology.

[0003] There are usually two ways for energy and signal synchronous transmission, namely the separated - channel method and the shared - channel method. The separated - channel transmission method is to establish an additional channel on the basis of the energy - transmission channel. The shared - channel transmission method is essentially that the signal and energy share a transmission channel, which can be divided into two categories: carrier - modulation type and energy - modulation type. The former indirectly accesses the sending end and the receiving end of the system through a coupling transformer to complete the input and extraction of the signal; the latter mostly completes the signal transmission by changing the energy waveform, such as amplitude - modulation type, frequency - modulation type, etc. It has the advantages of simple system structure and avoiding cross - coupling between the two channels in the dual - channel transmission technology. However, there are also some deficiencies: slow signal transmission rate, output voltage fluctuation, etc. In view of the above deficiencies, a multi - level amplitude - shift keying modulation energy and signal synchronous transmission system based on a phase - shifted full - bridge is proposed. Summary of the Utility Model

[0004] In order to overcome the above - mentioned deficiencies, the utility model provides a multi - level amplitude - shift keying modulation energy and signal synchronous transmission system.

[0005] The utility model realizes the above object through the following technical solutions:

[0006] A multi - level amplitude - shift keying modulation energy and signal synchronous transmission system includes a DC source, an inverter, an energy - transmission topology, a load, a demodulation circuit, and a DSP chip. The DC source is electrically connected to the energy - transmission topology through the inverter. The energy - transmission topology is connected to the load, and the energy - transmission topology is electrically connected to the DSP chip through the demodulation circuit;

[0007] The energy transmission topology includes a primary emission circuit and a secondary reception circuit. The primary emission circuit includes an emission coil, a first parasitic resistor, and a first compensation capacitor. The two ends of the series circuit composed of the emission coil, the first parasitic resistor, and the first compensation capacitor are electrically connected to the output terminals of the inverter respectively. The secondary reception circuit includes a reception coil, a second parasitic resistor, and a second compensation capacitor. The two ends of the series circuit composed of the reception coil, the second parasitic resistor, and the second compensation capacitor are electrically connected to the load. The demodulation circuit is coupled to the series circuit composed of the reception coil, the second parasitic resistor, and the second compensation capacitor. The emission coil is wirelessly connected to the reception coil.

[0008] This system does not have a DC-DC modulation circuit, which reduces the impact of passive devices on the system and improves the baud rate. Without the pre-filtering of the DC-DC circuit, it can transmit data with a higher bit width, thereby improving the signal transmission rate. It adopts the multi-level amplitude shift keying modulation method, and electric energy does not interfere with the signal. The designed demodulation circuit is combined with the DSP for application, and the voltage amplitude fluctuation at the receiving end is controlled within about 5%, minimizing the impact of the fluctuation on the load as much as possible.

[0009] Preferably, the inverter is a phase-shifted full-bridge inverter. The phase-shifted full-bridge inverter includes a voltage source, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first diode, a second diode, a third diode, and a fourth diode. The first MOS transistor and the first diode are anti-parallel connected, the second MOS transistor and the second diode are anti-parallel connected, the third MOS transistor and the third diode are anti-parallel connected, the fourth MOS transistor and the fourth diode are anti-parallel connected. The first MOS transistor and the second MOS transistor form a leading leg, and the third MOS transistor and the fourth MOS transistor form a lagging leg. The voltage source is electrically connected to the gates of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor respectively.

[0010] Preferably, the demodulation circuit includes a voltage division circuit, a rectification circuit, a voltage follower circuit, an envelope detection circuit, a low-pass filter circuit, a differential amplifier circuit, a low-pass filter circuit, and a protection circuit connected in sequence.

[0011] Preferably, the current source is a DC switching power supply module.

[0012] Preferably, the capacitance values of the first compensation capacitor and the second compensation capacitor are 40 nF, the self-inductance value of the emission coil is 282 μH, and the self-inductance value of the reception coil is 283 μH.

[0013] The beneficial effects of the present utility model are as follows: In this multi - level amplitude - shift keying modulation energy and signal synchronous transmission system, the pre - transmitted modulation signal is used to generate a PWM variable through a DSP, which is directly superimposed on the control terminal of the MOSEFT tube in the full - bridge inverter to control the phase - shift angle of the inverter, thereby changing the voltage amplitude and generating M kinds of amplitude transformations. The energy and the signal are simultaneously transmitted to the receiving coil through the transmitting coil, the energy is transmitted to the load through the circuit, and the signal is restored by using a current Hall sensor, a demodulation circuit and a DSP. Description of the Drawings

[0014] The present utility model will be described by way of examples and with reference to the drawings, where:

[0015] Figure 1 is the structural diagram of the energy and signal synchronous transmission system of the present utility model;

[0016] Figure 2 is the working waveform diagram of the phase - shift full - bridge inverter of the present utility model;

[0017] Figure 3 is the circuit schematic diagram of the demodulation circuit of the present utility model. Detailed Embodiment

[0018] Now, the present utility model will be further described in detail with reference to the drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present utility model in a schematic way, so they only show the components related to the present utility model.

[0019] As Figure 1 shown, a multi - level amplitude - shift keying modulation energy and signal synchronous transmission system includes a DC source, an inverter, an energy transmission topology, a load, a demodulation circuit and a DSP chip. The DC source is electrically connected to the energy transmission topology through the inverter, the energy transmission topology is connected to the load, and the energy transmission topology is electrically connected to the DSP chip through the demodulation circuit;

[0020] The energy transmission topology includes a primary transmitting circuit and a secondary receiving circuit. The primary transmitting circuit includes a transmitting coil Lp, a first parasitic resistance Rp and a first compensation capacitor Cp. The two ends of the series circuit composed of the transmitting coil Lp, the first parasitic resistance Rp and the first compensation capacitor Cp are respectively electrically connected to the output terminals of the inverter. The secondary receiving circuit includes a receiving coil Ls, a second parasitic resistance Rs and a second compensation capacitor Cs. The two ends of the series circuit composed of the receiving coil Ls, the second parasitic resistance Rs and the second compensation capacitor Cs are connected to the load. The demodulation circuit is coupled to the series circuit composed of the receiving coil Ls, the second parasitic resistance Rs and the second compensation capacitor Cs, and the transmitting coil Lp is wirelessly connected to the receiving coil Ls.

[0021] Let the impedance of the primary-side circuit be \(Z_1\), and write the impedance equation of the transmitting end of the S-S type topology:

[0022] (1)

[0023] Let the impedance of the secondary-side circuit be Z s , and write the impedance equation of the receiving end of the S-S type topology:

[0024] (2)

[0025] Let Z r be the equivalent impedance (secondary side mapped to the primary side), and write the mapped impedance equation of the S-S type topology:

[0026] (3)

[0027] Let the total impedance of the primary-side circuit be Z p , and the total impedance Z p of the primary side of the circuit can be expressed as:

[0028] (4)

[0029] To ensure that the secondary-side circuit is in the resonant condition and remains purely resistive, the compensation capacitor C s is:

[0030] (5)

[0031] The primary-side circuit should also remain purely resistive and operate in the resonant state. The compensation capacitor C p is:

[0032] (6)

[0033] The current I p of the primary-side circuit and the current I s of the secondary-side circuit are expressed as:

[0034] (7)

[0035] The total input power of the system is:

[0036] (8)

[0037] The output power of the system is:

[0038] (9)

[0039] The efficiency of the system is:

[0040] (10)

[0041] Figure 2 is the waveform output when the full-bridge inverter works normally. The DSP generates four pulse-width modulation signals for the driving signals of the MOSFETs. The waveforms of the control signals of the MOSFETs are as Figure 2 a and Figure 2 shown in b, where the dotted lines in Figures a and b are US3 and US4, and α is the phase-shift angle. Figure 2 c and d are the output voltage and current waveforms of the full-bridge inverter respectively.

[0042] Let the turn-on time φ of S4 be the initial phase point. The output voltage Up of the inverter can be expressed as

[0043] (11)

[0044] where U d is the voltage of the DC voltage source. Performing Fourier series expansion on Equation (11), we can obtain

[0045] (12)

[0046] Therefore, the k th harmonic effective value of the inverter output voltage is

[0047] (13)

[0048] It can be known from Equation (13) that under the condition of a constant current source, because the resonant compensation capacitor Cp is added to the primary circuit, the high-order harmonics are filtered out, and only the fundamental wave is retained to transfer energy. As the phase-shift angle of the phase-shifted full-bridge continuously increases, the duty cycle of the voltage output by the inverter will continuously decrease to 0. That is, by controlling the phase-shift angle between the leading bridge arm and the lagging bridge arm of the phase-shifted full-bridge inverter, the effective value of the inverted voltage output by the system can be changed, and the electric energy is transmitted to the receiving coil Ls through the transmitting coil Lp, thereby adjusting the energy coupled to the receiving end, making the receiving-end voltage linearly change with the phase-shift angle. The changed voltage amplitude corresponds to the transmitted signal, forming a comprehensive energy signal flow, realizing MASK modulation, and achieving the purpose of simultaneous energy and information transmission.

[0049] According to Equation (9), it can be obtained that when phase-shift control is performed, the output power of the system is

[0050] (14)

[0051] According to Equation (8), the total input efficiency of the system when phase-shift control is performed can be obtained as

[0052] (15)

[0053] The transmission efficiency of the system is

[0054] (16)

[0055] It can be seen from Equations (14), (15), and (16) that when the phase-shift angle is changed, the transmission power of the system will be affected, but the transmission efficiency of the system will not be affected. Therefore, during the co-transmission of energy and information, while ensuring the transmission rate and controlling the bit error rate, the fluctuation of the output power should be minimized as much as possible to reduce the impact of the electrical energy fluctuation on the load.

[0056] As a specific embodiment, the inverter is a phase-shifted full-bridge inverter. The phase-shifted full-bridge inverter includes a voltage source, a first MOS transistor S1, a second MOS transistor S2, a third MOS transistor S3, a fourth MOS transistor S4, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first MOS transistor S1 and the first diode D1 are anti-parallelly connected, the second MOS transistor S2 and the second diode D2 are anti-parallelly connected, the third MOS transistor S3 and the third diode D3 are anti-parallelly connected, the fourth MOS transistor S4 and the fourth diode D4 are anti-parallelly connected. The first MOS transistor S1 and the second MOS transistor S2 form a leading leg, and the third MOS transistor S3 and the fourth MOS transistor S4 form a lagging leg. The voltage source is electrically connected to the gates of the first MOS transistor S1, the second MOS transistor S2, the third MOS transistor S3, and the fourth MOS transistor S4 respectively.

[0057] As a specific embodiment, the demodulation circuit includes a voltage division circuit, a rectification circuit, a voltage follower circuit, an envelope detection circuit, a low-pass filter circuit, a differential amplifier circuit, a low-pass filter circuit, and a protection circuit connected in sequence.

[0058] Among them, the voltage dividing circuit includes a first resistor R1 and a second resistor R2, the rectifying circuit includes a fifth diode D5 and a third resistor R3, the voltage follower circuit includes a first operational amplifier and a fourth resistor R4, the envelope detection circuit includes a sixth diode D6, a fifth resistor R5 and a first capacitor C1, the low-pass filtering circuit includes a sixth resistor R6 and a second capacitor C2, the differential amplification circuit includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and a second operational amplifier, the low-pass filtering circuit includes an eleventh resistor R11 and a third capacitor C3, the protection circuit includes a seventh diode D7, an eighth diode D8, a triode Q1, a field effect transistor Q2, a twelfth resistor R12, a thirteenth resistor R13 and a fourteenth resistor R14. One end of the series circuit composed of the receiving coil Ls, the second parasitic resistor Rs and the second compensation capacitor Cs is grounded through the first resistor R1 and the second resistor R2. The anode of the fifth diode D5 is electrically connected to the first resistor R1 and the second resistor R2 respectively. The cathode of the fifth diode D5 is grounded through the third resistor R3. The cathode of the fifth diode D5 is electrically connected to the non-inverting input terminal of the first operational amplifier. The inverting input terminal of the first operational amplifier is electrically connected to the anode of the sixth diode D6 through the fifth resistor R5. The cathode of the sixth diode D6 is grounded through the parallel circuit composed of the fifth resistor R5 and the first capacitor C1. The cathode of the sixth diode D6 is grounded through the sixth resistor R6 and the second capacitor C2. The cathode of the sixth diode D6 is electrically connected to the non-inverting input terminal of the second operational amplifier through the sixth resistor R6 and the seventh resistor R7. The inverting input terminal of the second operational amplifier is grounded through the ninth resistor R9. The inverting input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier through the tenth resistor R10. The output terminal of the second operational amplifier is grounded through the eleventh resistor R11 and the third capacitor C3. The output terminal of the second operational amplifier is electrically connected to the emitter of the triode Q1 and the drain of the field effect transistor Q2 respectively. The emitter of the triode Q1 is electrically connected to the cathode of the seventh diode D7 through the twelfth resistor R12. The base of the triode Q1 is electrically connected to the anode of the seventh diode D7 through the thirteenth resistor R13. The collector of the triode Q1 is electrically connected to the anode of the seventh diode D7 through the fourteenth resistor R14. The collector of the triode Q1 is electrically connected to the drain of the field effect transistor Q2 and the cathode of the eighth diode D8 respectively. The anode of the eighth diode D8 is electrically connected to the source of the field effect transistor Q2. The first operational amplifier and the second operational amplifier form an integrated circuit, and the model of the integrated circuit is LM2904.

[0059] The signal demodulation is jointly realized by the demodulation circuit and the DSP. The demodulation circuit is as Figure 3As shown, it includes structures such as voltage division, rectification, voltage following, envelope detection, low-pass filtering, differential amplification, and protection. First, the voltage collected by the current Hall sensor is input into the demodulation circuit. First, voltage division is performed to protect the chip and devices. After passing through the rectification circuit and voltage follower, the main circuit is isolated from the subsequent demodulation circuit to reduce interference. Through envelope detection, the amplitude change of the high-frequency signal is detected. The selection of the time constant RC is very important. After low-pass filtering, the differential amplifier will differentially amplify the signal voltage with a very small change amount to fully display the signal characteristics of the voltage. Uref can be obtained by dividing the supply voltage Uo of the chip. After the processed voltage passes through low-pass filtering, it enters the protection circuit. The zener diode D7 with a voltage of 2.7V is selected. When the input voltage does not exceed 2.7V, Q1 is not turned on, there is a voltage drop across the GS of Q2, and it is turned on, and the voltage is normally output. When the voltage is greater than 2.7V, the zener diode D7 is turned on. When the exceeded voltage value is greater than the turn-on voltage of the PN junction of Q1, Q1 is turned on. The turned-on voltage makes the GS voltages at both ends of Q2 equal, and the voltage drop is offset, forming an open circuit, and the output stops, playing a protective role.

[0060] Signals can be obtained by comparing and judging the data or using algorithms. In this system, all the collected data is stored in an array, and the data in the array is compared and judged to obtain signals.

[0061] As a specific embodiment, the current source is a DC switching power supply module, and the DC switching power supply module includes overvoltage protection and overcurrent protection.

[0062] As a specific embodiment, the capacitance values of the first compensation capacitor Cp and the second compensation capacitor Cs are 40 nF, the self-inductance value of the transmitting coil Lp is 282 μH, and the self-inductance value of the receiving coil Ls is 283 μH.

[0063] Based on the inspiration of the present invention, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A multi - level amplitude - shift keying modulation energy and signal synchronous transmission system, characterized in that: It includes a DC source, an inverter, an energy transmission topology, a load, a demodulation circuit, and a DSP chip. The DC source is electrically connected to the energy transmission topology through the inverter. The energy transmission topology is connected to the load, and the energy transmission topology is electrically connected to the DSP chip through the demodulation circuit; The energy transmission topology includes a primary transmitting circuit and a secondary receiving circuit. The primary transmitting circuit includes a transmitting coil, a first parasitic resistor, and a first compensation capacitor. The two ends of the series circuit composed of the transmitting coil, the first parasitic resistor, and the first compensation capacitor are respectively electrically connected to the output terminals of the inverter. The secondary receiving circuit includes a receiving coil, a second parasitic resistor, and a second compensation capacitor. The two ends of the series circuit composed of the receiving coil, the second parasitic resistor, and the second compensation capacitor are electrically connected to the load. The demodulation circuit is coupled to the series circuit composed of the receiving coil, the second parasitic resistor, and the second compensation capacitor. The transmitting coil is wirelessly connected to the receiving coil.

2. The multi - level amplitude - shift keying modulation energy and signal synchronous transmission system according to claim 1, wherein: The inverter is a phase-shifted full-bridge inverter. The phase-shifted full-bridge inverter includes a voltage source, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first diode, a second diode, a third diode, and a fourth diode. The first MOS transistor and the first diode are anti-parallel connected. The second MOS transistor and the second diode are anti-parallel connected. The third MOS transistor and the third diode are anti-parallel connected. The fourth MOS transistor and the fourth diode are anti-parallel connected. The first MOS transistor and the second MOS transistor form a leading leg, and the third MOS transistor and the fourth MOS transistor form a lagging leg. The voltage source is respectively electrically connected to the gates of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor.

3. The multi - level amplitude - shift keying modulation energy and signal synchronous transmission system according to claim 1, characterized in that: The demodulation circuit includes a voltage division circuit, a rectification circuit, a voltage follower circuit, an envelope detection circuit, a low-pass filter circuit, a differential amplifier circuit, a low-pass filter circuit, and a protection circuit connected in sequence.

4. The multi - level amplitude - shift keying modulation energy and signal synchronous transmission system according to claim 1, characterized in that: The DC source is a DC switching power supply module.

5. The multi - level amplitude - shift keying modulation energy and signal synchronous transmission system according to claim 1, wherein: The capacitance values of the first compensation capacitor and the second compensation capacitor are 40 nF. The self-inductance value of the transmitting coil is 282 μH, and the self-inductance value of the receiving coil is 283 μH. The resonant frequency and the operating frequency of the system are 47.3 kHz. Through the DSP chip, according to different transmission signals, the phase shift angle of the corresponding PWM of the leading leg and the lagging leg of the phase-shifted full-bridge inverter is controlled to achieve signal modulation.

Images