Memory device

Abstract

A memory device comprises a substrate, a plurality of metallization layers, a plurality of memory units and bit lines. A plurality of metallization layers is disposed over the substrate. Each memory unit comprises a transistor and a capacitor. The bit lines are coupled to a corresponding group of the plurality of memory cells. The bit line includes at least a first conductive line structure and a second conductive line structure extending along a first lateral direction and disposed in a first metallization layer of the plurality of metallization layers. The first conductive line structure and the second conductive line structure are physically spaced apart from each other, but electrically coupled to each other by one or more conductive line structures disposed in the plurality of metallization layers.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having twisted bit lines. Background Art

[0002] Due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, the iterative reduction of the minimum feature size enables an increase in integration density, allowing more components to be integrated into a given area. Summary of the Utility Model

[0003] One aspect of the present disclosure discloses a memory device. The memory device includes a substrate, a plurality of metallization layers, a plurality of memory cells, and bit lines. The plurality of metallization layers are disposed above the substrate. Each memory cell includes a transistor and a capacitor. The bit lines are coupled to a corresponding set of the plurality of memory cells. The bit lines include at least a first wire structure and a second wire structure, which extend along a first lateral direction and are disposed in a first metallization layer of the plurality of metallization layers. The first wire structure and the second wire structure are physically spaced apart from each other, but are electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers.

[0004] Another aspect of the present disclosure discloses a memory device. The memory device includes a plurality of memory cells and bit lines. The memory cells are disposed on one or more metallization layers above the substrate. The bit lines are operatively coupled to a corresponding set of the plurality of memory cells. The bit lines are at least composed of a first wire structure and a second wire structure disposed in a first metallization layer of the plurality of metallization layers. The first wire structure and the second wire structure are physically spaced apart from each other, but are electrically coupled to each other through one or more other wire structures.

[0005] Another aspect of the present disclosure discloses a memory device. The memory device includes a substrate, a plurality of metallization layers, a transistor, a bit line, and a capacitor. The plurality of metallization layers are located above the substrate. The transistor is disposed above a first metallization layer of the metallization layers. The bit line is disposed in a second metallization layer of the metallization layers, wherein the bit line is operatively coupled to a first source / drain terminal of the transistor. The capacitor is disposed above the bit line, wherein the capacitor is operatively coupled to a second source / drain terminal of the transistor. Wherein the bit line includes at least a first wire structure and a second wire structure, and wherein the first wire structure and the second wire structure are physically spaced apart from each other, but are electrically coupled to each other through one or more other wire structures. Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for the sake of clarity in discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 Block diagram showing a memory device including a plurality of back-end-of-line (BEOL) memory cells according to some embodiments;

[0008] Figure 2 Shown according to some embodiments Figure 1 Circuit diagram of one of the BEOL memory cells of the memory device shown;

[0009] Figure 3 Shown according to some embodiments Figure 2 Perspective view of the BEOL memory cell shown;

[0010] Figure 4 Shown according to some embodiments including a plurality of Figure 2 Perspective view of a memory array including BEOL memory cells shown;

[0011] Figure 5 Shown according to some embodiments including a plurality of Figure 2 Cross-sectional view of a memory device including BEOL memory cells shown;

[0012] Figures 6 to 14 Various exemplary layouts of multiple twisted bit lines of a memory are shown according to some embodiments;

[0013] Figure 15 Schematic diagram of a twisted bit line is shown according to some embodiments;

[0014] Figure 16 Shown according to some embodiments corresponding to Figure 15 Exemplary layout of the schematic diagram shown;

[0015] Figure 17 Schematic diagram of a twisted bit line is shown according to some embodiments;

[0016] Figure 18 Shown according to some embodiments corresponding to Figure 17 Exemplary layout of the schematic diagram shown;

[0017] Figure 19 Schematic diagram of a twisted bit line is shown according to some embodiments;

[0018] Figure 20 Shown according to some embodiments corresponding to Figure 19 Exemplary layout of the schematic diagram shown;

[0019] Figure 21 A flowchart showing an exemplary method for manufacturing a memory device according to some embodiments.

[0020] [Symbol Explanation]

[0021] 100: Memory device

[0022] 102: Memory array

[0023] 103: Memory cell

[0024] 104: Row decoder

[0025] 106: Column decoder

[0026] 108: I / O circuit

[0027] 110: Control logic circuit

[0028] 200, 200A, 200B, 200C: Memory cells

[0029] 202: Access transistor

[0030] 202A, 202B, 202C: Transistors

[0031] 204: Capacitor

[0032] 210: First wire structure

[0033] 212: Dielectric layer

[0034] 214: Channel layer

[0035] 216: Second wire structure

[0036] 218: Third wire structure

[0037] 220: Via structure

[0038] 222, 222A, 222B, 222C: WL

[0039] 224, 224A, 224B, 224C, 224D: BL

[0040] 226: Via structure

[0041] 400: Memory array

[0042] 500: Memory device

[0043] 502: Substrate

[0044] 504: First transistor

[0045] 506: Second transistor

[0046] 508: Third transistor

[0047] 510: Between M5 and M6

[0048] 600: Layout

[0049] 601: Via structure

[0050] 602: First BL

[0051] 602A, 652A: First end

[0052] 602B, 652B: Second end

[0053] 603: Via structure

[0054] 612, 614, 616, 622, 624, 626: Conductor structure

[0055] 620, 660: Power path

[0056] 652: Second BL

[0057] 700: Layout

[0058] 701, 703, 705: Via structure

[0059] 702: First BL

[0060] 702A, 752A: First end

[0061] 702B, 752B: Second end

[0062] 712, 714, 716: Conductor structure

[0063] 720, 760: Power path

[0064] 722: Conductor structure

[0065] 752: Second BL

[0066] 800: Layout

[0067] 801, 805: Via structure

[0068] 802: First BL

[0069] 802A, 852A: First end

[0070] 802B, 852B: Second end

[0071] 812, 822: Conductor structure

[0072] 820,860: Power path

[0073] 852: Second BL

[0074] 900: Layout

[0075] 902: First BL

[0076] 902A,932A,952A,972A: First end

[0077] 902B,932B,952B,972B: Second end

[0078] 905: Through-hole structure

[0079] 912,942,962,982: Conductor structure

[0080] 920,940,960,980: Power path

[0081] 932: Second BL

[0082] 952: Third BL

[0083] 972: Fourth BL

[0084] 1000: Layout

[0085] 1001,1005: Through-hole structure

[0086] 1002: First BL

[0087] 1002A,1052A: First end

[0088] 1002B,1052B: Second end

[0089] 1012,1022: Conductor structure

[0090] 1020,1060: Power path

[0091] 1052: Second BL

[0092] 1100: Layout

[0093] 1101,1105: Through-hole structure

[0094] 1102: First BL

[0095] 1102A,1132A,1152A,1172A: First end

[0096] 1102B,1132B,1152B,1172B: Second end

[0097] 1112, 1142, 1162, 1182: Conductor structure

[0098] 1120, 1140, 1160, 1180: Power path

[0099] 1132: Second BL

[0100] 1152: Third BL

[0101] 1172: Fourth BL

[0102] 1200: Layout

[0103] 1202: First BL

[0104] 1202A, 1252A: First end

[0105] 1202B, 1252B: Second end

[0106] 1205: Via structure

[0107] 1212: Conductor structure

[0108] 1220, 1260: Power path

[0109] 1252: Second BL

[0110] 1252C: Third part

[0111] 1300: Layout

[0112] 1302: First BL

[0113] 1302A: First end

[0114] 1302B: Second end

[0115] 1305: Via structure

[0116] 1312: Conductor structure

[0117] 1312A, 1312B: A pair of parts

[0118] 1312C: Midpoint part

[0119] 1352: Second BL

[0120] 1352A: First end

[0121] 1352B: Second end

[0122] 1352C: Third part

[0123] 1400: Layout

[0124] 1402: First BL

[0125] 1402A: First End

[0126] 1402B: Second End

[0127] 1405: Through-Hole Structure

[0128] 1412,1414: Conductor Structure

[0129] 1416: BG

[0130] 1418: WL

[0131] 1420,1460: Power Path

[0132] 1452: Second BL

[0133] 1452A: First End

[0134] 1452B: Second End

[0135] 1452C: Third Part

[0136] 1501: Noise Source

[0137] 1502A,1532A,1562A: End

[0138] 1502B,1532B,1562B: End

[0139] 1502C,1532C,1562C: Middle Part

[0140] 1600: Layout

[0141] 1701: Noise Source

[0142] 1702A,1732A,1762A: End

[0143] 1702B,1732B,1762B: End

[0144] 1702C,1732C,1762C: End

[0145] 1702D,1732D,1762D: Middle Part

[0146] 1702E,1732E,1762E: Middle Part

[0147] 1800: Layout

[0148] 1901: Noise Source

[0149] 1902A,1932A,1962A,1992A: End

[0150] 1902B, 1932B, 1962B, 1992B: End

[0151] 1902C, 1932C, 1962C, 1992C: Middle part

[0152] 2000: Layout

[0153] 2100: Method

[0154] 2102, 2104, 2106: Operations

[0155] M0, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10: Metallization layers

[0156] BG: Back gate

[0157] BL: Bit line

[0158] C1, C2, C3, C4, CN: Columns

[0159] D: Drain

[0160] G: Gate

[0161] R1, R2, R3, RM: Rows

[0162] S: Source

[0163] WL: Word line

[0164] X: Direction

[0165] Y: Direction Detailed implementation manners

[0166] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following describes specific examples of components and arrangements to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming the first feature above or on the second feature below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the disclosure may repeat reference numerals and / or letters in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0167] In addition, for ease of description, the present disclosure may use spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., to describe the relationship of one element or feature to one or more other elements or features, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0168] Many electronic products require different amounts of memory devices (e.g., memory bit cells or memory cells) to store information, such as data. A common configuration of a memory bit cell consists of an access transistor and a capacitor connected in series electrically, sometimes referred to as a one-transistor-one-capacitor (1T1C) cell. Data can be stored in the memory cell during a write mode, or data can be retrieved from the memory cell during a read mode. The source / drain terminals of the access transistor of the memory cell are connected to an internal signal line, sometimes referred to as a bit line or digital line. The gate terminal of the access transistor of the memory cell is connected to an addressing line, sometimes referred to as a word line. The word line selects the access transistor to conduct, and the bit line is thus coupled to the corresponding capacitor via the sensing (e.g., conducting) channel of the access transistor.

[0169] A thin-film transistor (TFT) is a field-effect transistor that includes a channel layer, a gate terminal, and source / drain terminals located on a substrate that supports but does not conduct electricity. TFTs are different from traditional transistors, where the channels of traditional transistors are typically formed within a substrate such as a silicon substrate, formed from the substrate, or formed based on the substrate. By integrating TFTs into the back-end-of-line (BEOL) network while leaving the silicon substrate area for high-speed transistors, TFTs have become an attractive option for pushing Moore's law. TFTs can be used as access transistors for memory cells. Memories containing such memory cells are sometimes referred to as BEOL memory devices. However, the design and implementation of current BEOL memory devices still face many challenges. For example, the bit lines of BEOL memory devices are typically arranged as parallel wires in a single metallization layer. With this configuration, noise coupled to one of the bit lines can easily be coupled to other bit lines, which may undesirably reduce the performance of BEOL memory devices.

[0170] The present disclosure provides various embodiments of a BEOL memory device including a plurality of memory cells, each memory cell being composed of a transistor and a capacitor. The BEOL memory device may also include a plurality of bit lines, each bit line being operatively coupled to a corresponding set of memory cells. In various embodiments of the present disclosure, these bit lines may be "twisted", where each bit line is based on including a plurality of different portions physically spaced apart from each other. The term "twisted bit line" as disclosed herein may refer to a plurality of bit lines that respectively have some portions overlapping each other when viewed from the top. For example, the first bit line may include at least a first end portion and a second end portion, which are respectively implemented as a first wire and a second wire of a first BEOL metallization layer; the second bit line may include at least a third end portion and a fourth end portion, which are respectively implemented as a third wire and a fourth wire of the first BEOL metallization layer. In addition, one or more other different portions may be respectively included in the first bit line and the second bit line, where these different portions are coupled to their corresponding end portions, and may be configured such that these different portions span one or more other BEOL metallization layers. By configuring the bit lines in this way, even if there is noise and the noise is coupled to a specific bit line, the noise can be spread out through different portions of the bit line to further reduce the coupling between different bit lines. Therefore, the performance of the BEOL memory device disclosed herein can be significantly improved.

[0171] Figure 1 A exemplary block diagram of a semiconductor (e.g., memory) device 100 is shown according to various embodiments. In Figure 1 the illustrated embodiment, the memory device 100 includes a memory array 102, a row decoder 104, a column decoder 106, an input / output (I / O) circuit 108, and a control logic circuit 110. Although not explicitly shown in Figure 1 it, the elements of the memory device 100 are operatively coupled to each other and to the control logic circuit 110. For example, the control logic circuit 110, the I / O circuit 108, the column decoder 106, and the row decoder 104 may be electrically coupled to the memory array 102. Although for the purpose of clear illustration, in Figure 1 the illustrated example, the elements are shown as separate blocks, but in some other embodiments, Figure 1 some or all of the elements shown in

[0172] The memory array 102 is a hardware component that stores data. In one embodiment, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other storage units) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ..., each extending along a first direction (e.g., the X direction). M and a plurality of columns C1, C2, C3 . . . C extending along the second direction. N (e.g., Y direction). Each row / column may include one or more conductive structures. In some embodiments, each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column and can be operated based on the voltage or current passing through the corresponding conductive structures of the column and row.

[0173] Row decoder 104 is a hardware component that can receive a row address of memory array 102 and assert a conductive structure (e.g., a word line) at the row address. Column decoder 106 is a hardware component that can receive a column address of memory array 102 and assert one or more conductive structures (e.g., a bit line, a source line) at the column address. I / O circuitry 108 is a hardware component that can access (e.g., read, program) each memory cell 103 asserted by row decoder 104 and column decoder 106. Control logic circuitry 110 is a hardware component that can control the coupling of components (e.g., memory array 102 to I / O circuitry 108).

[0174] Figure 2 According to some embodiments, it can be Figure 1 The example configuration of the memory cell 200 is shown as an example of the memory cell 103. Figure 2 In the example of FIG, memory cell 200 is implemented as a one-transistor-one-capacitor (1T1C) configuration, e.g., access transistor 202 and capacitor 204 are coupled in series with each other. Specifically, access transistor 202 may have a source / drain terminal electrically coupled to one of the terminals of capacitor 204, the other source / drain terminal of access transistor 202 is electrically connected to a bit line (BL), and a gate terminal is electrically coupled to a word line (WL).

[0175] In some embodiments of the present disclosure, the memory cell 200 can be operatively configured as a dynamic random access memory (DRAM) cell. However, it should be understood that the memory cell 200 can be operatively configured as any of a variety of other memory configurations, such as a ferroelectric random access memory (FeRAM) cell, a spin-transfer torque magnetic RAM (STT-RAM) cell, a phase change RAM (PCRAM) cell, etc., while remaining within the scope of the present disclosure.

[0176] To access (e.g., program, read) the memory cell 200, an access transistor 202 (if implemented as an n-type transistor) is turned on by applying a signal (e.g., voltage) corresponding to a high logic state, and via a word line WL, to a gate terminal of the access transistor 202. Simultaneously or subsequently, a signal (e.g., a pulse signal) is applied to a drain terminal of the access transistor 202 via a bit line BL. When the access transistor 202 is turned on, access to the memory cell 200 is permitted. For example, a (e.g., programming, read) path can be provided from the bit line BL through the access transistor 202 to the capacitor 204.

[0177] According to various embodiments of the present disclosure, the access transistor 202 and the capacitor 204 are formed on the same side of a semiconductor substrate, e.g., the front side of the semiconductor substrate. Additionally, both the access transistor 202 and the capacitor 204 are formed across one or more metallization layers and are disposed above a front-side surface of the semiconductor substrate, such as M0, M1, M2, M3, M4, M5, M6, etc. Each metallization layer includes multiple wires (e.g., metal lines) embedded in one or more inter-layer dielectrics (ILD) or inter-metal dielectrics (IMD). The ILD / IMD can include one or more of a low-k dielectric layer (i.e., a dielectric having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide). Such metallization layers can be collectively referred to as a back-end-of-line (BEOL) network. Thus, the memory cell 200 is sometimes referred to as the BEOL memory cell 200.

[0178] According to various embodiments, Figure 3 A perspective view of an exemplary configuration of such a (forming) BEOL memory cell 200 is shown, and Figure 4 A perspective view of a memory array 400 including multiple formed BEOL memory cells 200 is shown. It should be noted that, Figure 3 In relation toFigure 4 It may be simplified and thus one or more elements may not be explicitly shown.

[0179] First, referring to Figure 3 , in some embodiments, access transistor 202 may be formed as a thin-film transistor (TFT) structure, and furthermore, the access transistor may be configured as a back-gate transistor. For example, in Figure 3 , access transistor 202 may include a first wire structure 210, a dielectric layer 212 disposed above the first wire structure 210, a semiconductive-behaving layer 214 disposed above the dielectric layer 212, and a second wire structure 216 and a third wire structure 218 disposed above the channel layer 214. The first wire structure 210 can operably serve as the gate terminal (sometimes referred to as the back-gate “BG”) of access transistor 202, the dielectric layer 212 can effectively serve as the gate dielectric of access transistor 202, the semiconductive-behaving layer 214 can serve as the channel of access transistor 202, and the second wire structure 216 and the third wire structure 218 can operably serve as the source terminal (sometimes referred to as “S”) and the drain terminal (sometimes referred to as “D”) of access transistor 202.

[0180] Each element of access transistor 202 (such as wire structures 210 to 218) may be formed within one layer of a metallization layer or between two adjacent metallization layers, such as between metallization layers M5 and M6. The wire structures 210, 216, and 218 may include tungsten, copper, gold, cobalt, ruthenium, or a combination thereof. The dielectric layer 212 may include one or more layers of a high-k dielectric layer (i.e., a dielectric having a dielectric constant greater than about 3.9), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, etc., or a combination thereof. The semiconductive-behaving layer 214 may include semiconductive-behaving oxide materials, such as IGZO, InZnO, InSnO, SnO2, MgAlZnO, CuO, SnO, oxides of the cuprite group Cu-X-O with or without doping, or a combination thereof.

[0181] Although Figure 3Although not explicitly shown in the figure, the capacitor 204 may be formed as a metal-insulator-metal (MIM) or metal-oxide-metal (MOM) structure disposed above the access transistor 202. The capacitor 204 may be electrically coupled to the access transistor 202 (or its drain terminal, such as the wire structure 218) through a via structure 220. For example, the capacitor 204 may include a capacitor dielectric layer inserted between a bottom electrode and a top electrode. The bottom / top electrode may include tungsten, copper, gold, cobalt, ruthenium, or a combination thereof; the capacitor dielectric layer therebetween may include one or more layers of high-k dielectric layers, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, etc., or a combination thereof. For the access transistor 202 formed between the metallization layers M5 and M6, each element of the capacitor 204 may be formed within another metallization layer or between two adjacent metallization layers above the metallization layer M6, for example, between the metallization layers M6 and M7.

[0182] Still referring to Figure 3 , the gate terminal of the access transistor 202 (e.g., the wire structure 210) is coupled to WL222 through a via structure (not shown). For example, WL222 may be formed within a metallization layer (e.g., the metallization layer M5) below the access transistor 202 and extend along a first lateral direction (e.g., the Y direction). The source terminal of the access transistor 202 (e.g., the wire structure 216) is coupled to BL224 through a via structure 226. For example, in Figure 3 , at least a part of BL224 may be formed within a metallization layer (e.g., the metallization layer M6) above the transistor 202 and extend along a second lateral direction (e.g., the X direction). According to various embodiments of the present disclosure, BL224 may include a plurality (e.g., 2) of ends physically spaced apart from each other within a metallization layer but electrically coupled to each other through one or more wire structures disposed on one or more other metallization layers, which will be discussed in further detail with reference to Figures 6 to 14 Further details will be discussed.

[0183] Next, referring to Figure 4 , the memory array 400 includes a plurality of BEOL memory cells 200 configured in a plurality of rows and columns. Figure 4Shows the corresponding transistors of some BEOL memory cells 200, such as transistors 202A, 202B, and 202C, while the corresponding capacitors of the memory cells are collectively shown as capacitor 204. Memory array 400 also includes WLs 222A, 222B, and 222C (which may respectively correspond to rows R1, R2, and R3) and BLs 224A, 224B, 224C, and 224D (which may respectively correspond to columns C1, C2, C3, and C4). In some embodiments, the WLs (such as 222A to 222C) may be disposed within metallization layer M5 and extend along a first lateral direction (such as the Y direction); and the BLs (such as 224A to 224D) may each include portions disposed in metallization layer M6 and extend along a second lateral direction perpendicular to the first lateral direction (such as the X direction). In Figure 4 In an exemplary embodiment, the memory cells of memory array 400 may share a common back gate BG, where each subset of the memory cells is disposed along a respective row sharing the common WL, and each subset of the memory cells is disposed along a respective column sharing the common BL.

[0184] Figure 5 According to various embodiments, a cross-sectional view of a memory device 500 (being formed) including the above-mentioned references Figures 2 to 4 is shown discussing a plurality of BEOL memory cells 200. For example, memory device 500 may include Figure 4 the memory array 400. In addition, memory device 500 may include a plurality of other structures operable as the elements discussed in Figure 1 such as I / O circuit 108, control logic circuit 110, etc.

[0185] As shown, memory device 500 may be divided into a plurality of portions / sections that are laterally disposed relative to each other, such as an array portion, a boundary portion, a transition portion, and a logic portion. These portions may be formed above substrate 502. Along the main surface of substrate 502, a plurality of first transistors 504, second transistors 506, and third transistors 508 are respectively formed in the array portion, the boundary portion, and the logic portion. Transistors 504 to 508 may form part of a front-end-of-line (FEOL) network. On the FEOL network, memory device 500 includes a plurality of metallization layers, such as M0, M1, M2, M4, M5, M6, M7, M8, M9, and M10, which are formed as part of a back-end-of-line (BEOL) network.

[0186] In the array portion, the memory device 500 may include a plurality of BEOL memory cells (e.g., BEOL memory cells 200A, 200B, 200C, etc.). Each of the memory cells 200A to 200C is composed of a corresponding transistor 202 formed between metallization layers M5 and M6 and a corresponding capacitor 204 formed between metallization layers M6 and M7. In some embodiments, the BEOL memory cells may be formed as a memory array, and the BEOL memory cells can be operably accessed through WLs (e.g., WL222A, 222B, 222C, etc.) and BLs (e.g., BL224A, etc.). In Figure 5 's cross-sectional view, WL222A to 222C are disposed in the metallization layer M5, and BL224A is disposed in the metallization layer M6. However, according to various embodiments of the present disclosure, the ends of BL224A (and other BLs) may be disposed in the metallization layer M6 and also have some other portions disposed in other metallization layers, which causes the BLs to twist with each other. In addition, the first transistor 504 disposed in the array portion can be operably used as one or more WL drivers of the memory array (e.g., Figure 1 a part of the column decoder 104 of). The second transistor 506 disposed in the boundary portion can be operably used as one or more sense amplifiers of the memory array (e.g., Figure 1 a part of the I / O circuit 108 of). The third transistor 508 disposed in the logic portion can be operably used as one or more control circuits of the memory array (e.g., Figure 1 a part of the control logic circuit 110 of).

[0187] Figure 6 According to some embodiments, an exemplary layout 600 is shown, which includes a first BL602 and a second BL652 configured in a twisted manner, e.g., (when viewed from the top) one or more portions of each of them overlap each other. Each of the first BL602 and the second BL652 can be operably coupled to a corresponding number of BEOL memory cells (e.g., Figure 2 the memory cell 200 of).

[0188] As shown in the figure, the first BL602 includes a first end 602A and a second end 602B that are spaced apart from each other, and the second BL652 includes a first end 652A and a second end 652B that are spaced apart from each other. Each of the first ends 602A and 652A and the second ends 602B and 652B extends along the X direction. In addition, the projections of the first end 602A and the second end 602B (of the first BL602) are spaced apart in the Y direction, and the projections of the first end 652A and the second end 652B (of the second BL652) are spaced apart in the Y direction. In other words, the projections of the first end 602A and the second end 602B are parallel to each other, and the projections of the first end 652A and the second end 652B are parallel to each other.

[0189] Regarding the first BL602, even though the first end 602A and the second end 602B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures provided in one or more metallization layers. For example, the first end 602A is coupled to the wire structure 612 (provided in the metallization layer M5) through one of the via structures 601, the wire structure 612 is coupled to the wire structure 614 (provided in the metallization layer M4) through one of the via structures 603, the wire structure 614 is coupled to the wire structure 616 (provided in the metallization layer M5) through another via structure 603, and the wire structure 616 is coupled to the second end 602B via another via structure 601.

[0190] In this way, the power path 620 can be formed at least by the first end 602A being in the metallization layer M6, the wire structure 612 being in the metallization layer M5, the wire structure 614 being in the metallization layer M4, the wire structure 616 being in the metallization layer M5 again, and the second end 602B being in the metallization layer M6 again. In some embodiments, the power path 620 can be operationally equivalent to the first BL602. In other words, the first BL602 can operationally include the first end 602A, the wire structure 612, the wire structure 614, the wire structure 616, and the second end 602B.

[0191] Regarding the second BL652, even though the first end 652A and the second end 652B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures provided in one or more metallization layers.

[0192] For example, the first end portion 652A is coupled to the wire structure 622 (disposed in the metallization layer M5) through one of the via structures 601, and the wire structure 622 is coupled to the wire structure 624 (disposed in the metallization layer M4) through the high via structure 603. The wire structure 624 is coupled to the wire structure 626 (disposed in the metallization layer M5) through another via structure 603, and the wire structure 626 is coupled to the second end portion 652B via another via structure 601.

[0193] In this way, the power path 660 can be formed at least by the first end portion 652A being in the metallization layer M6, the wire structure 622 being in the metallization layer M5, the wire structure 624 being in the metallization layer M4, the wire structure 626 being again in the metallization layer M5, and the second end portion 652B being again in the metallization layer M6. In some embodiments, the power path 660 can be operationally equivalent to the second BL652. In other words, the second BL652 can operationally include the first end portion 652A, the wire structure 622, the wire structure 624, the wire structure 626, and the second end portion 652B.

[0194] In Figure 6 embodiments, the wire structures (e.g., 602A, 602B, 652A, 652B) formed in the metallization layer M6 can extend in the X direction, the wire structures (e.g., 612, 622, 616, 626) formed in the metallization layer M5 can extend in the Y direction, and the wire structures (e.g., 614, 624) formed in the metallization layer M4 can extend in the X direction. When one or more "intermediate" portions are disposed in the metallization layer and extend in a different direction from the ends, different BLs, such as BL602 (or equivalent path 620) and BL652 (or equivalent path 660), can be twisted.

[0195] Figure 7 According to some embodiments, an exemplary layout 700 is shown, which includes a first BL702 and a second BL752 configured in a twisted manner, for example (when viewed from the top), one or more portions of each of them overlap with each other. Each of the first BL702 and the second BL752 can be operably coupled to a corresponding number of BEOL memory cells (e.g., Figure 2 memory cells 200) of

[0196] As shown in the figure, the first BL702 includes a first end 702A and a second end 702B spaced apart from each other, and the second BL752 includes a first end 752A and a second end 752B spaced apart from each other. Each of the first ends 702A and 752A and the second ends 702B and 752B extends in the X direction. In addition, the first end 702A of the first BL702 and the second end 702B of the first BL702 are spaced apart in projection in the Y direction, and the first end 752A of the second BL752 and the second end 752B of the second BL752 are spaced apart in projection in the Y direction. In other words, the projections of the first end 702A and the second end 702B are parallel to each other, and the projections of the first end 752A and the second end 752B are parallel to each other.

[0197] Regarding the first BL702, even though the first end 702A and the second end 702B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures provided in one or more metallization layers. For example, the first end 702A is coupled to the wire structure 712 (provided in the metallization layer M5) through one of the via structures 701, the wire structure 712 is coupled to the wire structure 714 (provided in the metallization layer M4) through one of the via structures 703, the wire structure 714 is coupled to the wire structure 716 (provided in the metallization layer M5) through another via structure 703, and the wire structure 716 is coupled to the second end 702B through another via structure 701.

[0198] In this way, the power path 720 can be formed at least by the first end 702A being in the metallization layer M6, the wire structure 712 being in the metallization layer M5, the wire structure 714 being in the metallization layer M4, the wire structure 716 being again in the metallization layer M5, and the second end 702B being again in the metallization layer M6. In some embodiments, the power path 720 can be operationally equivalent to the first BL702. In other words, the first BL702 can operationally include the first end 702A, the wire structure 712, the wire structure 714, the wire structure 716, and the second end 702B.

[0199] Regarding the second BL752, even though the first end 752A and the second end 752B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures provided in one or more metallization layers. For example, the first end 752A is coupled to the wire structure 722 (provided between the metallization layers M5 and M6 at 510) through one of the via structures 705, and the wire structure 722 is coupled to the second end 752B via another via structure 705. In some embodiments, the wire structure 722 can be used as a source terminal or a drain terminal of one or more BEOL memory cells (e.g., Figure 2of the wire structures 216, 218).

[0200] In this way, the power path 760 can be formed by at least a first end 752A in the metallization layer M6, a wire structure 722 between the metallization layers M5 and M6, and a second end 752B again in the metallization layer M6. In some embodiments, the power path 760 can be operationally equivalent to the second BL752. In other words, the second BL752 operably includes a first end 752A, a wire structure 722, and a second end 752B.

[0201] In Figure 7 embodiments, the wire structures formed in the metallization layer M6 (e.g., 702A, 702B, 752A, 752B) can extend along the X direction, the wire structures formed in the metallization layer M5 (e.g., 712, 716) can extend along the Y direction, the wire structures formed in the metallization layer M4 (e.g., 714) can extend along the X direction, and the wire structures formed between the metallization layers M5 and M6 (e.g., 722) can extend along the Y direction. When one or more "intermediate" portions are provided in the metallization layer and extend in a different direction from the ends, different BLs, such as BL702 (or equivalent path 720) and BL752 (or equivalent path 760), can be twisted.

[0202] Figure 8 According to some embodiments, an exemplary layout 800 is shown, which includes a first BL802 and a second BL852 configured in a twisted manner, e.g., (when viewed from the top) one or more portions of each of them overlap each other. Each of the first BL802 and the second BL852 can be operably coupled to a corresponding number of BEOL memory cells (e.g., Figure 2 memory cells 200).

[0203] As shown, the first BL802 includes a first end 802A and a second end 802B spaced apart from each other, and the second BL852 includes a first end 852A and a second end 852B spaced apart from each other. Each of the first ends 802A and 852A and the second ends 802B and 852B extends along the X direction. In addition, the first end 802A of the first BL802 is projected and spaced apart from the second end 802B of the first BL802 along the Y direction, and the first end 852A of the second BL852 is projected and spaced apart from the second end 852B of the second BL852 along the Y direction. In other words, the projections of the first end 802A and the second end 802B are parallel to each other, and the projections of the first end 852A and the second end 852B are parallel to each other.

[0204] Regarding the first BL802, even though the first end portion 802A and the second end portion 802B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers. For example, the first end portion 802A is coupled to a wire structure 812 (disposed in the metallization layer M5) through one of the via structures 801, and the wire structure 812 is coupled to the second end portion 802B via another via structure 801.

[0205] In this way, the power path 820 can be formed at least by the first end portion 802A in the metallization layer M6, the wire structure 812 in the metallization layer M5, and the second end portion 802B which is again in the metallization layer M6. In some embodiments, the power path 820 can be operationally equivalent to the first BL802. In other words, the first BL802 can operationally include the first end portion 802A, the wire structure 812, and the second end portion 802B.

[0206] Regarding the second BL852, even though the first end portion 852A and the second end portion 852B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers. For example, the first end portion 852A is coupled to a wire structure 822 (disposed between the metallization layers M5 and M6 at 510) through one of the via structures 805, and the wire structure 822 is coupled to the second end portion 852B via another via structure 805. In some embodiments, the wire structure 822 can be used as a source terminal or a drain terminal of one or more BEOL memory cells (e.g., Figure 2 the wire structures 216, 218).

[0207] In this way, the power path 860 can be formed at least by the first end portion 852A in the metallization layer M6, the wire structure 822 between the metallization layers M5 and M6, and the second end portion 852B which is again in the metallization layer M6. In some embodiments, the power path 860 can be operationally equivalent to the second BL852. In other words, the second BL852 operably includes the first end portion 852A, the wire structure 822, and the second end portion 852B.

[0208] In Figure 8In embodiments, wire structures (e.g., 802A, 802B, 852A, 852B) formed in metallization layer M6 may extend along the X direction, wire structures (e.g., 812) formed in metallization layer M5 may be formed as islands spanning along the X and Y directions, and wire structures (e.g., 822) formed in metallization layer M4 may extend along the Y direction. When one or more "intermediate" portions are provided in the metallization layer and extend in different directions from the ends, different BLs, such as BL802 (or equivalent path 820) and BL852 (or equivalent path 860), may be twisted.

[0209] Figure 9 According to some embodiments, an exemplary layout 900 is shown, which includes a first BL902, a second BL932, a third BL952, and a fourth BL972 configured in a twisted manner, e.g., one or more corresponding portions thereof (when viewed from the top) overlap each other. Each of the first BL902, the second BL932, the third BL952, and the fourth BL972 can be operably coupled to a corresponding number of BEOL memory cells (e.g., Figure 2 memory cells 200).

[0210] As shown, the first BL902 includes a first end 902A and a second end 902B spaced apart from each other, the second BL932 includes a first end 932A and a second end 932B spaced apart from each other, the third BL952 includes a first end 952A and a second end 952B spaced apart from each other, and the fourth BL972 includes a first end 972A and a second end 972B spaced apart from each other. Each of the first ends 902A, 932A, 952A, and 972A and the second ends 902B, 932B, 952B, and 972B extend along the X direction. Additionally, the projection of the first end 902A (of the first BL902) is spaced apart from the projection of the second end 902B (of the first BL902) along the Y direction, and the other BLs have a similar configuration.

[0211] Regarding the first BL902, the first end 902A and the second end 902B can be electrically coupled to each other through a plurality of wire structures provided in one or more metallization layers even though they are physically separated in the same metallization layer M6. For example, the first end 902A is coupled to a wire structure 912 (provided in metallization layer M5) through one of the via structures 901, and the wire structure 912 is coupled to the second end 902B through another via structure 901.

[0212] As such, the power path 920 can be formed by at least a first end 902A in the metallization layer M6, a wire structure 912 in the metallization layer M5, and a second end 902B in the metallization layer M6. In some embodiments, the power path 920 can be operationally equivalent to the first BL902. In other words, the first BL902 can operationally include the first end 902A, the wire structure 912, and the second end 902B.

[0213] Regarding the second BL932, the first end 932A and the second end 932B can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers even though they are physically separated in the same metallization layer M6. For example, the first end 932A is coupled to a wire structure 942 (disposed between the metallization layers M5 and M6 at 510) through one of the via structures 905, and the wire structure 942 is coupled to the second end 932B through another via structure 905. In some embodiments, the wire structure 942 can act as a source terminal or a drain terminal of one or more BEOL memory cells (e.g., Figure 2 the wire structures 216, 218).

[0214] As such, the power path 940 can be formed by at least a first end 932A in the metallization layer M6, a wire structure 942 between the metallization layers M5 and M6, and a second end 932B again in the metallization layer M6. In some embodiments, the power path 940 can be operationally equivalent to the second BL932. In other words, the second BL932 operably includes the first end 932A, the wire structure 942, and the second end 932B.

[0215] For the third BL952, the first end 952A and the second part 952B can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers even though they are physically separated in the same metallization layer M6. For example, the first end 952A is coupled to a wire structure 962 (disposed in the metallization layer M5) through one of the via structures 901, and the wire structure 962 is coupled to the second end 952B via another via structure 901.

[0216] As such, the power path 960 can be formed by at least a first end 952A in the metallization layer M6, a wire structure 962 in the metallization layer M5, and a second end 952B in the metallization layer M6. In some embodiments, the power path 960 can be operationally equivalent to the third BL952. In other words, the third BL952 operably includes the first end 952A, the wire structure 962, and the second end 952B.

[0217] Regarding the fourth BL972, the first end portion 972A and the second end portion 972B can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers even though they are physically separated in the same metallization layer M6. For example, the first end portion 972A is coupled to a wire structure 982 (disposed between the metallization layers M5 and M6 at 510) through one of the via structures 905, and the wire structure 982 is coupled to the second end portion 972B through another via structure 905. In some embodiments, the wire structure 982 can be used as a source terminal or a drain terminal of one or more BEOL memory cells (e.g., Figure 2 the wire structures 216, 218).

[0218] In this way, the power path 980 can be formed at least by the first end portion 972A in the metallization layer M6, the wire structure 982 between the metallization layers M5 and M6, and the second end portion 972B again in the metallization layer M6. In some embodiments, the power path 980 can be operationally equivalent to the fourth BL972. In other words, the fourth BL972 operably includes the first end portion 972A, the wire structure 982, and the second end portion 972B.

[0219] In Figure 9 embodiments, the wire structures formed in the metallization layer M6 (e.g., 902A, 902B, 932A, 932B, 952A, 952B, 972A, 972B) can extend in the X direction, the wire structures formed in the metallization layer M5 (e.g., 912, 962) can each be formed to have an L-shaped profile, which consists of a first part extending in the X direction and a second part extending in the Y direction, and the wire structures formed between the metallization layers M5 and M6 (e.g., 942, 982) can extend in the Y direction. When one or more "intermediate" portions are disposed in the metallization layer and extend in a different direction from the end portions, different BLs, such as 902 (or equivalent path 920), 932 (or equivalent path 940), 952 (or equivalent path 960), and 972 (or equivalent path 980), can be twisted.

[0220] Figure 10 According to some embodiments, an exemplary layout 1000 is shown, which includes a first BL1002 and a second BL1052 configured in a twisted manner, e.g., (when viewed from the top) one or more parts of each of them overlap each other. Each of the first BL1002 and the second BL1052 can be operably coupled to a corresponding number of BEOL memory cells (e.g., Figure 2 the memory cells 200).

[0221] As shown in the figure, the first BL1002 includes a first end 1002A and a second end 1002B spaced apart from each other, and the second BL1052 includes a first end 1052A and a second end 1052B spaced apart from each other. Each of the first ends 1002A and 1052A and the second ends 1002B and 1052B extends in the X direction. In addition, in the Y direction, the projection of the first end 1002A of the first BL1002 is spaced apart from the projection of the second end 1002B of the first BL1002, and in the Y direction, the projection of the first end 1052A of the second BL1052 is spaced apart from the projection of the second end 1052B of the second BL1052. In other words, the projections of the first end 1002A and the second end 1002B are parallel to each other, and the projections of the first end 1052A and the second end 1052B are parallel to each other.

[0222] Regarding the first BL1002, even though the first end 1002A and the second end 1002B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers. For example, the first end 1002A is coupled to the wire structure 1012 (disposed between the metallization layers M5 and M6) through one of the via structures 1001, and the wire structure 1012 is coupled to the second end 1002B via another via structure 1001. In some embodiments, the wire structure 1012 can be used as the gate terminal or BG of one or more BEOL memory cells (e.g., Figure 2 the wire structure 210).

[0223] In this way, the power path 1020 can be formed at least by the first end 1002A in the metallization layer M6, the wire structure 1012 between the metallization layers M5 and M6, and the second end 1002B in the metallization layer M6. In some embodiments, the power path 1020 can be operationally equivalent to the first BL1002. In other words, the first BL1002 operably includes the first end 1002A, the wire structure 1012, and the second end 1002B.

[0224] Regarding the second BL1052, even though the first end 1052A and the second end 1052B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers. For example, the first end 1052A is coupled to the wire structure 1022 (disposed between the metallization layers M5 and M6 510) through one of the via structures 1005, and the wire structure 1022 is coupled to the second end 1052B through another via structure 1005. In some embodiments, the wire structure 1022 can be used as the source terminal or drain terminal of one or more BEOL memory cells (e.g., Figure 2of the wire structures 216, 218).

[0225] In this way, the power path 1060 can be formed by at least the first end 1052A in the metallization layer M6, the wire structure 1022 between the metallization layers M5 and M6, and the second end 1052B in the metallization layer M6. In some embodiments, the power path 1060 can be operationally equivalent to the second BL1052. In other words, the second BL1052 operably includes the first end 1052A, the wire structure 1022, and the second end 1052B.

[0226] In Figure 10 embodiments, the wire structures (e.g., 1002A, 1002B, 1052A, 1052B) formed in the metallization layer M6 can extend in the X direction, the wire structure (e.g., 1012) formed between the metallization layers M5 and M6 can be formed as an island spanning in the X and Y directions, and other wire structures (e.g., 1022) formed between the metallization layers M5 and M6 can extend in the Y direction. When one or more "intermediate" portions are disposed in the metallization layer and extend in a different direction from the ends, different BLs, such as BL1002 (or equivalent path 1020) and BL1052 (or equivalent path 1060), can be twisted.

[0227] Figure 11 According to some embodiments, an exemplary layout 1100 is shown, which includes a first BL1102, a second BL1132, a third BL1152, and a fourth BL1172 configured in a twisted manner, e.g., (when viewed from the top) one or more portions of each of them overlap each other. Each of the first BL1102, the second BL1132, the third BL1152, and the fourth BL1172 can be operably coupled to a corresponding number of BEOL memory cells (e.g., Figure 2 memory cells 200).

[0228] As shown in the figure, the first BL 1102 includes a first end 1102A and a second end 1102B that are spaced apart from each other. The second BL 1132 includes a first end 1132A and a second end 1132B that are spaced apart from each other. The third BL 1152 includes a fourth BL 1172 that includes a first end 1152A and a second end 1152B that are spaced apart from each other, and the fourth BL 1172 includes a first end 1172A and a second end 1172B that are spaced apart from each other. Each of the first ends 1102A, 1132A, 1152A, and 1172A and the second ends 1102B, 1132B, 1152B, and 1172B extend in the X direction. In addition, the projection of the first end 1102A of the (first BL 1102) in the Y direction is spaced apart from the projection of the second end 1102B of the (first BL 1102), and the other BLs are configured similarly.

[0229] Regarding the first BL 1102, even though the first end 1102A and the second end 1102B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures provided in one or more metallization layers. For example, the first end 1102A is coupled to the wire structure 1112 (provided between the metallization layers M5 and M6) through one of the via structures 1101, and the wire structure 1112 is coupled to the second end 1102B through another via structure 1101. In some embodiments, the wire structure 1112 can be used as the gate terminal or BG of one or more BEOL memory cells (e.g., Figure 2 the wire structure 210).

[0230] In this way, the power path 1120 can be formed at least by the first end 1102A in the metallization layer M6, the wire structure 1112 between the metallization layers M5 and M6, and the second end 1102B in the metallization layer M6. In some embodiments, the power path 1120 can be operationally equivalent to the first BL 1102. In other words, the first BL 1102 operably includes the first end 1102A, the wire structure 1112, and the second end 1102B.

[0231] Regarding the second BL 1132, even though the first end 1132A and the second end 1132B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures provided in one or more metallization layers. For example, the first end 1132A is coupled to the wire structure 1142 (provided between the metallization layers M5 and M6) through one of the via structures 1105, and the wire structure 1142 is coupled to the second end 1132B through another via structure 1105. In some embodiments, the wire structure 1142 can be used as the source terminal or drain terminal of one or more BEOL memory cells (e.g., Figure 2of the wire structures 216, 218).

[0232] In this way, the power path 1140 can be formed by at least the first end 1132A in the metallization layer M6, the wire structure 1142 between the metallization layers M5 and M6, and the second end 1132B in the metallization layer M6. In some embodiments, the power path 1140 can be operationally equivalent to the second BL 1132. In other words, the second BL 1132 operably includes the first end 1132A, the wire structure 1142, and the second end 1132B.

[0233] Regarding the third BL 1152, the first end 1152A and the second end 1152B can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers even if they are physically separated in the same metallization layer M6. For example, the first end 1152A is coupled to the wire structure 1162 (disposed between the metallization layers M5 and M6) through one of the via structures 1101, and the wire structure 1162 is coupled to the second end 1152B through another via structure 1101.

[0234] In this way, the power path 1160 can be formed by at least the first end 1152A in the metallization layer M6, the wire structure 1162 in the metallization layer M5, and the second end 1152B in the metallization layer M6. In some embodiments, the power path 1160 can be operationally equivalent to the third BL 1152. In other words, the third BL 1152 operably includes the first end 1152A, the wire structure 1162, and the second end 1152B.

[0235] Regarding the fourth BL 1172, the first end 1172A and the second end 1172B can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers even if they are physically separated in the same metallization layer M6. For example, the first end 1172A is coupled to the wire structure 1182 (disposed between the metallization layers M5 and M6) through one of the via structures 1105, and the wire structure 1182 is coupled to the second end 1172B through another via structure 1105. In some embodiments, the wire structure 1182 can be used as a source terminal or a drain terminal of one or more BEOL memory cells (e.g., Figure 2 of the wire structures 216, 218).

[0236] Accordingly, the power path 1180 can be formed by at least a first end portion 1172A in the metallization layer M6, a wire structure 1182 between the metallization layers M5 and M6, and a second end portion 1172B in the metallization layer M6. In some embodiments, the power path 1180 can be operationally equivalent to the fourth BL 1172. In other words, the fourth BL 1172 operably includes the first end portion 1172A, the wire structure 1182, and the second end portion 1172B.

[0237] In Figure 11 embodiments, wire structures (e.g., 1102A, 1102B, 1132A, 1132B, 1152A, 1152B, 1172A, 1172B) formed in the metallization layer M6 can extend in the X direction, wire structures (e.g., 1112, 1162) formed between the metallization layers M5 and M6 can each be formed in an L-shaped profile, which consists of a first part extending in the X direction and a second part extending in the Y direction, and wire structures (e.g., 1142, 1182) formed between the metallization layers M5 and M6 can extend in the Y direction. When one or more "intermediate" parts are provided in the metallization layer and extend in a different direction from the end portions, different BLs, such as BL1102 (or equivalent path 1120), BL1132 (or equivalent path 1140), BL1152 (or equivalent path 1160), and BL1172 (or equivalent path 1180), can be twisted.

[0238] Figure 12 Exemplary layout 1200 is shown according to some embodiments, which includes a first BL 1202 and a second BL 1252 configured in a twisted manner, e.g., (when viewed from the top) one or more parts of each of them overlap each other. Each of the first BL 1202 and the second BL 1252 can be operably coupled to a corresponding number of BEOL memory cells (e.g., Figure 2 memory cells 200).

[0239] As shown, the first BL 1202 includes a first end portion 1202A and a second end portion 1202B spaced apart from each other, and the second BL 1252 includes a first end portion 1252A, a second end portion 1252B, and a third part 1252C connecting the first end portion 1252A and the second end portion 1252B. Each of the first end portions 1202A and 1252A and the second end portions 1202B and 1252B extend in the X direction, while the third part 1252C extends in the Y direction. In addition, the projection of the first end portion 1202A (of the first BL 1202) in the Y direction is spaced apart from the projection of the second end portion 1202B (of the first BL 1202), and the projection of the first end portion 1252A (of the second BL 1252) in the Y direction is spaced apart from the projection of the second end portion 1252B (of the second BL 1252).

[0240] Regarding the first BL1202, even though the first end portion 1202A and the second end portion 1202B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers. For example, the first end portion 1202A is coupled to a wire structure 1212 (disposed between the metallization layers M5 and M6) through one of the via structures 1205, and the wire structure 1212 is coupled to the second end portion 1202B through another via structure 1205. In some embodiments, the wire structure 1212 can be used as a source terminal or a drain terminal of one or more BEOL memory cells (e.g., Figure 2 the wire structures 216, 218).

[0241] In this way, the power path 1220 can be formed at least by the first end portion 1202A in the metallization layer M6, the wire structure 1212 between the metallization layers M5 and M6, and the second end portion 1202B in the metallization layer M6. In some embodiments, the power path 1220 can be operationally equivalent to the first BL1202. In other words, the first BL1202 operably includes the first end portion 1202A, the wire structure 1212, and the second end portion 1202B.

[0242] Regarding the second BL1252, even though the first end portion 1252A and the second end portion 1252B are physically separated in the same metallization layer M6, they can be physically coupled to each other through the third portion 1252C. For example, the first end portion 1252A is connected to one end of the third portion 1252C, and the second end portion 1052B is connected to the other end of the third portion 1252C.

[0243] In this way, the power path 1260 can be formed at least by the first end portion 1252A in the metallization layer M6, the third portion 1252C, and the second end portion 1252B. In some embodiments, the power path 1260 can be operationally equivalent to the second BL1252. In other words, the second BL1252 operably includes the first end portion 1252A, the third portion 1252C, and the second end portion 1252B.

[0244] In Figure 12In embodiments, wire structures (e.g., 1202A, 1202B, 1252A, 1252B, 1252C) formed in metallization layer M6 can extend in the X direction or the Y direction, and wire structures (e.g., 1212) formed between metallization layers M5 and M6 can be formed as islands spanning in the X and Y directions. When one or more "intermediate" portions are provided in the metallization layer and extend in a different direction from the ends, different BLs, such as 1202 (or equivalent path 1220) and 1252 (or equivalent path 1260), can be twisted.

[0245] Figure 13 According to some embodiments, an exemplary layout 1300 is shown, which includes a first BL 1302 and a second BL 1352 configured in a twisted manner, e.g., (when viewed from the top) one or more portions of each of them overlap each other. Each of the first BL 1302 and the second BL 1352 can be operatively coupled to a corresponding number of BEOL memory cells (e.g., Figure 2 memory cells 200).

[0246] As shown, the first BL 1302 includes a first end 1302A and a second end 1302B spaced apart from each other, and the second BL 1352 includes a first end 1352A, a second end 1352B, and a third portion 1352C connecting the first end 1352A and the second end 1352B. Each of the first ends 1302A and 1352A and the second ends 1302B and 1352B extends in the X direction, while the third portion 1352C extends in the Y direction. In addition, the projection of the first end 1302A (of the first BL 1302) in the Y direction is spaced apart from the projection of the second end 1302B (of the first BL 1302), and the projection of the first end 1352A (of the second BL 1352) in the Y direction is spaced apart from the projection of the second end 1352B (of the second BL 1352).

[0247] Regarding the first BL 1302, the first end 1302A and the second portion 1302B can be electrically coupled to each other through a plurality of wire structures provided in one or more metallization layers even though they are physically separated in the same metallization layer M6. For example, the first end 1302A is coupled to a wire structure 1312 (provided between metallization layers M5 and M6) through one of the via structures 1305, and the wire structure 1312 is coupled to the second end 1302B through another via structure 1305. In some embodiments, the wire structure 1312 can be used as a source terminal or a drain terminal of one or more BEOL memory cells (e.g., Figure 2 wire structures 216, 218).

[0248] Thus, the power path 1320 can be formed by at least a first end portion 1302A in the metallization layer M6, a wire structure 1312 between the metallization layers M5 and M6, and a second end portion 1302B again in the metallization layer M6. In some embodiments, the path 1320 can be operationally equivalent to the first BL 1302. In other words, the first BL 1302 operably includes the first end portion 1302A, the wire structure 1312, and the second end portion 1302B.

[0249] Regarding the second BL 1352, the first end portion 1352A and the second end portion 1352B can be physically coupled to each other through a third portion 1352C even if they are physically separated in the same metallization layer M6. For example, the first end portion 1352A is connected to one end of the third portion 1352C, and the second end portion 1352B is connected to the other end of the third portion 1352C.

[0250] In this way, the power path 1360 can be formed by at least the first end portion 1352A, the third portion 1352C, and the second end portion 1352B in the metallization layer M6. In some embodiments, the power path 1360 can be operationally equivalent to the second BL 1352. In other words, the second BL 1352 operably includes the first end portion 1352A, the third portion 1352C, and the second end portion 1352B.

[0251] In Figure 13 embodiments, the wire structures (e.g., 1302A, 1302B, 1352A, 1352B, 1352C) formed in the metallization layer M6 can extend in the X direction or the Y direction, and the wire structure (e.g., the wire structure 1312) formed between the metallization layers M5 and M6 can be formed in an H-shaped profile, which consists of a pair of portions (e.g., 1312A and 1312B) extending in the Y direction and a corresponding midpoint portion (e.g., 1312C) extending in the X direction and connecting this pair of portions. When one or more "intermediate" portions are disposed in the metallization layer and extend in a different direction from the end portions, different BLs, such as 1302 (or the equivalent path 1320) and 1352 (or the equivalent path 1360), can be twisted.

[0252] Figure 14 According to some embodiments, an exemplary layout 1400 is shown, which includes a first BL 1402 and a second BL 1452 configured in a twisted manner, for example (when viewed from the top), one or more portions of each of them overlap with each other. Each of the first BL 1402 and the second BL 1452 can be operably coupled to a corresponding number of BEOL memory cells (e.g., Figure 2 memory cells 200) of

[0253] As shown in the figure, the first BL1402 includes a first end 1402A and a second end 1402B that are spaced apart from each other. The second BL1452 includes a first end 1452A, a second end 1452B, and a third portion 1452C that connects the first end 1452A and the second end 1452B. Each of the first ends 1402A and 1452A and the second ends 1402B and 1452B extends in the X direction, while the third portion 1452C extends in the Y direction. In addition, the projections of the first end 1402A and the second end 1402B (of the first BL1402) are spaced apart in the Y direction, and the projections of the first end 1452A and the second end 1452B (of the second BL1452) are spaced apart in the Y direction.

[0254] Regarding the first BL1402, even though the first end 1402A and the second portion 1402B are physically separated in the same metallization layer M6, they can be electrically coupled to each other through a plurality of wire structures disposed in one or more metallization layers. The first end 1402A is coupled to a wire structure 1412 (disposed between the metallization layers M5 and M6) through one of the via structures 1405, and the second end 1402B is coupled to another wire structure 1414 through another via structure 1405. In some embodiments, the wire structures 1412 and 1414 can be used as the source terminal and the drain terminal of a BEOL memory cell, respectively (e.g., Figure 2 the wire structures 216, 218). For reference, the BG1416 and WL1418 of the above-mentioned BEOL memory cell are also shown.

[0255] In this way, the power path 1420 can be formed at least by the first end 1402A in the metallization layer M6, the wire structure 1412 between the metallization layers M5 and M6, a conductive path formed operably in the channel layer of the corresponding BEOL memory cell coupled between the wire structures 1412 and 1414, the wire structure 1414 between the metallization layers M5 and M6, and the second end 1402B that is again in the metallization layer M6. In some embodiments, the power path 1420 can be operationally equivalent to the first BL1402. In other words, the first BL1402 operably includes the first end 1402A, the wire structures 1412 and 1414, the channel layer that couples the wire structure 1412 to the wire structure 1414, and the second end 1402B.

[0256] Regarding the second BL1452, the first end portion 1452A and the second end portion 1452B can be physically coupled to each other through the third portion 1452C even if they are physically separated in the same metallization layer M6. For example, the first end portion 1452A is connected to one end of the third portion 1452C, and the second end portion 1452B is connected to the other end of the third portion 1452C.

[0257] In this way, the power path 1460 can be formed at least by the first end portion 1452A, the third portion 1452C, and the second end portion 1452B in the metallization layer M6. In some embodiments, the power path 1460 can be operationally equivalent to the second BL1452. In other words, the second BL1452 operably includes the first end portion 1452A, the third portion 1452C, and the second portion 1452B.

[0258] In Figure 14 the embodiments, the wire structures formed in the metallization layer M6 (e.g., 1402A, 1402B, 1452A, 1452B, 1452C) can extend along the X direction or the Y direction, while the wire structures formed between the metallization layers M5 and M6 (e.g., 1412, 1414) can extend along the Y direction. When one or more "intermediate" portions are provided in the metallization layer and extend in a different direction from the end portions, different BLs, such as 1402 (or the equivalent path 1420) and 1452 (or the equivalent path 1460), can be twisted.

[0259] According to some embodiments, Figure 15 a schematic diagram showing BL1502, 1532, and 1562, where the noise source 1501 is located nearby, Figure 16 showing an exemplary layout 1600 corresponding to at least a part of the Figure 15 schematic diagram.

[0260] As shown in the figure, each of BL1502 to BL1562 includes two ends. For example, BL1502 includes ends 1502A and 1502B, BL1532 includes ends 1532A and 1532B, and BL1562 includes ends 1562A and 1562B. By placing the corresponding ends of each BL at different distances relative to the noise source 1501, the coupling of noise can be balanced, which can advantageously reduce the impact of noise on the BL. By configuring the ends of each BL in this way, each BL can have one or more intermediate portions that are twisted with at least another BL. For example, the ends 1502A and 1502B of BL1502 can be coupled to each other through an intermediate portion 1502C, the ends 1532A and 1532B of BL1532 can be coupled to each other through an intermediate portion 1532C, and the ends 1562A and 1562B of BL1562 can be coupled to each other through an intermediate portion 1562C. In Figure 15 the illustrated example, the intermediate portions 1502C, 1532C, and 1562C can be twisted or otherwise overlap each other.

[0261] Figure 16 The layout of Figure 15 is implemented as the illustrated example. As shown in the figure, the ends 1502A and 1502B (provided in the metallization layer M6) can be coupled to each other through a wire structure provided below the ends 1502A and 1502B, and the ends 1502A and 1502B are configured as source / drain terminals of a BEOL memory cell, as in the example layouts 700, 800, 900, 1000, and 1100 respectively shown in Figures 7 to 11 . Such a wire structure can be an implementation of the intermediate portion 1502C. The ends 1532A and 1532B (provided in the metallization layer M6) can be coupled to each other through a wire structure provided in the same metallization layer as the ends 1532A and 1532B. Such a wire structure can be an implementation of the intermediate portion 1532C. The ends 1562A and 1562B (provided in the metallization layer M6) can be coupled to each other through a wire structure (provided in the metallization layer M5), as in the example layouts 600 and 700 respectively shown in Figure 6 and Figure 7 . Such a wire structure can be an implementation of the intermediate portion 1562C.

[0262] According to some embodiments, Figure 17 shows a schematic diagram of BL1702, 1732, and 1762, where a noise source 1701 is located nearby, Figure 18 shows an example layout 1800 corresponding to at least a part of the schematic diagram of Figure 17 .

[0263] As shown in the figure, each of BL1702 to 1762 includes three ends. For example, BL1702 includes ends 1702A, 1702B, and 1702C, BL1732 includes ends 1732A, 1732B, and 1732C, and BL1762 includes ends 1762A, 1762B, and 1762C. By placing the corresponding ends of each BL at different distances relative to the noise source 1701, the coupling of the noise can be balanced, which can advantageously reduce the impact of the noise on the BL. By arranging the ends of each BL in this way, each BL can have one or more intermediate portions, where the intermediate portion is twisted with at least another BL. For example, ends 1702A and 1702B of BL1702 can be coupled to each other through intermediate portion 1702D, ends 1702B and 1702C of BL1702 can be coupled to each other through intermediate portion 1702E, ends 1732A and 1732B of BL1732 can be coupled to each other through intermediate portion 1732D, ends 1732B and 1732C of BL1732 can be coupled to each other through intermediate portion 1732E, ends 1762A and 1762B of BL1762 can be coupled to each other through intermediate portion 1762D, and ends 1762B and 1762C of BL1762 can be coupled to each other through intermediate portion 1762E. In Figure 17 the illustrated example, the intermediate portions 1702D, 1702E, 1732D, 1732E, 1762D, and 1762E can be twisted with each other or otherwise overlap each other.

[0264] Figure 18 The layout of Figure 17 is implemented as shown in the illustrated example. As shown in the figure, ends 1702A and 1702B (provided in the metallization layer M6) can be coupled to each other through a wire structure, as in the example layouts 600 and 700 shown respectively in Figure 6 and Figure 7 This wire structure can be an implementation of the intermediate portion 1702D. Ends 1732A and 1732B (provided in the metallization layer M6) can be coupled to each other through a wire structure provided in the same metallization layer as ends 1732A and 1732B. This wire structure can be an implementation of the intermediate portion 1732D. Ends 1762A and 1762B (provided in the metallization layer M6) can be coupled to each other through a wire structure provided in the same metallization layer as ends 1762A and 1762B. This wire structure can be an implementation of the intermediate portion 1762D.

[0265] According to some embodiments, Figure 19 shows a schematic diagram of BL1902, 1932, and 1962, where the noise source 1901 is located nearby, Figure 20 shows corresponding to Figure 19Exemplary layout 2000 of at least a portion of the schematic diagram. As shown, each of BL1902 to BL1992 includes two ends. For example, BL1902 includes ends 1902A and 1902B, BL1932 includes ends 1932A and 1932B, BL1962 includes ends 1962A and 1962B, and BL1992 includes ends 1992A and 1992B. By placing the corresponding ends of each BL at different distances relative to the noise source 1901, the coupling of noise can be balanced, which can advantageously mitigate the impact of noise on the BL. By arranging the ends of the BLs in this way, each BL can have one or more intermediate portions that are twisted with respect to at least another BL. For example, ends 1902A and 1902B of BL1902 can be coupled to each other through intermediate portion 1902C, ends 1932A and 1932B of BL1932 can be coupled to each other through intermediate portion 1932C, ends 1962A and 1962B of BL1962 can be coupled to each other through intermediate portion 1962C, and ends 1992A and 1992B of BL1992 can be coupled to each other through intermediate portion 1992C. In Figure 19 the exemplary embodiment shown, intermediate portions 1902C, 1932C, 1962C, and 1992C can be twisted or otherwise overlap each other.

[0266] Figure 20 The layout 2000 is Figure 19 the exemplary implementation shown. As shown, ends 1902A and 1902B (provided in metallization layer M6) can be coupled to each other through a wire structure (provided in metallization layer M5), as in the exemplary layouts 600 and 700 shown in Figure 6 and Figure 7 respectively. Such a wire structure can be an implementation of intermediate portion 1902C. Ends 1932A and 1932B (provided in metallization layer M6) can be coupled to each other through a wire structure provided in the same metallization layer as ends 1932A and 1932B. Such a wire structure can be an implementation of intermediate portion 1932C. Ends 1962A and 1962B (provided in metallization layer M6) can be coupled to each other through a wire structure (provided in metallization layer M5), as in the exemplary layouts 600 and 700 shown in Figure 6 and Figure 7 respectively. Such a wire structure can be an implementation of intermediate portion 1962C. Ends 1992A and 1992B (provided in metallization layer M6) can be coupled to each other through a wire structure provided below ends 1992A and 1992B, and ends 1992A and 1992B are configured as source / drain terminals of a BEOL memory cell, as in the exemplary embodiments shown in Figures 7 to 11The exemplary layouts 700, 800, 900, 1000, and 1100 shown. Such a wire structure can be an embodiment of the intermediate portion 1992C.

[0267] According to various aspects of the present disclosure, Figure 21 A flowchart of an exemplary method is shown for fabricating a corresponding memory device coupled to a twisted BL (as shown in the exemplary layouts 600 - 1400, respectively, such as Figures 6 to 14 ). For example, some operations of method 2100 can be used to fabricate a plurality of BLs, each BL being operably coupled to a corresponding number of BEOL memory cells and each BL having at least one intermediate portion overlapping an intermediate portion of another BL.

[0268] It should be noted that method 2100 is merely an example and is not intended to limit the present disclosure. Thus, it should be understood that additional operations can be provided before, during, and / or after method 2100, and some other operations may be described only briefly herein. The following discussion of method 2100 may refer to one or more elements discussed with respect to Figures 1 to 20 discussed.

[0269] According to some embodiments, method 2100 begins with operation 2102, where a transistor is formed over at least a first metallization layer among a plurality of metallization layers over a semiconductor substrate. The semiconductor substrate can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., where the semiconductor substrate can be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate can be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a semiconductor material layer formed over an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates can also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0270] Each metallization layer includes a plurality of wire structures embedded in the corresponding IMD / ILD. The wire structures may include a plurality of back-end-of-line (BEOL) wires or islands, such as wire structures 210, 216, 218, WL222, BL224, etc. Each wire structure may include one or more metal materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or a combination thereof. The IMD / ILD embedding the interconnect structure may include one or more low-k dielectric layers (i.e., dielectrics with a dielectric constant less than about 3.9), ultra-low-k dielectric layers, or oxides (e.g., silicon oxide).

[0271] Transistors formed within one of the metallization layers or between adjacent metallization layers are sometimes referred to as BEOL transistors. Such BEOL transistors can be implemented as two-dimensional back-gate transistors (e.g., 202), whose channels can be formed of one or more semiconductor surface oxide materials, such as IGZO, InZnO, InSnO, SnO2, MgAlZnO, etc., or one or more 2D materials, such as transition metal dichalcogenide (TMD) materials, graphene, etc. In the example discussed above, the BEOL transistors can be formed above metallization layers M0 to M4 and between metallization layers M5 and M6 ( Figure 5 ).

[0272] According to some embodiments, method 2100 proceeds to operation 2104, where a bit line is formed in the second metallization layer of the plurality of metallization layers.

[0273] The bit line is operatively coupled to the first source / drain terminal of the BEOL transistor formed in operation 2102. In various embodiments, the bit line may include at least a first wire structure and a second wire structure that are physically spaced apart from each other, but the first wire structure and the second wire structure are electrically coupled to each other through one or more wire structures disposed in respective metallization layers different from the second metallization layer.

[0274] As a non-limiting example, in Figure 6 , the bit line (e.g., 602) may include a first wire structure 602A and a second wire structure 602B disposed in metallization layer M6, where the first wire structure 602A and the second wire structure 602B are coupled to each other through wire structures 612, 614, and 616. These wire structures connecting the first wire structure 602A and the second wire structure 602B are disposed across metallization layers M4 to M5. Similarly, in Figure 6In [the figure], another bit line (e.g., 652) can be formed as a first wire structure 652A and a second wire structure 652B disposed in the metallization layer M6, wherein the first wire structure 652A and the second wire structure 652B are coupled to each other through wire structures 622, 624, and 626 formed across the metallization layers M4 to M5. As another non-limiting example, in Figure 7 In [the figure], a bit line (e.g., 752) can include a first wire structure 752A and a second wire structure 752B disposed in the metallization layer M6, wherein the first wire structure 752A and the second wire structure 752B are coupled to each other through a wire structure 722 (source / drain terminal of a BEOL memory cell) disposed between the metallization layers M5 and M6. As another non-limiting example, in Figure 9 In [the figure], a bit line (e.g., 902) can include a first wire structure 902A and a second wire structure 90B disposed in the metallization layer M6, wherein the first wire structure 902A and the second wire structure 902B are coupled to each other through a wire structure 912 (formed in an L-shaped profile) disposed in the metallization layer M5.

[0275] According to some embodiments, method 2100 proceeds to operation 2106, wherein a capacitor is formed within a plurality of metallization layers and above the bit line.

[0276] The capacitor is operatively coupled to the second source / drain terminal of the BEOL transistor formed in operation 2102. In various embodiments, the capacitor can be formed as a MIM or MOM structure (e.g., 204), which includes a bottom electrode and a top electrode sandwiching a capacitor dielectric layer. In the above example where the bit line is formed in the metallization layer M6, the capacitor can be formed between the metallization layers M6 and M7.

[0277] One aspect of the present disclosure discloses a memory device. The memory device includes a substrate, a plurality of metallization layers, a plurality of memory cells, and bit lines. The plurality of metallization layers are disposed above the substrate. Each memory cell includes a transistor and a capacitor. The bit lines are coupled to a corresponding set of the plurality of memory cells. The bit line includes at least a first wire structure and a second wire structure, the first wire structure and the second wire structure extending along a first lateral direction and disposed in a first metallization layer of the plurality of metallization layers. The first wire structure and the second wire structure are physically spaced apart from each other, but are electrically coupled to each other through one or more wire structures disposed in the plurality of metallization layers.

[0278] In some embodiments, the transistors and capacitors of each memory cell are formed across multiple metallization layers. In some embodiments, wherein along a second lateral direction perpendicular to the first lateral direction, the projection of the second wire structure and the first wire structure are physically spaced apart from each other. In some embodiments, wherein the wire structure includes a third wire structure disposed in a second metallization layer of the metallization layers and extending along the second lateral direction; a fourth wire structure disposed in a third metallization layer of the metallization layers and extending along the first lateral direction; and a fifth wire structure disposed in the second metallization layer and extending along the second lateral direction. In some embodiments, wherein the wire structure includes source / drain structures of a corresponding one of the groups of memory cells, and the source / drain structures extend along the second lateral direction. In some embodiments, wherein the wire structure includes an island structure disposed in a second metallization layer of the metallization layers. In some embodiments, wherein the wire structure includes a third wire structure, wherein the third wire structure is disposed in a second metallization layer of the metallization layers, and the third wire structure has a first portion extending along the first lateral direction and a second portion extending along the second lateral direction. In some embodiments, wherein the wire structure includes gate structures of a corresponding one or more groups of memory cells, and wherein the gate structures are formed as island structures. In some embodiments, wherein the wire structure includes gate structures of a corresponding one or more groups of memory cells, and wherein the gate structures are formed to have a first portion extending along the first lateral direction and a second portion extending along the second lateral direction. In some embodiments, wherein the wire device includes source / drain structures of a corresponding one or more groups of memory cells, and wherein the source / drain structures are formed as island structures. In some embodiments, wherein the wire structure includes source / drain structures of a corresponding one of the groups of memory cells, and wherein the source / drain structures are formed as H-shaped structures.

[0279] Another aspect of the present disclosure discloses a memory device. The memory device includes a plurality of memory cells and bit lines. The memory cells are disposed on one or more metallization layers formed above a substrate. The bit lines are operatively coupled to a corresponding one of the groups of the plurality of memory cells. The bit lines are at least composed of a first wire structure and a second wire structure disposed in a first metallization layer of the plurality of metallization layers. The first wire structure and the second wire structure are physically spaced apart from each other, but are electrically coupled to each other through one or more other wire structures.

[0280] In some embodiments, a first wire structure and a second wire structure both extend along a first lateral direction, and in a second lateral direction perpendicular to the first lateral direction, a projection of the second wire structure is physically spaced apart from the first wire structure. In some embodiments, the other wire structure or the plurality of other wire structures includes: a third wire structure disposed in a second metallization layer of a metallization layer and extending along the second lateral direction; a fourth wire structure disposed in a third metallization layer of the metallization layer and extending along the first lateral direction; and a fifth wire structure disposed in the second metallization layer and extending along the second lateral direction. In some embodiments, one or more of the other wire structures includes a source / drain structure of one of the memory cells. In some embodiments, one or more of the other wire structures includes an island structure disposed in the second metallization layer of the metallization layer. In some embodiments, one or more of the other wire structures includes a third wire structure, the third wire structure being disposed in the second metallization layer of the plurality of metallization layers, and the third wire structure having a first portion extending along the first lateral direction and a second portion extending along the second lateral direction. In some embodiments, one or more of the other wire structures includes a gate structure in one or more of the memory cells.

[0281] Another aspect of the present disclosure discloses a method of forming a memory device. The method includes forming a transistor at least over a first metallization layer among a plurality of metallization layers disposed over a substrate. The method includes forming a bit line over the transistor in a second metallization layer of the plurality of metallization layers, wherein the bit line is operatively coupled to a first source / drain terminal of the transistor. The method includes forming a capacitor over the bit line in the plurality of metallization layers, wherein the capacitor is operatively coupled to a second source / drain terminal of the transistor. The bit line includes at least a first wire structure and a second wire structure, and wherein the first wire structure and the second wire structure are physically spaced apart from each other, but are electrically coupled to each other through one or more wire structures disposed in other metallization layers different from the second metallization layer.

[0282] In some embodiments, a first wire structure and a second wire structure both extend along a first lateral direction, and in a second lateral direction perpendicular to the first lateral direction, a projection of the second wire structure is physically spaced apart from the first wire structure.

[0283] Another aspect of the present disclosure discloses a memory device. The memory device includes a substrate, a plurality of metallization layers, transistors, bit lines, and capacitors. The plurality of metallization layers are located above the substrate. The transistors are disposed above a first metallization layer of the metallization layers. The bit lines are disposed in a second metallization layer of the metallization layers, wherein the bit lines are operatively coupled to a first source / drain terminal of the transistors. The transistors are disposed above the bit lines, wherein the capacitors are operatively coupled to a second source / drain terminal of the transistors. Wherein the bit lines include at least a first wire structure and a second wire structure, and wherein the first wire structure and the second wire structure are physically spaced apart from each other, but are electrically coupled to each other through one or more other wire structures.

[0284] As used herein, the term “about / approximately” generally indicates a given amount of value that can vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term “about” can represent a given amount of value, for example, varying within a range of 10 - 30% of this value (e.g., ±10%, ±20%, or ±30% of the value).

[0285] The features of several embodiments are outlined above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as those described in the embodiments herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made by those skilled in the art within the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that, Comprising: A substrate; A plurality of metallization layers disposed above the substrate; A plurality of memory cells, each memory cell comprising a transistor and a capacitor; And A bit line coupled to a corresponding set of the plurality of memory cells; Wherein the bit line comprises at least a first wire structure and a second wire structure, the first wire structure and the second wire structure extending along a first lateral direction and disposed in a first metallization layer of the plurality of metallization layers; Wherein the first wire structure and the second wire structure are physically spaced apart from each other, but are electrically coupled to each other through a plurality of wire structures disposed in the metallization layer or the plurality of metallization layers.

2. The memory device according to claim 1, wherein Wherein the transistor and the capacitor of each memory cell are formed across a plurality of the plurality of metallization layers.

3. The memory device according to claim 1, wherein Wherein along a second lateral direction perpendicular to the first lateral direction, a projection of the second wire structure is physically spaced apart from the first wire structure.

4. The memory device according to claim 3, wherein, Wherein the plurality of wire structures comprise: A third wire structure disposed in a second metallization layer of the plurality of metallization layers and extending along the second lateral direction; A fourth wire structure disposed in a third metallization layer of the plurality of metallization layers and extending along the first lateral direction; and A fifth wire structure disposed in the second metallization layer and extending along the second lateral direction.

5. A memory device, characterized in that, Comprising: A plurality of memory cells disposed in one or more layers of a plurality of metallization layers above a substrate; And A bit line operably coupled to a corresponding set of the plurality of memory cells; Wherein the bit line is at least composed of a first wire structure and a second wire structure disposed in a first metallization layer of the plurality of metallization layers; Wherein the first wire structure and the second wire structure are physically spaced apart from each other, but are electrically coupled to each other through one or more other wire structures.

6. The memory device according to claim 5, wherein, Wherein both the first wire structure and the second wire structure extend along a first lateral direction, and wherein along a second lateral direction perpendicular to the first lateral direction, a projection of the second wire structure is physically spaced apart from the first wire structure.

7. The memory device according to claim 6, wherein, Wherein the other wire structure or the plurality of other wire structures comprise: A third wire structure disposed in a second metallization layer of the plurality of metallization layers and extending along the second lateral direction; A fourth wire structure disposed in a third metallization layer of the plurality of metallization layers and extending along the first lateral direction; and A fifth wire structure disposed in the second metallization layer and extending along the second lateral direction.

8. The memory device according to claim 6, wherein, Wherein the other wire structure or the plurality of other wire structures comprise a source / drain structure of one of the plurality of memory cells.

9. The memory device according to claim 6, characterized in that, Wherein the other wire structure or the plurality of other wire structures comprise an island structure disposed in a second metallization layer of the plurality of metallization layers.

10. A memory device, characterized in that, Comprising: A substrate; A plurality of metallization layers located above the substrate; A transistor disposed above a first metallization layer of the plurality of metallization layers; A bit line disposed in a second metallization layer of the plurality of metallization layers, wherein the bit line is operably coupled to a first source / drain terminal of the transistor; And A capacitor is disposed above the bit line, wherein the capacitor is operatively coupled to a second source / drain terminal of the transistor; wherein the bit line includes at least a first wire structure and a second wire structure, and wherein the first wire structure and the second wire structure are physically spaced apart from each other, but are electrically coupled to each other through one or more other wire structures.

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