BMS reset circuit, device and system

Abstract

The utility model relates to a reset circuit, device and system of a BMS, the reset circuit of the BMS comprises a switch, a capacitive reactance circuit, an impedance circuit, a triode and a first resistor, one end of the first resistor is connected with a main control chip, the other end of the first resistor is connected with a collector electrode of the triode, one end of the switch is powered on, and the other end of the switch is powered off. The other end of the switch, the capacitive reactance circuit, the impedance circuit and the base electrode of the triode are sequentially connected, the emitter electrode of the triode is grounded, and one end of the capacitive reactance circuit and one end of the impedance circuit are both grounded. When the communication pin is pulled down due to interference, resetting of the BMS is realized through combination of the triode and the first resistor; meanwhile, interference is effectively filtered out by introducing the capacitive reactance circuit and the impedance circuit.

Description

Technical Field

[0001] This application relates to the technical field of automatic reset circuits, and specifically, to a reset circuit, device, and system for a BMS. Background Art

[0002] With the continuous maturity of the technology of lithium-ion power batteries, lithium batteries are combined in series and parallel to form battery packs with different voltages and capacities, and are applied to products such as electric bicycles and electric motorcycles. Some of them require functions such as high-precision power measurement and driving range display, and thus there is a need for a high-end BMS with a communication port. SMBUS communication is a short-distance communication, generally applied to laptops. SMBUS communication has low cost and simple design. However, when directly using an SMBUS communication circuit on an electric bicycle, under strong electromagnetic interference conditions, the communication pin of the main control chip of the BMS will be continuously pulled low and cannot be automatically restored, thus affecting the normal communication function of the SMBUS communication signal. Summary of the Utility Model

[0003] The purpose of this application is to provide a reset circuit, device, and system for a BMS to solve the problem that the communication pin of the main control chip of the BMS is continuously pulled low, and to reset the main control chip to restore normal communication.

[0004] To solve the above problems, this application adopts the following technical solutions to achieve:

[0005] The first aspect of this application provides a reset circuit for a BMS, including: a switch, a capacitive reactance circuit, an impedance circuit, a triode, and a first resistor. One end of the first resistor is connected to the main control chip, and the other end of the first resistor is connected to the collector of the triode. One end of the switch is powered, and the other end of the switch, the capacitive reactance circuit, the impedance circuit, and the base of the triode are connected in sequence. The emitter of the triode is grounded, and one end of the capacitive reactance circuit and one end of the impedance circuit are both grounded.

[0006] Further, the reset circuit for the BMS includes a second resistor, and both ends of the second resistor are respectively connected to the switch and the capacitive reactance circuit.

[0007] Further, the capacitive reactance circuit includes a first capacitor and a second capacitor. One end of the first capacitor and one end of the second capacitor are both connected to the second resistor, and the other end of the first capacitor and the other end of the second capacitor are both grounded.

[0008] Further, the capacitance values of the first capacitor and the second capacitor are the same.

[0009] Further, the impedance circuit includes a third resistor and a fourth resistor. The third resistor is respectively connected to the capacitive reactance circuit and the base of the triode. One end of the fourth resistor is connected to the third resistor, and the other end of the fourth resistor is grounded.

[0010] Further, the triode is an NPN type.

[0011] Further, the switch is a surface mount plastic encapsulated reed switch.

[0012] A second aspect of the present application provides a reset device for a BMS, including a housing with a receiving cavity formed therein, and the reset circuit of the BMS as described in any one of the above, which is disposed inside the housing.

[0013] A third aspect of the present application provides a reset system for a BMS, and the reset system for the BMS includes the above-mentioned reset device for the BMS.

[0014] Compared with the prior art, the beneficial effects of the present application are as follows: when pulled down due to interference, the reset of the BMS is achieved through the combination of the triode and the first resistor; at the same time, by introducing the capacitive reactance circuit and the impedance circuit, interference is effectively filtered out. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of a reset circuit for a BMS provided by an embodiment of the present application;

[0016] Figure 2 is a system block diagram of a reset circuit for a BMS provided by an embodiment of the present application; and

[0017] Figure 3 is a schematic diagram of a main control chip provided by an embodiment of the present application.

[0018] DESCRIPTION OF THE REFERENCE NUMERALS:

[0019] 10. Switch; 20. First resistor; 30. Capacitive reactance circuit; 31. First capacitor; 32. Second capacitor; 40. Impedance circuit; 41. Third resistor; 42. Fourth resistor; 50. Triode; 60. Second resistor; 200. Main control chip. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The following describes in detail the specific embodiments of the present application with reference to the drawings.

[0021] It should be noted that, without conflict, the embodiments in the present application and the technical features in the embodiments can be combined with each other. The detailed description in the specific embodiments should be understood as an explanatory description of the purpose of the present application and should not be regarded as an improper limitation of the present application.

[0022] It should be understood that the orientation or positional relationship is based on the orientation or positional relationship shown in the drawings. These orientation terms are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0023] Figure 1 The figure is a schematic diagram of a reset circuit of a BMS provided by an embodiment of the present application. Figure 2 The figure is a system block diagram of a reset circuit of a BMS provided by an embodiment of the present application. Figure 3 The figure is a schematic diagram of a main control chip provided by an embodiment of the present application.

[0024] As Figures 1 to 3 As shown, an embodiment of the present application provides a reset circuit of a BMS, including: a switch 10, a capacitive reactance circuit 30, an impedance circuit 40, a triode 50, and a first resistor 20. One end of the first resistor 20 is connected to the main control chip 200, and the other end of the first resistor 20 is connected to the collector of the triode 50. One end of the switch 10 is powered, and one end of the switch 10, the capacitive reactance circuit 30, the impedance circuit 40, and the base of the triode 50 are connected in sequence. The emitter of the triode 50 is grounded, and one end of the capacitive reactance circuit 30 and one end of the impedance circuit 40 are both grounded.

[0025] Specifically, one end of the switch 10 is connected to a power supply. For example, one end of the switch 10 is connected to VCC_5V, and the other end of the switch 10 is connected to the base of the triode 50 through a capacitive reactance circuit 30 and an impedance circuit 40. One end of the first resistor 20 is connected to the main control chip 200 of the BMS, and the other end of the first resistor 20 is connected to the collector of the triode 50. The emitter of the triode 50 is grounded. One end of the capacitive reactance circuit 30 and one end of the impedance circuit 40 are grounded. When it is detected that electromagnetic interference causes the corresponding pin of the BMS main control chip to be pulled low, the switch 10 closes, and a trigger signal is provided to the triode 50 through the capacitive reactance circuit 30 and the impedance circuit 40. Under the action of the trigger signal, the triode 50 guides the current to the first resistor 20, thereby resetting the main control chip 200 and restoring its corresponding pin to the normal state. After the reset is completed, the switch 10 disconnects and returns to the normal working state, and the BMS main control chip 200 starts working again. In particular, the triode 50 is an NPN type. The switch 10 is a surface mount plastic encapsulated reed switch.

[0026] When it is pulled low due to interference, the reset of the BMS is achieved through the combination of the triode 50 and the first resistor 20; at the same time, by introducing the capacitive reactance circuit 30 and the impedance circuit 40, the interference is effectively filtered out.

[0027] In some embodiments, the reset circuit of the BMS includes a second resistor 60, and both ends of the second resistor 60 are respectively connected to the switch 10 and the capacitive reactance circuit 30.

[0028] Specifically, the capacitive reactance circuit 30 is connected to the second resistor 60, and the other end of the second resistor 60 is connected to the main control chip 200 of the BMS through the capacitive reactance circuit 30, the impedance circuit 40, and the transistor 50. Through the cooperation of the capacitive reactance circuit 30 and the second resistor 60, electromagnetic interference is effectively filtered out.

[0029] In some embodiments, the capacitive reactance circuit 30 includes a first capacitor 31 and a second capacitor 32 , one end of the first capacitor 31 and one end of the second capacitor 32 are both connected to the second resistor 60 , and the other end of the first capacitor 31 and the other end of the second capacitor 32 are both grounded.

[0030] Specifically, one end of the first capacitor 31 and one end of the second capacitor 32 are both connected to one end of the second resistor 60, forming a parallel network of capacitance and resistance, and the other end of the first capacitor 31 and the other end of the second capacitor 32 are both grounded, which can effectively protect and filter. It should be noted that in the capacitive reactance circuit 30, the capacitance of the first capacitor 31 and the second capacitor 32 can be selected according to actual needs to achieve the best effect, and the resistance of the second resistor 60 can also be selected according to actual needs to adapt to different circuit environments and current regulation requirements. In particular, the capacitance values of the first capacitor 31 and the second capacitor 32 are consistent. By introducing the first capacitor 31 and the second capacitor 32, the impedance and capacitive reactance characteristics of the circuit can be effectively adjusted, thereby improving the adaptability of the circuit to frequency changes and enhancing the stability of the circuit.

[0031] In some embodiments, the impedance circuit 40 includes a third resistor 41 and a fourth resistor 42. The third resistor 41 is connected to the capacitive reactance circuit 30 and the base of the transistor 50 respectively. One end of the fourth resistor 42 is connected to the third resistor 41, and the other end of the fourth resistor 42 is grounded.

[0032] Specifically, the third resistor 41 and the fourth resistor 42 are connected between the capacitive reactance circuit 30 and the base of the transistor 50. One end of the fourth resistor 42 is connected to the third resistor 41, and the other end of the fourth resistor 42 is grounded, providing a stable reference potential. The third resistor 41 and the fourth resistor 42 can be connected by welding, plugging, or other reliable connection methods to ensure the stability and reliability of the circuit. By introducing the third resistor 41 and the fourth resistor 42, a stable current path can be provided, reducing noise and interference in the circuit.

[0033] A second aspect of the present application provides a reset device for a BMS, comprising a housing having a receiving cavity formed therein, and any one of the above-mentioned reset circuits for the BMS, which are disposed within the housing.

[0034] A third aspect of the present application provides a BMS reset system, which includes the above-mentioned BMS reset device.

[0035] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions required to be protected by the present application.

Claims

1. A reset circuit of a BMS, characterized in that, Comprising: A switch, a capacitive reactance circuit, an impedance circuit, a triode, and a first resistor. One end of the first resistor is connected to the main control chip, and the other end of the first resistor is connected to the collector of the triode. One end of the switch is powered, and the other end of the switch, the capacitive reactance circuit, the impedance circuit, and the base of the triode are connected in sequence. The emitter of the triode is grounded, and one end of the capacitive reactance circuit and one end of the impedance circuit are both grounded.

2. The reset circuit of a BMS according to claim 1, characterized in that, The reset circuit of the BMS includes a second resistor, and both ends of the second resistor are respectively connected to the switch and the capacitive reactance circuit.

3. The reset circuit of a BMS according to claim 2, characterized in that The capacitive reactance circuit includes a first capacitor and a second capacitor. One end of the first capacitor and one end of the second capacitor are both connected to the second resistor, and the other end of the first capacitor and the other end of the second capacitor are both grounded.

4. The reset circuit of a BMS according to claim 3, characterized in that, The capacitance values of the first capacitor and the second capacitor are the same.

5. The reset circuit of a BMS according to claim 1, characterized in that, The impedance circuit includes a third resistor and a fourth resistor. The third resistor is respectively connected to the capacitive reactance circuit and the base of the triode. One end of the fourth resistor is connected to the third resistor, and the other end of the fourth resistor is grounded.

6. The reset circuit of a BMS according to claim 1, wherein The triode is of NPN type.

7. The reset circuit of a BMS according to claim 1, characterized in that The switch is a surface mount hermetically sealed reed switch.

8. A reset device for a BMS, characterized in that, A housing with a receiving cavity formed therein, and the reset circuit of the BMS according to any one of claims 1-7 is disposed in the housing.

9. A reset system for a BMS, characterized in that, The reset system of the BMS includes the reset device of the BMS according to claim 8.

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