Storage control system and electronic equipment

Abstract

The utility model provides a memory control system and electronic equipment. The memory control system comprises a memory, a first control module, a first register and a second register, the first control module is respectively connected with the memory, the first register and the second register; wherein the data stored in the memory comprises first data and a plurality of second data, and the first control module is configured to read the first data, store the first data to the first register, read the second data in different time periods, and store the second data to the second register in different time periods. The first data is firstly read and stored in the first register, and then different second data can be read and stored in the second register in a time-sharing manner according to requirements, so that the storage space of the registers can be saved.

Description

Technical Field

[0001] Embodiments of the present utility model relate to the technical field of electronic circuits, and particularly to a control system for a memory and an electronic device. Background Art

[0002] With the development of the information age, many algorithm circuits need to introduce a large number of parameters during calculation. For a system including a one-time programmable memory for storing algorithm parameters, however, the one-time programmable memory can only read one data at a time. If multiple parameters of the one-time programmable memory need to be read during calculation, it will lead to slow calculation speed. Currently, referring to Figure 1 , usually all the used parameters in the one-time programmable memory 1 are loaded into the same register 2 at one time for the subsequent calculation circuit 3 to read data from the register 2 at any time. But in this way, some parameters are only used once but will permanently occupy the register 2, resulting in the storage space of the register 2 being occupied for a long time and wasting the storage space on the register 2. Summary of the Utility Model

[0003] Embodiments of the present utility model provide a control system for a memory and an electronic device, which can save the storage space of the register and reduce power consumption.

[0004] In a first aspect, embodiments of the present utility model provide a control system for a memory, including: a memory, a first control module, a first register, and a second register; the first control module is respectively connected to the memory, the first register, and the second register; wherein, the data stored in the memory includes first data and a plurality of second data, and the first control module is configured to read the first data and store the first data in the first register, and respectively read each of the second data in different time periods and store each of the second data in the second register in different time periods.

[0005] In some embodiments, the control system further includes a calculation module; the calculation module is respectively connected to the first register and the second register; the calculation module is configured to read the first data in the first register and the second data in the second register, and calculate the first data and the second data.

[0006] In some embodiments, the control system further includes a second control module; the second control module is connected to the calculation module; the second control module is configured to control the operation of the calculation module.

[0007] In some embodiments, the second control module is further connected to the first control module; the second control module is further configured to control the operation of the first control module.

[0008] In some embodiments, the first data is commonly used data.

[0009] In some embodiments, the first control module is further configured to write the first data and each second data into the memory.

[0010] In some embodiments, the memory is one of a one-time programmable memory, a multi-time programmable memory, and a flash memory.

[0011] In some embodiments, the first register includes at least one circuit structure of a trigger circuit and a latch circuit.

[0012] In some embodiments, the second register includes at least one circuit structure of a trigger circuit and a latch circuit.

[0013] In a second aspect, an embodiment of the present invention provides an electronic device, which includes a control system as described in any one of the first aspects.

[0014] Compared with the prior art, the present invention has the following beneficial effects: Different from the prior art, the present invention provides a memory control system and electronic device, comprising: a memory, a first control module, a first register, and a second register; the first control module is connected to the memory, the first register, and the second register respectively; wherein the data stored in the memory includes first data and multiple second data, and the first control module is configured to read the first data and store the first data in the first register, and read each second data in different time periods and store each second data in the second register in different time periods. By first reading and storing the first data in the first register, different second data can be read and stored in the second register in a time-sharing manner according to demand, thereby saving register storage space. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] One or more embodiments are exemplarily described by pictures in the corresponding drawings. These exemplified descriptions do not constitute limitations on the embodiments. Elements / modules and steps with the same reference numerals in the drawings are represented as similar elements / modules and steps. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0016] Figure 1 It is a structural block diagram of a system provided in the prior art;

[0017] Figure 2 This is a structural block diagram of a control system provided by an embodiment of the present utility model;

[0018] Figure 3It is a block diagram of another control system provided by an embodiment of the present utility model. Detailed implementation manners

[0019] The present utility model will be described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present utility model, but do not limit the present utility model in any form. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present utility model, several modifications and improvements can still be made. These all belong to the protection scope of the present utility model.

[0020] To facilitate the understanding of the present utility model, the present utility model will be described in more detail below in conjunction with the accompanying drawings and specific embodiments. Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by those skilled in the technical field to which the present utility model belongs. The terms used in the specification of the present utility model are only for the purpose of describing specific embodiments and are not used to limit the present utility model. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0021] It should be noted that if there is no conflict, the various features in the embodiments of the present utility model can be combined with each other, and all are within the protection scope of the present utility model. In addition, although the functional modules are divided in the device schematic diagram, in some cases, it can be different from the module division in the device. In addition, the terms "first", "second", etc. used herein do not limit the data and the execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0022] In a first aspect, the present utility model provides a control system for a memory 10. Please refer to Figure 2 , the control system includes: a memory 10, a first control module 20, a first register 30, and a second register 40. The first control module 20 is respectively connected to the memory 10, the first register 30, and the second register 40. Among them, the data stored in the memory 10 includes first data and a plurality of second data. The first control module 20 is configured to read the first data, store the first data in the first register 30, and respectively read each second data in different time periods and store each second data in the second register 40 in different time periods.

[0023] The memory 10 refers to a memory device that stores all or part of the parameters required for system computing. The first data and the second data refer to the parameters stored in the memory 10, and the first data and each second data are neither the same nor overlapping. The memory 10 can be one of a one-time programmable memory, a multi-time programmable memory, and a flash memory. The one-time programmable memory refers to a memory device that allows users to program by themselves to store data or instructions, but can only be programmed once and the data cannot be changed afterwards. It is suitable for storing some fixed data or programs that do not need to be modified, such as the firmware program in an embedded system. The multi-time programmable memory is a memory that allows users to erase and reprogram multiple times. This memory can cope with rapidly changing technologies and market demands and has the ability to update stored data without replacing hardware. The flash memory is an electronic erasable programmable read-only memory that allows multiple erasures or writes during operation and is a non-volatile memory, that is, the data will not be lost after power-off.

[0024] The first register 30 and the second register 40 refer to storage units with limited capacity but extremely fast speed, which can be used to temporarily store information such as data, instruction addresses, and intermediate results required during system operation and control. The first register 30 and the second register 40 are a type of volatile memory, that is, the data stored in them will disappear after power-off.

[0025] The first control module 20 may include suitable control devices such as a microcontroller processor, and its specific model can be set according to actual needs and will not be limited here.

[0026] For complex tasks, the system usually decomposes them into multiple subtasks or stages for processing. For example, during a calculation, the system usually performs calculations in stages, and different data in the memory 10 are required in different calculation stages. For example, in the process of executing an operation, two operation stages need to be executed. The first operation stage requires the use of the first data and the second data A, and the second operation stage requires the use of the first data and the second data B. Then, the first control module 20 can first read the first data in the memory 10 and store the first data in the first register 30. Then, the first control module 20 reads the second data A in the memory 10 and stores the second data A in the second register 40. In this way, the system can use the first data and the second data A in the first register 30 to perform the operation in the first operation stage. After completion, the first control module 20 will read the second data B in the memory 10 and store the second data B in the second register 40. It should be noted that at this time, the second data A in the second register 40 will be overwritten by the second data B, that is, the second data A will not be able to be obtained from the second register 40. In this way, the system can use the first data and the second data B in the first register 30 to perform the operation in the second operation stage, thereby completing the operation.

[0027] It can be seen that compared with the method of reading and storing all data into the same register, which results in a larger register area and power consumption, in this embodiment, by first reading and storing the first data into the first register 30, different second data can be read and stored into the second register 40 in a time-sharing manner according to the calculation requirements in the subsequent calculation stage, which can save the storage space of the register and effectively reduce the area and power consumption.

[0028] In some embodiments, the first data is commonly used data.

[0029] Commonly used data may be parameter data that is read more than or equal to once during the operation process. It may be possible to pre-set which data in the memory 10 are commonly used data, or determine which data are commonly used data according to the number of times they are read during the operation process.

[0030] In this embodiment, by making the first data the commonly used data, that is, the commonly used data first stored in the first register 30, when the commonly used data in the memory 10 is subsequently called, the data in the first register 30 can be directly read to obtain it, and the data can be read in one cycle, which can effectively reduce the operating time of the system.

[0031] In some of these embodiments, see Figure 3, the control system further includes a calculation module 50. The calculation module 50 is respectively connected to the first register 30 and the second register 40. The calculation module 50 is configured to read the first data in the first register 30 and the second data in the second register 40, and calculate the first data and the second data.

[0032] The calculation module 50 refers to a module in the system responsible for data processing and calculation tasks. It may include a processing unit for data processing (such as a microprocessor or an application-specific integrated circuit), a memory for temporarily storing data, a data bus for data transmission, and necessary interface circuits to communicate with the first register 30 and the second register 40. Its specific structure can refer to the prior art and is not limited herein.

[0033] Specifically, during the execution of an operation process, two operation stages need to be executed. The first operation stage requires the first data and the second data A, and the second operation stage requires the first data and the second data B. Then, the first control module 20 can first read the first data in the memory 10 and store the first data in the first register 30. Then, the first control module 20 reads the second data A in the memory 10 and stores the second data A in the second register 40. In this way, the calculation module 50 can read the first data in the first register 30 and the second data A in the second register 40 to perform the operation in the first operation stage. After completion, the first control module 20 will read the second data B in the memory 10 and store the second data B in the second register 40. It should be noted that at this time, the second data A in the second register 40 will be overwritten by the second data B, that is, the second data A will not be able to be obtained from the second register 40. In this way, the calculation module 50 can read the first data in the first register 30 and the second data B in the second register 40 to perform the operation in the second operation stage, thus completing the operation.

[0034] In this embodiment, by setting up a dedicated calculation module 50 to complete the calculation task, the accuracy of data processing is ensured, which helps to optimize the system performance, improve the overall operation efficiency, and in practical applications, the calculation module 50 can be selected or replaced according to different application scenarios to adapt to different data processing requirements, improve the flexibility of system design, and make the system more general.

[0035] In some of these embodiments, refer to Figure 3 , the control system further includes a second control module 60. The second control module 60 is connected to the calculation module 50. The second control module 60 is configured to control the operation of the calculation module 50.

[0036] The second control module 60 may include a suitable controller such as a microcontroller. Its specific model can be set according to actual needs and is not limited herein.

[0037] In this embodiment, the second control module 60 controls the computing module 50, which can more effectively manage and schedule computing resources. For example, the second control module 60 can allocate computing tasks according to the priorities of computing tasks and the availability of computing resources, thereby optimizing the utilization rate of the computing module 50 and improving computing efficiency. In addition, subsequently, the second control module 60 can also be used as a bridge between the computing module 50 and other parts of the system, enabling real-time monitoring of the working state of the computing module 50 and fault detection. For example, once an abnormality or fault is detected in the computing module 50, the second control module 60 can quickly take corresponding measures for protection and recovery, thereby avoiding risks such as system crashes and data loss.

[0038] In some of these embodiments, referring to Figure 3 , the second control module 60 is also connected to the first control module 20. The second control module 60 is further configured to control the operation of the first control module 20.

[0039] In this control system, the second control module 60 is not only connected to the computing module 50 but also to the first control module 20. First, after determining a computing task, the second control module 60 can send it to both the computing module 50 and the first control module 20 simultaneously. The first control module 20 can determine which are the first data and the second data based on the computing tasks sent by the second control module 60, or determine the second data required for each computing stage. In this way, the first control module 20 can cooperate with the computing module 50 to ensure that each module works together according to the predetermined logic and timing, thereby improving the overall performance and stability of the system. In addition, the second control module 60 can also perform real-time monitoring and fault detection on the working state of the first control module 20. Once a fault or abnormality is detected in the first control module 20, the second control module 60 can quickly take measures for isolation and recovery, thereby preventing the spread of faults and reducing the risk of system crashes, and improving the reliability of system operation.

[0040] In some of these embodiments, the first control module 20 is further configured to write the first data and each second data into the memory 10.

[0041] When the memory 10 is used for the first time, the first control module 20 can write the first data and each second data into the memory 10 to achieve data writing into the memory 10. In addition, for a memory 10 that can be erased and rewritten multiple times, the content stored in the memory 10 can be rewritten through the first control module 20. For example, data that is no longer needed can be deleted and new data can be written to optimize storage resources and improve the utilization rate of storage space.

[0042] In some of these embodiments, the first register 30 includes at least one circuit structure of a flip-flop circuit and a latch circuit.

[0043] A trigger circuit refers to a circuit structure including a trigger, which may be a D trigger or other types of triggers. A latch circuit refers to a circuit structure including a latch. The specific circuit structures of the trigger circuit and the latch circuit may refer to the prior art and are not limited here.

[0044] In this embodiment, the user can flexibly select a trigger circuit, a latch circuit, etc. as the first register 30 according to actual application scenarios and requirements, thereby improving design flexibility.

[0045] In some embodiments, the second register 40 includes at least one circuit structure of a flip-flop circuit and a latch circuit.

[0046] Similarly, in this embodiment, the user can flexibly select a trigger circuit, a latch circuit, etc. as the second register 40 according to actual application scenarios and requirements, thereby improving design flexibility.

[0047] In a second aspect, an embodiment of the present application provides an electronic device, which includes a control system as described in any one of the first aspects.

[0048] In this embodiment, the control system has the same structure and function as the control system described in any one of the first aspects, which will not be described in detail here. The electronic device may refer to a computer, a server, or other device.

[0049] In the electronic device, the first data is first read and stored in the first register, and then different second data can be read and stored in the second register in a time-sharing manner according to needs, thereby saving storage space of the register.

[0050] It should be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; under the idea of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other variations in different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A control system for a memory, characterized in that, Comprising: A memory, a first control module, a first register, and a second register; The first control module is respectively connected to the memory, the first register, and the second register; Wherein, the data stored in the memory includes first data and a plurality of second data, and the first control module is configured to read the first data, store the first data into the first register, and respectively read each of the second data in different time periods and store each of the second data into the second register in different time periods.

2. The control system according to claim 1, characterized in that The control system further includes a calculation module; The calculation module is respectively connected to the first register and the second register; The calculation module is configured to read the first data in the first register and the second data in the second register, and calculate the first data and the second data.

3. The control system according to claim 2, wherein The control system further includes a second control module; The second control module is connected to the calculation module; The second control module is configured to control the operation of the calculation module.

4. The control system according to claim 3, characterized in that The second control module is further connected to the first control module; The second control module is further configured to control the operation of the first control module.

5. The control system according to any one of claims 1-4, characterized in that, The first data is common data.

6. The control system according to any one of claims 1-4, wherein The first control module is further configured to write the first data and each of the second data into the memory.

7. The control system according to any one of claims 1-4, characterized in that, The memory is one of a one-time programmable memory, a multi-time programmable memory, and a flash memory.

8. The control system according to any one of claims 1-4, characterized in that, The first register includes at least one circuit structure of a flip-flop circuit and a latch circuit.

9. The control system according to claim 8, wherein The second register includes at least one circuit structure of a flip-flop circuit and a latch circuit.

10. An electronic device, characterized in that, Comprising the control system according to any one of claims 1-9.

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