Semiconductor assembly and electronic device

Abstract

The utility model provides a semiconductor assembly and electronic equipment, and relates to the technical field of integrated circuits. The semiconductor component comprises a control chip, the control chip comprises 2n channels, and n is an integer greater than or equal to zero; and at least one LPDDR chip, the LPDDR chip comprises at least one first area, and an LPDDR wafer is arranged in the LPDDR chip corresponding to the first area. Each channel of the control chip is correspondingly connected with one LPDDR wafer, and when n is a positive integer, the LPDDR wafers corresponding to at least a part of channels of the control chip are located at different LPDDR chips. The LPDDR chip in the application is small in packaging area, flexible in signal point location arrangement, flexible in adaptation of the LPDDR chip and the control chip, and capable of supporting various forms of control chips and improving the overall bandwidth performance.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly relates to a semiconductor component and an electronic device. Background Art

[0002] The LPDDR (Low Power Double Data Rate SDRAM) chip is a communication standard formulated by the JEDEC (Joint Electron Device Engineering Council) Association in the United States for low-power memory. It is known for its low power consumption and small size and is specifically used for mobile electronic devices.

[0003] In the process of conceiving and implementing the present application, the inventor found that there are at least the following problems: In some solutions, generally 315 balls are used to separately package the LPDDR chip. The package size of this packaging method is 15 mm × 12.4 mm, which occupies a relatively large area, and it is usually dual-channel, making it difficult to adapt to various forms of control chips, and the overall bandwidth performance is poor.

[0004] The foregoing description is provided to give general background information and does not necessarily constitute prior art. Summary of the Utility Model

[0005] In view of the above technical problems, the present application provides a semiconductor component and an electronic device, which can reduce the packaging area of the LPDDR chip and improve the flexibility of matching between the LPDDR chip and the control chip.

[0006] On the one hand, the present application provides a semiconductor component, which includes:

[0007] A control chip, the control chip includes 2 n channels, where n is an integer greater than or equal to zero;

[0008] At least one LPDDR chip, the LPDDR chip includes at least one first region, and a LPDDR wafer is disposed in the LPDDR chip corresponding to the first region;

[0009] Each of the channels of the control chip is correspondingly connected to a LPDDR wafer, and when n is a positive integer, the LPDDR wafers corresponding to at least a part of the channels of the control chip are located in different LPDDR chips.

[0010] In a possible implementation manner, the LPDDR chip includes one first region, and each of the channels of the control chip is electrically connected to the LPDDR wafer of one LPDDR chip.

[0011] In a possible implementation, the LPDDR chip includes two of the first regions, and the two first regions are symmetrically arranged.

[0012] In a possible implementation, one of the two LPDDR wafers of at least part of the LPDDR chip is electrically connected to the control chip correspondingly, and the other LPDDR wafer is not connected.

[0013] In a possible implementation, each channel of the control chip is electrically connected to one of the two LPDDR wafers of an LPDDR chip correspondingly, and the other LPDDR wafer is not connected;

[0014] Alternatively, the control chip includes at least four channels, the at least four channels are divided into multiple channel groups, each channel group includes two channels, and the two channels in each channel group are respectively electrically connected to the two LPDDR wafers of an LPDDR chip correspondingly.

[0015] In a possible implementation, the control chip includes an SOC chip.

[0016] In a possible implementation, the LPDDR chip further includes a circuit board, the circuit board includes at least one packaging area, the packaging area corresponds to the first region, and a plurality of signal points are arranged in the packaging area;

[0017] The packaging area includes a first functional area, a second functional area and a control area. The first functional area and the second functional area are arranged in sequence along a first direction, and the control area is adjacently arranged on the same side of the first functional area and the second functional area along a second direction, and the second direction is perpendicular to the first direction;

[0018] At least two data input / output points, at least two power input / output points are arranged in both the first functional area and the second functional area. At least one of the first functional area and the second functional area is provided with a write clock point and a read clock point. At least one of the first functional area and the second functional area is provided with a differential synchronization signal point.

[0019] In a possible implementation, 8 data input / output points are arranged in both the first functional area and the second functional area.

[0020] In a possible implementation, the first functional area is provided with five rows of signal points along the first direction, and the second functional area is provided with four rows of signal points along the first direction;

[0021] Among them, the second functional area is provided with a first write clock point, a first read clock point, and a first differential synchronization signal point, and the first differential synchronization signal point includes a first differential read synchronization signal point and a first differential write synchronization signal point;

[0022] The first functional area is provided with a second write clock point, a second read clock point, and a second differential synchronization signal point, and the second differential synchronization signal point includes a second differential read synchronization signal point and a second differential write synchronization signal point

[0023] A second aspect of the present application provides an electronic device, which includes the above semiconductor component.

[0024] An embodiment of the present application provides a semiconductor component and an electronic device, including a control chip and at least one LPDDR chip. The control chip includes 2 n channels, where n is an integer greater than or equal to zero. The LPDDR chip includes at least one first area, and one LPDDR wafer is disposed in the LPDDR chip corresponding to each first area. Among them, each channel of the control chip is correspondingly connected to an LPDDR wafer to perform data transmission between the control chip and the LPDDR chip, and realize the work of data communication and data calculation. When n is a positive integer, the LPDDR wafers corresponding to at least some of the channels of the control chip are located in different LPDDR chips, so that the multi-channel control chip can be electrically connected to multiple LPDDR chips, improving the matching compatibility with the multi-channel control chip, increasing the overall bandwidth, while improving the applicability of the LPDDR chip and reducing the development cost and management cost of the LPDDR chip.

[0025] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions, and the beneficial effects brought by these technical features of the technical solutions, other technical problems that can be solved by the semiconductor component and the electronic device provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific implementation manner. Description of the Drawings

[0026] The drawings here are incorporated into the specification and constitute a part of this specification, showing the embodiments that conform to the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the description of the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] The realization of the purpose, functional features and advantages of this application will be further described with reference to the embodiments and the accompanying drawings. Through the above-mentioned accompanying drawings, the specific embodiments of this application have been shown, and there will be more detailed descriptions hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments.

[0028] Figure 1 The first connection schematic diagram of the control chip and the LPDDR chip provided by the embodiment of this application;

[0029] Figure 2 The second connection schematic diagram of the control chip and the LPDDR chip provided by the embodiment of this application;

[0030] Figure 3 The third connection schematic diagram of the control chip and the LPDDR chip provided by the embodiment of this application;

[0031] Figure 4 The fourth connection schematic diagram of the control chip and the LPDDR chip provided by the embodiment of this application;

[0032] Figure 5 The fifth connection schematic diagram of the control chip and the LPDDR chip provided by the embodiment of this application;

[0033] Figure 6 The sixth connection schematic diagram of the control chip and the LPDDR chip provided by the embodiment of this application;

[0034] Figure 7 The seventh connection schematic diagram of the control chip and the LPDDR chip provided by the embodiment of this application;

[0035] Figure 8 The cross-sectional view of the LPDDR chip provided by the embodiment of this application;

[0036] Figure 9 A layout schematic diagram of the electrical connection balls on the circuit board provided by the embodiment of this application;

[0037] Figure 10 A layout schematic diagram of the signal points on the circuit board provided by the embodiment of this application;

[0038] Figure 11 Another layout schematic diagram of the signal points on the circuit board provided by the embodiment of this application.

[0039] Explanation of reference numerals:

[0040] 100 - Circuit board; 110 - Encapsulation area; 111 - First functional area; 112 - Second functional area; 113 - Control area; 200 - LPDDR wafer; 300 - Electrical contact ball; 400 - Control chip; 500 - LPDDR chip. Detailed implementation manner

[0041] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0042] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non - exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0043] It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining". Furthermore, as used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should be further understood that the terms "comprising", "including" indicate the presence of features, steps, operations, elements, components, categories, and / or groups, but do not preclude the presence, occurrence or addition of one or more other features, steps, operations, elements, components, categories, and / or groups. The terms "or", "and / or", "including at least one of the following" and the like used in this application may be interpreted inclusively, or mean any one or any combination. For example, "including at least one of the following: A, B, C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C", and again, "A, B or C" or "A, B and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C". An exception to this definition only occurs when the combination of elements, functions, steps or operations are mutually exclusive in some way.

[0044] It should be understood that although the steps in the flowcharts in the embodiments of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this application, the execution of these steps has no strict order limitation, and they can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and their execution order is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0045] Depending on the context, the words "if", "when" as used herein may be interpreted as "when" or "while" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detecting (stated condition or event)" may be interpreted as "when determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)".

[0046] It should be understood that the specific embodiments described herein are merely for explaining the present application and are not intended to limit the present application.

[0047] In subsequent descriptions, suffixes such as "module", "component", or "unit" used to represent elements are only for the convenience of explaining the present application and have no specific meaning in themselves. Therefore, "module", "component", or "unit" can be used interchangeably.

[0048] The LPDDR chip is a type of volatile memory product, characterized by low power consumption and small size, and is specifically used for mobile electronic devices. In some solutions, 315 balls are mainly used to individually package the LPDDR chip. The 315 balls can be understood as 315 solder balls or copper balls electrically connected between the LPDDR chip and the circuit board.

[0049] As described in the background art, when the LPDDR chip is packaged with 315 balls, the package size is 15 mm × 12.4 mm, occupying a relatively large area. Therefore, this packaging method is mostly used for large electronic devices such as notebook computers. For small electronic devices such as smart phones and wearable devices, this packaging method cannot be well adapted. Taking a smart phone as an example, the functional design of the phone motherboard is becoming more and more refined and complex, and the area available for the LPDDR chip to occupy is continuously compressed. However, the above-mentioned LPDDR chip with 315 balls occupies too much area and is very unfriendly to the design of the phone motherboard.

[0050] The LPDDR chip is usually dual-channel, and not all control chips connected to the LPDDR chip are dual-channel. Some control chips are single-channel or quad-channel. The adaptability between the LPDDR chip and the control chip is poor, and it is difficult to support various forms of control chips, resulting in relatively poor overall bandwidth performance.

[0051] In view of this, the embodiments of the present application provide a semiconductor component and an electronic device, including a control chip and at least one LPDDR chip. The control chip includes 2 n channels, where n is an integer greater than or equal to zero. The LPDDR chip includes at least one first region, and a LPDDR wafer is disposed in the LPDDR chip corresponding to each first region. Among them, each channel of the control chip is correspondingly connected to a LPDDR wafer to perform data transmission between the control chip and the LPDDR chip, and realize the work of data communication and data calculation. When n is a positive integer, the LPDDR wafers corresponding to at least some of the channels of the control chip are located in different LPDDR chips, so that the multi-channel control chip can be electrically connected to multiple LPDDR chips, improving the matching compatibility with the multi-channel control chip, increasing the overall bandwidth, and at the same time improving the applicability of the LPDDR chip and reducing the development cost and management cost of the LPDDR chip.

[0052] The following provides a detailed description of the semiconductor component provided in the embodiments of the present application and the electronic device equipped with the semiconductor component.

[0053] The embodiments of the present application provide an electronic device, which can be a large-scale electronic device or a small-scale electronic device. Specifically, the electronic device can be a terminal device, and the terminal device can also be referred to as a terminal, a user equipment (UE), a mobile station (MS), a mobile terminal (MT), etc.

[0054] The electronic device includes, but is not limited to, a mobile phone, a smart TV, a wearable device, a tablet computer (Pad), a computer with wireless transceiver function, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc.

[0055] The above-mentioned electronic device includes a semiconductor component. Refer to Figures 1 to 7 , the semiconductor component includes a control chip 400 and at least one LPDDR chip 500. The at least one LPDDR chip 500 is disposed on one side of the control chip 400 and is electrically connected to the control chip 400. The control chip 400 can adjust and control the working state of the LPDDR chip 500. Among them, the control chip 400 can be a system on chip (SOC), which has good integration and fast operation speed. The system on chip can be an existing system on chip, which will not be elaborated here.

[0056] Optionally, the control chip 400 includes 2 n channels, where n is an integer greater than or equal to zero, that is, the control chip 400 supports 2 nA control chip 400 with n channels, where n can be 0, 1, 2, etc. Optionally, the control chip 400 includes a single channel, that is, the control chip 400 is a control chip 400 supporting single-channel data exchange; for another example, the control chip 400 includes a dual channel, that is, the control chip 400 is a control chip 400 supporting dual-channel data exchange; optionally, the control chip 400 includes a quad channel, that is, the control chip 400 is a control chip 400 supporting quad-channel data exchange. Among them, the quad-channel control chip 400 can give full play to the multi-core characteristics of the control chip 400, improve the overall bandwidth performance, and meet data communication or data calculation.

[0057] The LPDDR chip 500 includes at least one first area. Optionally, the LPDDR chip 500 includes 1, 2, or 4 first areas. One LPDDR wafer 200 is provided in the LPDDR chip 500 corresponding to each first area, and the LPDDR wafer 200 forms a channel of the LPDDR chip 500. Optionally, the LPDDR wafer 200 is an LPDDR5 wafer, and optionally, the LPDDR chip 500 is an LPDD5 chip 500.

[0058] Optionally, pins can be arranged in the edge area of the LPDDR wafer 200. The pins of the LPDDR wafer 200 are connected to the circuits arranged inside the LPDDR wafer 200, so as to lead out the internal circuit of the LPDDR wafer 200 through the pins and connect it to the peripheral circuit. Each pin of the LPDDR wafer 200 has its specific function and is used to transmit signals with different functions. Optionally, each pin transmits signals such as data transmission signals, power supply signals, control signals, and ground signals between the LPDDR wafer 200 and the peripheral circuit.

[0059] An LPDDR chip 500 can include 1 LPDDR wafer 200, or more LPDDR wafers 200. When the LPDDR chip 500 includes more than two LPDDR wafers 200, the first areas of the LPDDR chip 500 are even numbers, and the number of LPDDR wafers 200 is correspondingly an even number. Optionally, the first areas of the LPDDR chip 500 are 2 or 4, and the number of LPDDR wafers 200 is correspondingly 2 or 4, and these LPDDR wafers 200 are arranged symmetrically.

[0060] Optionally, each channel of the control chip 400 is correspondingly connected to an LPDDR wafer 200, that is, each channel of the control chip 400 is correspondingly connected to the channel of the LPDDR chip 500, so as to perform data transmission between the control chip 400 and the LPDDR chip 500, and realize the work of data communication and data calculation. Optionally, when n is a positive integer, the LPDDR wafers 200 corresponding to at least some of the channels of the control chip 400 are located in different LPDDR chips 500, so that the multi-channel control chip 400 can be electrically connected to multiple LPDDR chips 500, improving the matching compatibility with the multi-channel control chip 400, increasing the overall bandwidth, while improving the applicability of the LPDDR chip 500 and reducing the development cost and management cost of the LPDDR chip 500.

[0061] In some possible embodiments, refer to Figures 1 to 3 , the LPDDR chip 500 includes a first region, the LPDDR chip 500 correspondingly includes an LPDDR wafer 200, and the LPDDR chip 500 is single-channel. Each channel of the control chip 400 is electrically connected to the LPDDR wafer 200 of an LPDDR chip 500. Optionally, as Figure 1 shown, the control chip 400 includes 1 channel, that is, the control chip 400 is single-channel. The channel of the control chip 400 is correspondingly connected to an LPDDR wafer 200, and the LPDDR wafer 200 is correspondingly connected to an LPDDR chip 500, and the semiconductor component forms a structure of a single control chip 400 and a single LPDDR chip 500.

[0062] Optionally, as Figure 2 shown, the control chip 400 includes 2 channels, that is, the control chip 400 is dual-channel. Each channel of the control chip 400 is correspondingly connected to an LPDDR wafer 200, and the control chip 400 is correspondingly connected to two LPDDR chips 500, and the semiconductor component forms a structure of a single control chip 400 and dual LPDDR chips 500.

[0063] Optionally, as Figure 3 shown, the control chip 400 includes 4 channels, that is, the control chip 400 is dual-channel. Each channel of the control chip 400 is correspondingly connected to an LPDDR wafer 200, and the control chip 400 is correspondingly connected to four LPDDR chips 500, and the semiconductor component forms a structure of a single control chip 400 and four LPDDR chips 500.

[0064] In some other possible embodiments, refer to Figures 4 to 7, the LPDDR chip 500 includes two first regions, and the two first regions are symmetrically arranged. Each first region corresponds to an LPDDR wafer 200, and the second region is used to transmit a ground signal to ground the two LPDDR wafers 200 respectively. The LPDDR chip 500 further includes a second region located between the two first regions. The second region is adjacent to the two first regions, and the two first regions are symmetrically arranged with respect to the second region.

[0065] In this way, the LPDDR chip 500 correspondingly includes two symmetrically arranged LPDDR wafers 200. One of the two LPDDR wafers 200 forms the A channel of the LPDDR chip 500, and the other LPDDR wafer 200 forms the B channel of the LPDDR chip 500. The LPDDR chip 500 is a dual-channel one. The second region is adjacent to the two first regions to reduce the overall package area of the LPDDR chip 500.

[0066] Optionally, one of the two LPDDR wafers 200 of at least part of the LPDDR chips 500 is electrically connected to the control chip 400 correspondingly, and the other LPDDR wafer 200 is not connected. In this way, at least one LPDDR chip 500 uses only one of the LPDDR wafers 200 for external connection, that is, at least one LPDDR chip 500 is used as a single channel to improve the flexibility of the connection between the LPDDR chip 500 and the control chip 400.

[0067] Optionally, one of the LPDDR wafers 200 in each LPDDR chip 500 is connected, and the other LPDDR wafer 200 is not connected, that is, all the LPDDR chips 500 use single channels. Optionally, only one of the two LPDDR wafers 200 in some LPDDR chips 500 is connected, and both of the two LPDDR wafers 200 in another part of the LPDDR chips 500 are connected, that is, some LPDDR chips 500 use single channels and another part of the LPDDR chips 500 use dual channels. Optionally, both of the two LPDDR wafers 200 in each LPDDR chip 500 are connected, that is, all the LPDDR chips 500 use dual channels.

[0068] In some possible implementation manners, each channel of the control chip 400 is electrically connected to one of the two LPDDR wafers 200 of an LPDDR chip 500, and the other LPDDR wafer 200 is not connected, that is, all LPDDR chips 500 use single channels. In this way, each channel of the control chip 400 is correspondingly connected to an LPDDR chip 500. The LPDDR chip 500 is still dual-channel, and the original packaging, structure, and layout routing can be compatible, and the original substrate can also be used to avoid the development cost and management cost of re-developing a set of substrates.

[0069] Optionally, in terms of the packaging form of the LPDDR chip 500, the pins of one of the LPDDR wafers 200 can be directly defined as not connected (NC), and the pins of the other LPDDR wafer 200 can be defined as test pins. In this way, it is equivalent to only retaining one of the A channel and the B channel, and the other is not used.

[0070] Optionally, as Figure 4 shown, the control chip 400 includes 1 channel, that is, the control chip 400 is single-channel. The channel of the control chip 400 is correspondingly connected to one of the LPDDR wafers 200 in an LPDDR chip 500, and the other LPDDR wafer 200 is not connected. The semiconductor component forms a structure of a single control chip 400 and a single LPDDR chip 500.

[0071] Optionally, as Figure 5 shown, the control chip 400 includes 2 channels, that is, the control chip 400 is dual-channel. One channel of the control chip 400 is correspondingly connected to one of the LPDDR wafers 200 in an LPDDR chip 500, and the other LPDDR wafer 200 is not connected. The other channel of the control chip 400 is correspondingly connected to one of the LPDDR wafers 200 in another LPDDR chip 500, and the other LPDDR wafer 200 is not connected. The semiconductor component forms a structure of a single control chip 400 and two LPDDR chips 500.

[0072] Optionally, as Figure 6 shown, the control chip 400 includes 4 channels, that is, the control chip 400 is quad-channel. Each channel of the control chip 400 is correspondingly connected to one of the LPDDR wafers 200 in an LPDDR chip 500, and the other LPDDR wafer 200 is not connected. The semiconductor component forms a structure of a single control chip 400 and four LPDDR chips 500.

[0073] Optionally, one of the dual channels (Channel A and Channel B) of the LPDDR chip 500 is circuit - connected to the channel of the control chip 400 to achieve data communication and data calculation, and the other is not circuit - connected to the control chip 400. Regarding the selection of Channel A or Channel B, the placement layout of the electronic components in the electronic device needs to be considered to make the layout routing simpler.

[0074] In some other possible implementation manners, the control chip 400 includes at least four channels. The at least four channels are divided into multiple channel groups, each channel group includes two channels, and the two channels in each channel group are respectively electrically connected to the two LPDDR wafers 200 of an LPDDR chip 500. In this way, the control chip 400 can be connected to two or more LPDDR chips 500, and both the dual channels (Channel A and Channel B) of the LPDDR chip 500 will participate in data communication and data calculation. Among them, the above - mentioned two or more LPDDR chips 500 can be flat - assembled with the control chip 400 on one side of the control chip 400, or stacked - assembled (packaging on packaging, POP) with the control chip 400 on one side of the control chip 400.

[0075] Optionally, as Figure 7 shown, the control chip 400 includes four channels. Two of the channels of the control chip 400 are respectively electrically connected to the two LPDDR wafers 200 of an LPDDR chip 500, and the other two channels of the control chip 400 are respectively electrically connected to the two LPDDR wafers 200 of another LPDDR chip 500, forming a structure of a single control chip 400 and two LPDDR chips 500.

[0076] In the embodiments of the present application, referring to Figure 8 , the LPDDR chip 500 further includes a circuit board 100. The circuit board 100 is provided with at least one packaging area, and each LPDDR wafer 200 is packaged in each packaging area in a one - to - one correspondence. Among them, the packaging area corresponds to the first area, and the packaging area can be completely accommodated in the first area. For example, the edge of the packaging area can coincide with the edge of the first area. The packaging area also corresponds to the LPDDR wafer 200, and the LPDDR wafer 200 can be completely accommodated in the packaging area. For example, the edge of the LPDDR wafer 200 can coincide with the edge of the packaging area.

[0077] The circuit board 100 can be the main board in an electronic device. The circuit board 100 includes, but is not limited to, a printed circuit board (PCB), a flexible printed circuit (FPC), and a rigid-flex circuit board, etc. Other devices can also be provided on the circuit board 100. For example, a processor, a power manager, and other devices can be provided on the circuit board 100. The circuit board 100 serves to carry these devices and enable communication connections between these devices.

[0078] Refer to Figure 9 , a plurality of electrical contact balls 300 are provided between the LPDDR wafer 200 and the circuit board 100, and these electrical contact balls 300 can be arranged in an array as a whole. By providing the electrical contact balls 300, electrical connection between the LPDDR wafer 200 and the circuit board 100 can be achieved. The above electrical contact balls 300 can be solder balls (such as tin balls or copper balls) or conductive bumps. For example, the electrical contact balls 300 can be tin balls or copper balls. These electrical contact balls 300 can be electrically connected to the pins of the LPDDR wafer 200 through the internal lines of the LPDDR wafer 200, and the circuit board 100 can transmit signals to the peripheral circuit through the LPDDR wafer 200 to achieve electrical connection between the LPDDR wafer 200 and the peripheral circuit.

[0079] Each electrical contact ball 300 is electrically connected to the pin of the LPDDR wafer 200 through the internal line of the LPDDR wafer 200. This connection method can ensure that the signals on the pins can be accurately transmitted to the electrical contact balls 300, thereby realizing signal transmission between the LPDDR wafer 200 and the external circuit. That is to say, the plurality of electrical contact balls 300 provided between the LPDDR wafer 200 and the circuit board 100 can be regarded as a plurality of signal points arranged in the encapsulation area of the circuit board 100, and these signal points are led out by the respective pins of the LPDDR wafer 200. Among them, each signal point is used to transmit different signals.

[0080] Refer to Figures 8 to 10 , an encapsulation area 110 is arranged on the circuit board 100. Correspondingly, an LPDDR wafer 200 is encapsulated on the circuit board 100. The encapsulation area 110 can be divided into three sub-areas. In this embodiment, these three sub-areas are respectively defined as a first functional area 111, a second functional area 112, and a control area 113. In the encapsulation area 110, all electrical contact balls 300 (or all signal points) are distributed in the first functional area 111, the second functional area 112, and the control area 113, and there are no electrical contact balls 300 (or signal points) in the area outside the first functional area 111, the second functional area 112, and the control area 113.

[0081] The first functional area 111 and the second functional area 112 can be arranged in sequence along the first direction, and the control area 113 can be adjacently arranged on the same side of the first functional area 111 and the second functional area 112 along the second direction, where the first direction is perpendicular to the second direction. Optionally, the first direction can be Figure 9 and Figure 10 the Y direction shown in Figure 9 and Figure 10 the X direction shown in. The encapsulation area 110 jointly formed by the first functional area 111, the second functional area 112, and the control area 113 can be rectangular, and the adjacent two sides of the rectangle extend along the X direction and the Y direction respectively.

[0082] Hereinafter, taking the orientation shown in Figure 9 and Figure 10 as an example, all the electrical connection balls 300 (signal points) in the encapsulation area 110 are arranged in an array along the X direction and the Y direction. A group of electrical connection balls 300 located at the same position in the X direction and arranged in sequence along the Y direction is defined as a column of electrical connection balls 300. A group of electrical connection balls 300 located at the same position in the Y direction and arranged in sequence along the X direction is defined as a row of electrical connection balls 300. Moreover, the area occupied by one electrical connection ball 300 is defined as one signal point.

[0083] For the first functional area 111 and the second functional area 112, the arrangement modes of the first functional area 111 and the second functional area 112 in the first direction can be flexibly set. The total number of rows of all the electrical connection balls 300 arranged in the first direction in the first functional area 111 and the total number of rows of all the electrical connection balls 300 arranged in the first direction in the second functional area 112 can be the same or different. And, in the first direction, there can be a gap between the first functional area 111 and the second functional area 112, or there can be no gap between the first functional area 111 and the second functional area 112.

[0084] As an implementation manner, in the first direction, there can be a gap between the first functional area 111 and the second functional area 112. The gap mentioned here is in terms of the area occupied by a single electrical connection ball 300 (or a single signal point). That there is a gap between the first functional area 111 and the second functional area 112 means that the first functional area 111 and the second functional area 112 are completely separated in the first direction. Optionally, the first functional area 111 is close to

[0085] All the electric ball receivers 300 on one side (arranged along the second direction) of the second functional area 112 and all the electric ball receivers 300 on the side of the second functional area 112 close to the first functional area 111 (arranged along the second direction) include at least one interval of the electric ball receivers 300. It can also be understood that there is at least one row of blank positions between the first functional area 111 and the second functional area 112, and the blank positions are the positions where the electric ball receivers 300 are not set.

[0086] As another implementation manner, in the first direction, there may be no interval between the first functional area 111 and the second functional area 112. The so-called no interval means that the first functional area 111 and the second functional area 112 include an adjacent area in the first direction. Optionally, the first functional area 111 and the second functional area 112 may be completely adjacent, or the first functional area 111 and the second functional area 112 may be partially adjacent. In short, there is no complete row of blank positions between the first functional area 111 and the second functional area 112.

[0087] One row (along the second direction) of the first functional area 111 closest to the second functional area 112 is filled with electric ball receivers 300 (that is, there is no blank position in one row of the first functional area 111 closest to the second functional area 112), one row (along the second direction) of the second functional area 112 closest to the first functional area 111 is filled with electric ball receivers 300 (that is, there is no blank position in one row of the second functional area 112 closest to the first functional area 111), and the first functional area 111 and the second functional area 112 are adjacent. Optionally, there is at least one blank position in one row of the first functional area 111 closest to the second functional area 112 (along the second direction), and there is at least one blank position in one row of the second functional area 112 closest to the first functional area 111 (along the second direction). Except for the blank positions, the electric ball receivers 300 in this row of the first functional area 111 are adjacent to the electric ball receivers 300 in this row of the second functional area 112.

[0088] One row (along the second direction) of the first functional area 111 closest to the second functional area 112 is filled with electric ball receivers 300, and there is at least one blank position in one row of the second functional area 112 closest to the first functional area 111 (along the second direction). Except for the blank positions, the electric ball receivers 300 in this row of the first functional area 111 are adjacent to the electric ball receivers 300 in this row of the second functional area 112. There is at least one blank position in one row of the first functional area 111 closest to the second functional area 112 (along the second direction), and one row (along the second direction) of the second functional area 112 closest to the first functional area 111 is filled with electric ball receivers 300. Except for the blank positions, the electric ball receivers 300 in this row of the first functional area 111 are adjacent to the electric ball receivers 300 in this row of the second functional area 112.

[0089] In the second direction, the first functional area 111 and the second functional area 112 can be arranged in a one-sided alignment manner, and there are no complete columns of blank points in both the first functional area 111 and the second functional area 112. That is to say, in the second direction, the total number of columns occupied by all the electric receiving balls 300 in the first functional area 111 and the total number of columns occupied by all the electric receiving balls 300 in the second functional area 112 may not be the same. Exemplarily, a column of electric receiving balls 300 on one side edge in the first functional area 111 and a column of electric receiving balls 300 on the same side edge in the second functional area 112 are in the same column. A column of electric receiving balls 300 on the other side edge in the first functional area 111 and a column of electric receiving balls 300 on the same side edge in the second functional area 112 are in different columns.

[0090] A column of electric receiving balls 300 on the leftmost side in the first functional area 111 and a column of electric receiving balls 300 on the leftmost side in the second functional area 112 are in the same column. A column of electric receiving balls 300 on the rightmost side in the second functional area 112 and a column of electric receiving balls 300 on the rightmost side in the second functional area 112 are in different columns. Optionally, the total number of columns occupied by all the electric receiving balls 300 in the second functional area 112 is more than the total number of columns occupied by all the electric receiving balls 300 in the first functional area 111, and the right side of the second functional area 112 extends beyond the right side of the first functional area 111.

[0091] In this way, in the second direction, the electric receiving balls 300 in the first functional area 111 and the electric receiving balls 300 in the second functional area 112 are both arranged in a dense manner, there are no complete columns of blank points in both the first functional area 111 and the second functional area 112, and the areas occupied by the first functional area 111 itself and the second functional area 112 itself are both small.

[0092] For the control area 113 itself, all the electric receiving balls 300 in the control area 113 are arranged along the X direction and the Y direction. The electric receiving balls 300 in the control area 113 can be arranged in a dense manner. There are no complete rows of blank points and no complete columns of blank points in the control area 113. In this way, the area occupied by the control area 113 itself is small.

[0093] For the whole formed by the control area 113 and the first functional area 111 and the second functional area 112, the control area 113 is arranged on the same side of the first functional area 111 and the second functional area 112 in the second direction, and the control area 113 is adjacently arranged with the first functional area 111 and the second functional area 112. Figure 9 and Figure 10Taking the orientation shown as an example, the control area 113 is adjacently arranged on the right side of the first functional area 111 and the second functional area 112. In this way, in the second direction, there is no complete column of blank points between the control area 113 and the first functional area 111 and the second functional area 112. In the second direction, the overall encapsulation area 110 formed by the control area 113 and the first functional area 111 and the second functional area 112 has no complete column of blank points, and the overall occupied area of the encapsulation area 110 is relatively small.

[0094] In the first direction, the whole formed by the first functional area 111 and the second functional area 112 can occupy at least part of the area of the control area 113. In other words, in the first direction, the control area 113 can completely occupy the whole formed by the first functional area 111 and the second functional area 112, and the row of electrical connection balls 300 of the first functional area 111 that is farthest from the second functional area 112 will not exceed the row of electrical connection balls 300 on the side edge of the third row. Similarly, the row of electrical connection balls 300 of the second functional area 112 that is farthest from the first functional area 111 will not exceed the row of electrical connection balls 300 on the side edge of the third row.

[0095] The row of electrical connection balls 300 of the first functional area 111 that is farthest from the second functional area 112 can be arranged in the same row as the row of electrical connection balls 300 on the side edge of the control area 113. Optionally, between the row of electrical connection balls 300 of the first functional area 111 that is farthest from the second functional area 112 and the row of electrical connection balls 300 on the side edge of the control area 113, there are at least one row of blank points. Optionally, the row of electrical connection balls 300 of the second functional area 112 that is farthest from the first functional area 111 can be arranged in the same row as the row of electrical connection balls 300 on the side edge of the control area 113. Optionally, between the row of electrical connection balls 300 of the second functional area 112 that is farthest from the first functional area 111 and the row of electrical connection balls 300 on the side edge of the control area 113, there are at least one row of blank points.

[0096] As Figure 9 and Figure 10 shown, as an example, the row of electrical connection balls 300 of the first functional area 111 that is farthest from the second functional area 112 is arranged in the same row as the row of electrical connection balls 300 on the side edge of the control area 113. The row of electrical connection balls 300 of the second functional area 112 that is farthest from the first functional area 111 is arranged in the same row as the row of electrical connection balls 300 on the side edge of the control area 113. And, in the first direction, there are at least one row of blank points between the first functional area 111 and the second functional area 112.

[0097] With such a setting, in the encapsulation area 110 formed by the first functional area 111, the second functional area 112, and the control area 113 as a whole, there are no complete blank positions in a whole row or a whole column, and there is no space waste. Moreover, in the first direction, the whole formed by the first functional area 111 and the second functional area 112 is within the area occupied by the control area 113. In the second direction, one side of the first functional area 111 and the second functional area 112 is flush, and the control area 113 is adjacently arranged on the other side of the first functional area 111 and the second functional area 112, and the left and right sides of the whole encapsulation area 110 are flush. In this way, the area occupied by the encapsulation area 110 can be minimized to reduce the encapsulation area of the LPDDR wafer 200, so that the LPDDR wafer 200 can be better applied to small electronic devices.

[0098] Referring to Figure 9 and Figure 10 As shown, in this embodiment, in the first direction, the whole formed by the first functional area 111 and the second functional area 112 is located within the area occupied by the control area 113. On this basis, the total number of rows occupied by all the electrical connection balls 300 in the first functional area 111 and the total number of rows occupied by all the electrical connection balls 300 in the second functional area 112 add up to less than the total number of rows occupied by all the electrical connection balls 300 in the control area 113. In this way, there is at least one complete row of blank positions in the whole area formed by the first functional area 111 and the second functional area 112.

[0099] It can be two rows of electrical connection balls 300 at the mutually distant side edges of the first functional area 111 and the second functional area 112 shown in the figure, which are arranged in the same row as two rows of electrical connection balls 300 at the corresponding edges of the control area 113 respectively, and there is at least one complete row of blank positions between the first functional area 111 and the second functional area 112.

[0100] It can also be that there is no gap between the first functional area 111 and the second functional area 112, and there is at least one complete row of blank positions between the row of electrical connection balls 300 in the first functional area 111 that is farthest from the second functional area 112 and the row of electrical connection balls 300 at the corresponding edge of the control area 113 (the arrangement mode of the first functional area 111), and there is at least one complete row of blank positions between the row of electrical connection balls 300 in the second functional area 112 that is farthest from the first functional area 111 and the row of electrical connection balls 300 at the corresponding edge of the control area 113 (the arrangement mode of the second functional area 112). At least one of the arrangement mode of the first functional area 111 and the arrangement mode of the second functional area 112 is satisfied.

[0101] There may also be a gap between the first functional area 111 and the second functional area 112. At the same time, there is at least a complete row of blank points between the row of electrical connection balls 300 in the first functional area 111 that is farthest from the second functional area 112 and the row of electrical connection balls 300 at the corresponding edge of the control area 113 (the layout mode of the first functional area 111), and there is at least a complete row of blank points between the row of electrical connection balls 300 in the second functional area 112 that is farthest from the first functional area 111 and the row of electrical connection balls 300 at the corresponding edge of the control area 113 (the layout mode of the second functional area 112). At least one of the layout mode of the first functional area 111 and the layout mode of the second functional area 112 can meet the requirements.

[0102] With such a setting, in the overall area formed by the first functional area 111 and the second functional area 112, due to the existence of at least a complete row of blank points, these blank points that can form a complete row increase the area of the completely blank area in this overall area. The circuit boards 100 and the circuits in the LPDDR wafer 200 can be arranged in this completely blank area, which is convenient for the circuit layout design of the circuit boards 100 and the LPDDR wafer 200. Moreover, the relatively large completely blank area can ensure that there is enough spacing between adjacent circuits, reduce the short circuit of the circuits arranged in the circuit boards 100 and the LPDDR wafer 200, and is beneficial to improving the reliability of the chip packaging structure.

[0103] On this basis, since the first functional area 111 and the second functional area 112 are arranged on the same side of the control area 113 in the second direction, the at least a complete row of blank points existing in the overall area formed by the first functional area 111 and the second functional area 112 can make the completely blank area in this overall area extend to the edge of the side of the first functional area 111 and the second functional area 112 that is far from the third side. As Figure 9 and Figure 10 shown, in the overall area formed by the first functional area 111 and the second functional area 112, the completely blank area extends to the left edge of the packaging area 110.

[0104] Optionally, all the circuits arranged in the packaging area 110 on the circuit board 100 can extend to one side of the packaging area 110, and all the circuits can be led out from one side of the packaging area 110 to be connected to an external circuit. Referring to Figure 11 shown, the circuits arranged in the packaging area 110 on the circuit board 100 can all be led out from one side of the LPDDR wafer 200, and the external circuit connected to the LPDDR wafer 200 can be arranged on this side of the LPDDR wafer 200. In this way, the circuit layout between the chip packaging structure and the external circuit can be simplified, and the wiring difficulty of the circuit board 100 can be reduced.

[0105] Taking Figure 9 and Figure 10Taking the specific layout shown as an example, within a single encapsulation area 110, all the electrical connection balls 300 in the first functional area 111 altogether occupy five rows of signal points (rows A - E in the figure) and eight columns of signal points (columns 1 - 8 in the figure). All the electrical connection balls 300 in the second functional area 112 altogether occupy four rows of signal points (rows H - L in the figure) and ten columns of signal points (columns 1 - 10 in the figure). All the electrical connection balls 300 in the control area 113 altogether occupy eleven rows of signal points (rows A - L in the figure) and five columns of signal points (columns 9 - 13 in the figure).

[0106] There is a gap of two signal points between the first functional area 111 and the second functional area 112. Or rather, there are two complete blank rows of points (rows F and G in the figure) between the first functional area 111 and the second functional area 112. And the first functional area 111 includes two blank points, located at column 8 of row D and column 8 of row E respectively. The second functional area 112 includes three blank points, located at column 1 of row H, column 2 of row H, and column 1 of row K respectively. The control area 113 includes one blank point, located at column 13 of row E.

[0107] With such a setting, in this embodiment, by designing the quantity and positions of the electrical connection balls 300 (signal points) required to transmit various signals within the encapsulation area 110, the total quantity of the electrical connection balls 300 arranged within a single encapsulation area 110 can be 121. Compared with the encapsulation method in the related art, in the encapsulation method of this embodiment, the quantity of the electrical connection balls 300 is significantly reduced. And the layout of the electrical connection balls 300 within the encapsulation area 110 is compact, without a complete row of blank points and a complete column of blank points, and the occupied area of the encapsulation area 110 is relatively small. Therefore, by reducing the quantity of the electrical connection balls 300 and minimizing the occupied area of the encapsulation area 110, the area of the encapsulation area 110 can be significantly reduced, and the encapsulation area of the LPDDR wafer 200 can be reduced.

[0108] Optionally, the ball pitch L1 between adjacent two rows of electrical connection balls 300 is 0.5 mm, and the ball pitch L2 between adjacent two columns of electrical connection balls 300 is 0.6 mm (as Figure 9 shown). Compared with the encapsulation method in the related art, in the encapsulation method of this embodiment, the ball pitch between adjacent electrical connection balls 300 is reduced. Furthermore, the overall area of the encapsulation area 110 can be reduced, and the size of the LPDDR wafer 200 can be reduced. The reduction in the size of the LPDDR wafer 200 can save the space of the circuit board 100 and facilitate the layout design of other devices on the circuit board 100.

[0109] All signal points arranged within the single encapsulation area 110 are used to transmit different functional signals, and each signal point has an independent function. Optionally, the first functional area 111 and the second functional area 112 can be mainly used to arrange functional signal points, and the control area 113 can be mainly used to arrange control signal points. All signal points within the encapsulation area 110 can include at least two data input / output points (DQ), at least two power input / output points (VDD), at least one group of clock points (WCK), at least one group of differential synchronous signal points (RDQS), and at least one input data mask point (DMI).

[0110] Optionally, at least two ground points (VSS) are also arranged within the encapsulation area 110. Optionally, the data input / output points (DQ), the clock points (WCK), the differential synchronous signal points (RDQS), and the input data mask points (DMI) all belong to functional signal points, and these signal points can all be arranged within the first functional area 111 and the second functional area 112.

[0111] The following details the distribution design of each signal point in the encapsulation area 110. When there is one encapsulation area 110 provided on the circuit board 100, the electrically connected ball 300 arranged within this encapsulation area 110 serves as a signal transmission channel for the LPDDR chip 500. Taking Figure 10 the example shown, in this embodiment, the signal transmission channel of this LPDDR chip 500 is defined as channel A.

[0112] In a single encapsulation area 110, all data input / output points (DQ) can be entirely distributed within the first functional area 111 and the second functional area 112, and there are no data input / output points (DQ) within the control area 113. By centrally arranging the data input / output points (DQ) within the first functional area 111 and the second functional area 112, the area where the data input / output points (DQ) are located is clearly demarcated, facilitating the layout design of the data input / output points (DQ) and also facilitating the layout design of other signal points.

[0113] On this basis, the number of data input / output points (DQ) arranged within the first functional area 111 can be the same as the number of data input / output points (DQ) arranged within the second functional area 112. In this way, all data input / output points (DQ) are evenly distributed within the first functional area 111 and the second functional area 112, avoiding the phenomenon that one of the first functional area 111 and the second functional area 112 has an excessive number of data input / output points (DQ), and more space can be reserved within both the first functional area 111 and the second functional area 112 to arrange other signal points.

[0114] For ease of description, in this embodiment, all data input / output points (DQ) arranged in one of the first functional area 111 and the second functional area 112 are defined as the first group of data input / output points, and all data input / output points (DQ) arranged in the other of the first functional area 111 and the second functional area 112 are defined as the second group of data input / output points. The first group of data input / output points and the second group of data input / output points both include the same number of data input / output points (DQ).

[0115] Optionally, on the basis that the number of data input / output points (DQ) in the first group of data input / output points and the second group of data input / output points is the same, in this embodiment, there are no restrictions on the arrangement positions of the respective data input / output points (DQ) in the first group of data input / output points and the arrangement positions of the respective data input / output points (DQ) in the second group of data input / output points.

[0116] Taking the example that the first functional area 111 has five rows of signal points arranged along the first direction, one of the first group of data input / output points and the second group of data input / output points distributed in the first functional area 111 can be distributed in four rows of signal points in the first functional area 111, and there are no data input / output points (DQ) arranged in one row of signal points in the first functional area 111. Optionally, one of the first group of data input / output points and the second group of data input / output points distributed in the first functional area 111 is distributed in the four adjacent rows of signal points in the first functional area 111 close to the second functional area 112, and there are no data input / output points (DQ) arranged in the row of signal points in the first functional area 111 farthest from the second functional area 112.

[0117] Taking the example that the second functional area 112 has four rows of signal points arranged along the first direction, one of the first group of data input / output points and the second group of data input / output points distributed in the second functional area 112 is distributed in each row of signal points in the second functional area 112. That is to say, one of the first group of data input / output points and the second group of data input / output points distributed in the second functional area 112 occupies each row of signal points in the second functional area 112.

[0118] Along the second direction, at least one signal point is spaced between the first group of data input / output points and the control area 113. In other words, one of the first group of data input / output points is disposed in the first functional area 111 and the second functional area 112, and no data input / output points (DQ) are disposed in a column of signal points adjacent to the control area 113. Optionally, at least one signal point is spaced between the second group of data input / output points and the control area 113. In other words, one of the second group of data input / output points is disposed in the first functional area 111 and the second functional area 112, and no data input / output points (DQ) are disposed in a column of signal points adjacent to the control area 113.

[0119] Taking the example of the first functional area 111 including eight columns of signal points in the second direction and the second functional area 112 including ten columns of signal points in the second direction, in the second direction, the first group of data input / output points and the second group of data input / output points can both be distributed over a maximum of six consecutive columns of signal points. Taking the example of the first functional area 111 having five rows of signal points arranged along the first direction, the number of rows of signal points in the first functional area 111 is relatively large, and one of the first group of data input / output points and the second group of data input / output points distributed in the first functional area 111 can be distributed over five consecutive columns of signal points. Taking the example of the second functional area 112 having four rows of signal points arranged along the first direction, the number of rows of signal points in the second functional area 112 is relatively small, and one of the first group of data input / output points and the second group of data input / output points distributed in the second functional area 112 can be distributed over six consecutive columns of signal points.

[0120] Reference Figure 10 As shown, the number of data input and output points (DQ) in the package area 110 can be 16, namely DQ0-DQ15. The number of the first group of data input and output points is 8, namely DQ0-DQ7. The number of the second group of data input and output points is also 8, namely DQ8-DQ15.

[0121] Taking the LPDDR chip 500 as the A channel as an example, the 16 data input / output points (DQ) in the A channel are DQ0A - DQ15A respectively. Optionally, taking the example that the second group of data input / output points are arranged in the first functional area 111 and the first group of data input / output points are arranged in the second functional area 112, the 8 data input / output points (DQ) arranged in the first functional area 111 are DQ8A - DQ15A respectively, and the 8 data input / output points (DQ) arranged in the second functional area 112 are DQ0A - DQ7A respectively. The 8 data input / output points (DQ) DQ8A - DQ15A arranged in the first functional area 111 are distributed in rows B - E and columns 1 - 5, and the 8 data input / output points (DQ) DQ0A - DQ7A arranged in the second functional area 112 are distributed in rows H - L and columns 2 - 7.

[0122] Continue to refer to [[ID=4=4]]Figure 10 , in a single packaging area 110, the number of power input / output points (VDD) and ground points (VSS) is relatively large, and power input / output points (VDD) and ground points (VSS) can be distributed in the first functional area 111, the second functional area 112 and the control area 113. In this way, the power input / output points (VDD) and ground points (VSS) can be relatively evenly distributed in the entire packaging area 110, which is convenient for arranging the power lines (for transmitting power signals) and ground lines (for transmitting ground signals) in the circuit board 100 and the LPDDR chip 500. And, it can also reserve more scattered spaces, which is convenient for arranging other signal points.

[0123] Continue to refer to Figure 10 , the clock points (WCK) arranged in the packaging area 110 can include grouped write clock points (WCK T) and read clock points (WCK C). Among them, the write clock points (WCK T) and the read clock points (WCKC) can be arranged adjacent to each other, which is convenient for positioning the clock points (WCK) and also convenient for arranging the clock lines (for transmitting clock signals) in the circuit board 100 and the LPDDR chip 500.

[0124] In this embodiment, two sets of clock points (WCK) can be arranged in a single encapsulation area 110. The two sets of clock points can be respectively defined as a first clock point (WCK0) and a second clock point (WCK1). One of the first clock point (WCK0) and the second clock point (WCK1) can be arranged in the first functional area 111, and the other can be arranged in the second functional area 112. The first clock point (WCK0) includes an adjacent first write clock point (WCK0 T) and a first read clock point (WCK0 C), and the second clock point (WCK1) can include an adjacent second write clock point (WCK1 T) and a second read clock point (WCK1 C).

[0125] Taking the example that the first functional area 111 is arranged with five rows of signal points in the first direction, the number of rows of signal points in the first functional area 111 is relatively large. For the set of clock points (WCK) arranged in the first functional area 111 among the first clock point (WCK0) and the second clock point (WCK1), the write clock point (WCK T) and the read clock point (WCK C) in this set of clock points (WCK) can be adjacent to each other either in the first direction or in the second direction.

[0126] Taking the example that the second functional area 112 is arranged with four rows of signal points in the first direction, the number of rows of signal points in the second functional area 112 is relatively small. For the set of clock points (WCK) arranged in the second functional area 112 among the first clock point (WCK0) and the second clock point (WCK1), the write clock point (WCK T) and the read clock point (WCK C) in this set of clock points (WCK) can be adjacent to each other in the second direction.

[0127] As Figure 10 shown, taking the LPDDR chip 500 as channel A as an example, the first clock point (WCK0) can be located in the second functional area 112. The first write clock point (WCK0 T A) can be located at the 9th column of the Jth row in the second functional area 112, and the first read clock point (WCK0 C A) can be located at the 8th column of the Jth row in the second functional area 112. The second clock point (WCK1) can be located in the first functional area 111. The second write clock point (WCK1 T A) can be located at the 7th column of the Dth row in the first functional area 111, and the second read clock point (WCK1 C A) can be located at the 6th column of the Dth row in the first functional area 111.

[0128] Continue to refer to Figure 10, the differential synchronous signal points (RDQS) arranged in the encapsulation area 110 may include a group of differential read synchronous signal points (RDQS C) and differential write synchronous signal points (RDQS T). Optionally, the differential read synchronous signal points (RDQS C) and the differential write synchronous signal points (RDQS T) may be arranged adjacent to each other, which is convenient for positioning the differential synchronous signal points (RDQS) and also convenient for arranging the differential synchronous lines (for transmitting differential synchronous signals) in the circuit board 100 and the LPDDR chip 500.

[0129] In this embodiment, two groups of differential synchronous signal points (RDQS) may be arranged in a single encapsulation area 110. In this embodiment, the two groups of differential synchronous signal points (RDQS) are respectively defined as a first differential synchronous signal point (RDQS0) and a second differential synchronous signal point (RDQS1). One of the first differential synchronous signal point (RDQS0) and the second differential synchronous signal point (RDQS1) may be arranged in the first functional area 111, and the other may be arranged in the second functional area 112. The first differential synchronous signal point includes an adjacent first differential read synchronous signal point (RDQS0 C) and a first differential write synchronous signal point (RDQS0 T). The second clock point may include an adjacent second write clock point (RDQS1 C) and a second read clock point (RDQS1 T).

[0130] Taking the example that the first functional area 111 has five rows of signal points arranged in the first direction, the number of rows of signal points in the first functional area 111 is relatively large. For the one of the first differential synchronous signal point (RDQS0) and the second differential synchronous signal point (RDQS1) arranged in the first functional area 111, the differential read synchronous signal point (RDQSC) and the differential write synchronous signal point (RDQS T) in this group of differential synchronous signal points (RDQS) may be arranged adjacent to each other along the first direction or along the second direction. Taking the example that the second functional area 112 has four rows of signal points arranged in the first direction, the number of rows of signal points in the second functional area 112 is relatively small. For the one of the first differential synchronous signal point (RDQS0) and the second differential synchronous signal point (RDQS1) arranged in the second functional area 112, the differential read synchronous signal point (RDQSC) and the differential write synchronous signal point (RDQS T) in this group of differential synchronous signal points (RDQS) may be arranged adjacent to each other along the second direction.

[0131] Such as Figure 10As shown, taking the LPDDR chip 500 as the A channel as an example, the first differential synchronous signal point (RDQS0 A) can be located in the second functional area 112. The first differential read synchronous signal point (RDQS0C A) can be located at the 9th column of the Kth row in the second functional area 112. The first differential write synchronous signal point (RDQS0 T A) can be located at the 10th column of the Kth row in the second functional area 112. The second differential synchronous signal point (RDQS1 A) can be located in the first functional area 111. The second differential read synchronous signal point (RDQS1 C A) can be located at the 6th column of the Bth row in the first functional area 111. The second differential write synchronous signal point (RDQS1 T A) can be located at the 7th column of the Bth row in the first functional area 111.

[0132] Continue to refer to Figure 10 , in this embodiment, in a single packaging area 110, two input data mask points (DMI) can be set. In this embodiment, the two input data mask points (DMI) are respectively defined as the first input data mask point (DMI0) and the second input data mask point (DMI1). Among them, one of the first input data mask point (DMI0) and the second input data mask point (DMI1) can be located in the first functional area 111, and the other can be located in the second functional area 112.

[0133] As Figure 10 shown, taking the LPDDR chip 500 as the A channel as an example, the first input data mask point (DMI0 A) is arranged at the 9th column of the Kth row in the second functional area 112, and the second input data mask point (DMI1 A) is arranged at the 5th column of the Cth row in the first functional area 111.

[0134] Next, taking Figure 10 as an example, the layout structure of all signal points in the LPDDR chip 500 will be described.

[0135] The signal point at the Cth row of the first column is the eleventh data input / output point of the A channel of the LPDDR chip 500, and the signal point at the Eth row of the first column is the fourteenth data input / output point of the A channel of the LPDDR chip 500.

[0136] The signal point at the Bth row of the second column is the ninth data input / output point of the A channel of the LPDDR chip 500. The signal point at the Dth row of the second column is the thirteenth data input / output point of the A channel of the LPDDR chip 500. The signal point at the Jth row of the second column is the first data input / output point of the A channel of the LPDDR chip 500. The signal point at the Kth row of the second column is the power input / output point of the A channel of the LPDDR chip 500.

[0137] The signal point at the C-th row of the third column is the tenth data input / output point of Channel A of the LPDDR chip 500. The signal point at the E-th row of the third column is the fifteenth data input / output point of Channel A of the LPDDR chip 500. The signal point at the H-th row of the third column is the seventh data input / output point of Channel A of the LPDDR chip 500. The signal points at the A-th row and the K-th row of the third column are the power input / output points of Channel A of the LPDDR chip 500.

[0138] The signal point at the B-th row of the fourth column is the sixteenth data input / output point of Channel A of the LPDDR chip 500. The signal point at the J-th row of the fourth column is the first input data mask point of Channel A of the LPDDR chip 500. The signal point at the L-th row of the fourth column is the second data input / output point of Channel A of the LPDDR chip 500. The signal points at the A-th row, the C-th row, the D-th row, and the E-th row of the fourth column are the power input / output points of Channel A of the LPDDR chip 500.

[0139] The signal point at the A-th row of the fifth column is the power input / output point of Channel A of the LPDDR chip 500. The signal point at the C-th row of the fifth column is the second input data mask point of Channel A of the LPDDR chip 500. The signal point at the E-th row of the fifth column is the tenth data input / output point of Channel A of the LPDDR chip 500. The signal point at the H-th row of the fifth column is the sixth data input / output point of Channel A of the LPDDR chip 500. The signal point at the K-th row of the fifth column is the fifth data input / output point of Channel A of the LPDDR chip 500.

[0140] The signal point at the B-th row of the sixth column is the second differential read synchronization signal point of Channel A of the LPDDR chip 500. The signal point at the D-th row of the sixth column is the second read clock point of Channel A of the LPDDR chip 500. The signal point at the L-th row of the sixth column is the third data input / output point of Channel A of the LPDDR chip 500. The signal points at the C-th row and the J-th row of the sixth column are the power input / output points of Channel A of the LPDDR chip 500.

[0141] The signal point at the B-th row of the seventh column is the second differential write synchronization signal point of Channel A of the LPDDR chip 500. The signal point at the D-th row of the seventh column is the second write clock point of Channel A of the LPDDR chip 500. The signal point at the H-th row of the seventh column is the eighth data input / output point of Channel A of the LPDDR chip 500. The signal point at the K-th row of the seventh column is the fourth data input / output point of Channel A of the LPDDR chip 500. The signal points at the E-th row and the J-th row of the seventh column are the power input / output points of Channel A of the LPDDR chip 500.

[0142] The signal point at the Jth row in the eighth column is the first read clock point of the A channel of the LPDDR chip 500, and the signal points at the Ath row and the Lth row in the eighth column are the power input / output points of the A channel of the LPDDR chip 500.

[0143] The signal point at the Bth row in the ninth column is the third address point of the A channel of the LPDDR chip 500, the signal point at the Dth row in the ninth column is the first address point of the A channel of the LPDDR chip 500, the signal point at the Gth row in the ninth column is the second chip select point of the A channel of the LPDDR chip 500, the signal point at the Jth row in the ninth column is the first write clock point of the A channel of the LPDDR chip 500, the signal point at the Kth row in the ninth column is the first differential read synchronization signal point of the A channel of the LPDDR chip 500, and the signal points at the Cth row, the Eth row, and the Hth row in the ninth column are the power input / output points of the A channel of the LPDDR chip 500.

[0144] The signal point at the Bth row in the tenth column is the second address point of the A channel of the LPDDR chip 500, the signal point at the Dth row in the tenth column is the sixth address point of the A channel of the LPDDR chip 500, the signal point at the Fth row in the tenth column is the reserved point of the LPDDR chip 500, the signal point at the Gth row in the tenth column is the first chip select point of the A channel of the LPDDR chip 500, the signal point at the Kth row in the tenth column is the first differential read synchronization signal point of the A channel of the LPDDR chip 500, and the signal points at the Ath row and the Hth row in the tenth column are the power input / output points of the A channel of the LPDDR chip 500.

[0145] The signal point at the Cth row in the eleventh column is the seventh address point of the A channel of the LPDDR chip 500, the signal point at the Eth row in the eleventh column is the fourth address point of the A channel of the LPDDR chip 500, and the signal points at the Bth row, the Dth row, the Jth row, the Kth row, and the Lth row in the eleventh column are the power input / output points of the A channel of the LPDDR chip 500.

[0146] The signal point at the Cth row in the twelfth column is the fifth address point of the A channel of the LPDDR chip 500, the signal point at the Fth row in the twelfth column is the differential clock signal point of the A channel of the LPDDR chip 500, the signal point at the Gth row in the twelfth column is the differential clock signal point of the A channel of the LPDDR chip 500, and the signal points at the Jth row and the Lth row in the twelfth column are the power input / output points of the A channel of the LPDDR chip 500.

[0147] The signal point at the Jth row of the thirteenth column is the drive strength calibration signal point of the A channel of the LPDDR chip 500, and the signal points at the Cth row, Dth row, Kth row, and Lth row of the thirteenth column are the power input / output points of the A channel of the LPDDR chip 500.

[0148] The signal point at the Gth row of the tenth column is the first chip select point of the A channel of the LPDDR chip 500, and this signal point is used to control the operation of the second functional area 112. The signal point at the Gth row of the ninth column is the second chip select point of the A channel of the LPDDR chip 500, and this signal point is used to control the operation of the first functional area 111. During the operation of the LPDDR chip 500, the control area 113 operates, and at least one of the first functional area 111 and the second functional area 112 operates. Among them, it can be that the first functional area 111 operates and the second functional area 112 is idle, or the first functional area 111 is idle and the second functional area 112 operates, or the first functional area 111 and the second functional area 112 operate simultaneously.

[0149] The total number of electrical connection balls 300 arranged in the above LPDDR chip 500 is 121. Compared with the 315-ball packaging method in the related art, in the 121-ball packaging method of this embodiment, the number of electrical connection balls 300 is significantly reduced.

[0150] Refer to Figure 11 , Figure 11 is another layout schematic diagram of the signal points on the circuit board provided by the embodiment of the present application. There are two packaging areas 110 arranged on the circuit board 100, and the two packaging areas 110 on the circuit board 100 can be arranged along the first direction and symmetrically set. The first functional areas 111 of the two packaging areas 110 can be far away from each other and symmetrically set with the second direction as the symmetry direction, the second functional areas 112 of the two packaging areas 110 can be close to each other and symmetrically set with the second direction as the symmetry direction, and the control areas 113 of the two packaging areas 110 are also symmetrically set with the second direction as the symmetry direction.

[0151] Among the two packaging areas 110, the electrical connection balls 300 arranged in the upper packaging area 110 serve as a signal transmission channel of the LPDDR chip 500, and the electrical connection balls 300 arranged in the lower packaging area 110 serve as another signal transmission channel of the chip 500. For the convenience of description, Figure 11 the upper signal transmission channel is defined as the A channel of the LPDDR chip 500, and the lower signal transmission channel is defined as the B channel of the LPDDR chip 500.

[0152] In some examples, there may be at least one row of signal points between the two encapsulation areas 110. The at least one row of signal points faces the second area and is completely located within the second area. In this way, at least one electrical connection ball 300 can be provided between the two encapsulation areas 110. The electrical connection ball 300 between the two encapsulation areas 110 is used to transmit a ground signal. Or rather, the electrical connection ball 300 between the two encapsulation areas 110 serves as a ground point position for grounding the LPDDR wafers 200 encapsulated in the two encapsulation areas 110 respectively.

[0153] More than two electrical connection balls 300 can be provided between the two encapsulation areas 110, and the more than two electrical connection balls 300 all serve as ground point positions. Moreover, the more than two electrical connection balls 300 can occupy one row of signal points, and there is only one row of signal points between the two encapsulation areas 110. In this way, the overall occupied area of the two encapsulation areas 110 is relatively small, and the minimum encapsulation area of the two LPDDR wafers 200 can be achieved. For example, the more than two electrical connection balls 300 for transmitting ground signals can be arranged adjacent to each other in sequence along the second direction.

[0154] In other examples, there may be no interval between the two encapsulation areas 110, and the two encapsulation areas 110 are arranged adjacent to each other in the first direction. In other words, no electrical connection ball may be provided between the two encapsulation areas 110, and there are no signal points between the two encapsulation areas 110. Correspondingly, the LPDDR chip 500 does not include the second area. This embodiment does not limit this.

[0155] As Figure 10 shown, three electrical connection balls 300 (ground point positions) for transmitting ground signals are provided between the two encapsulation areas 110. The three electrical connection balls 300 are all located in the Mth row, and the three electrical connection balls 300 are arranged adjacent to each other in sequence and are located on the side of the control area 113 away from the first functional area 111 and the second functional area 112, and are located at the 11th column, the 12th column, and the 13th column of the Mth row respectively. All the electrical connection balls 300 of the lower encapsulation area 110 altogether occupy eleven rows of signal points (the Nth row - the ACth row in the figure) and 13 columns of signal points (the 1st column - the 13th column in the figure), which will not be elaborated here.

[0156] Taking the number of the electrical connection balls 300 for transmitting ground signals provided between the two encapsulation areas 110 as 3 as an example, the total number of the electrical connection balls 300 arranged on the circuit board 100 for the two encapsulation areas 110 is 245. Compared with the 315-ball encapsulation method in the related art, in the 245-ball encapsulation method of this embodiment, the number of the electrical connection balls 300 is significantly reduced.

[0157] When two channels of the LPDDR chips 500 are packaged on the circuit board 100 and both channels of the two LPDDR chips 500 are working, the control areas 113 of the channels of each LPDDR chip 500 are all working, and at least one of the first functional areas 111 and the second functional areas 112 of the channels of each LPDDR chip 500 is working. Optionally, the first functional areas 111 of the channels of the two LPDDR chips 500 may all be working and the second functional areas 112 may all be idle, or the first functional areas 111 of the channels of the two LPDDR chips 500 may all be idle and the second functional areas 112 may all be working, or the first functional areas 111 and the second functional areas 112 of the channels of the two LPDDR chips 500 may all be working simultaneously.

[0158] It can be understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided by the embodiments of the present application. The technical solutions of the present application can also be applied to other scenarios. For example, as is known to those of ordinary skill in the art, with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0159] The technical features of the technical solutions of the present application can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as falling within the scope recorded in the present application.

[0160] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor component, characterized in that, Comprising: Control chip, the control chip includes 2 n channels, where n is an integer greater than or equal to zero; At least one LPDDR chip, the LPDDR chip including at least one first region, and a LPDDR wafer being disposed within the LPDDR chip corresponding to the first region; Each of the channels of the control chip is correspondingly connected to one of the LPDDR wafers. When n is a positive integer, the LPDDR wafers corresponding to at least a partial number of the channels of the control chip are located in different LPDDR chips.

2. The semiconductor component according to claim 1, wherein, The LPDDR chip includes one of the first regions, and each of the channels of the control chip is electrically connected to the LPDDR wafer of one of the LPDDR chips.

3. The semiconductor component according to claim 1, wherein The LPDDR chip includes two of the first regions, and the two first regions are symmetrically arranged.

4. The semiconductor component according to claim 3, characterized in that, One of the two LPDDR wafers of at least a part of the LPDDR chips is correspondingly electrically connected to the control chip, and the other LPDDR wafer is not connected.

5. The semiconductor component according to claim 4, characterized in that, Each of the channels of the control chip is correspondingly electrically connected to one of the two LPDDR wafers of one of the LPDDR chips, and the other LPDDR wafer is not connected; or, The control chip includes at least four of the channels, and the at least four channels are divided into a plurality of channel groups. Each of the channel groups includes two of the channels, and the two channels within the channel group are correspondingly electrically connected to the two LPDDR wafers of one of the LPDDR chips.

6. The semiconductor component according to any one of claims 1-5, characterized in that, The LPDDR chip further includes a circuit board, the circuit board including at least one packaging region corresponding to the first region, and a plurality of signal points being arranged within the packaging region.

7. The semiconductor component according to claim 6, characterized in that, The packaging region includes a first functional region, a second functional region, and a control region. The first functional region and the second functional region are sequentially arranged along a first direction, and the control region is adjacently arranged on the same side of the first functional region and the second functional region along a second direction perpendicular to the first direction.

8. The semiconductor component according to claim 7, characterized in that, Including at least one of the following: At least two data input / output points are arranged within both the first functional region and the second functional region; At least two power input / output points are arranged within both the first functional region and the second functional region; A write clock point and a read clock point are arranged within at least one of the first functional region and the second functional region; Differential synchronous signal points are arranged within at least one of the first functional region and the second functional region.

9. The semiconductor component according to claim 8, characterized in that, Including at least one of the following: Eight of the data input / output points are arranged within both the first functional region and the second functional region; Five rows of the signal points are arranged within the first functional region along the first direction, and four rows of the signal points are arranged within the second functional region along the first direction; A first write clock point, a first read clock point, and a first differential synchronous signal point are arranged within the second functional region. The first differential synchronous signal point includes a first differential read synchronous signal point and a first differential write synchronous signal point. In the first functional area, there are arranged a second write clock point, a second read clock point, and a second differential synchronization signal point, and the second differential synchronization signal point includes a second differential read synchronization signal point and a second differential write synchronization signal point.

10. An electronic device, characterized in that, It includes the semiconductor component according to any one of claims 1 to 9.

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