Semiconductor packaging structure

Abstract

Some embodiments of the present application provide a semiconductor package structure comprising: a first substrate; a second substrate; the passive component is arranged between the first substrate and the second substrate, and the passive component is provided with two electrodes; at least part of the blocking piece extends to the position between the two electrodes; and a molding compound covering the passive component and the stopper, in which the molding compound covers an upper surface of the stopper away from the passive component and a side surface connecting the upper surface and a lower surface opposite to the upper surface. According to the semiconductor packaging structure provided by the invention, the corresponding layering and solder protruding problems are solved in a manner of not changing the structural characteristics and the component characteristics of the semiconductor packaging structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor package structure. Background Art

[0002] In the prior art, as Figure 1A and Figure 1B show, a first substrate 11 and a second substrate 12 of a semiconductor package structure 10 are connected by solder connectors 15, and the space between the first substrate 11 and the second substrate 12 is filled with a molding compound 13. A passive component 14 provided with corresponding electrodes 14t is connected between the corresponding solder connectors 15. Further, pads 11P1 and 11P2 are respectively provided at opposite sides of the first substrate 11, pads 12P1 and 12P2 are respectively provided at opposite sides of the second substrate 12, and the solder connectors 15 are respectively connected to the pads 11P1 and 12P1. However, as Figure 1B shows, the problem existing in the semiconductor package structure 10 is that delamination C occurs between the molding compound 13 and the surface 14s of the passive component 14. Specifically, referring to Figures 1C to 1E , Figures 1C to 1E , the generation of the relevant delamination C will be introduced in detail in combination with the semiconductor package structure 10'. Figures 1D to 1E shows Figure 1C an enlarged view of the region A' of Figure 1D and Figure 1E . It can be seen from

[0003] that delamination C occurs between the molding compound 13 and the surface 14s of the passive component 14 because the molding compound 13 (an organic material such as molding compound) and the surface 14s of the passive component 14 (an inorganic material such as ceramic) are different materials, and it is difficult to form a bond between the organic and non-organic materials, resulting in poor bonding force at the interface between the molding compound 13 and the surface 14s of the passive component 14. Moreover, thermal stress will be generated in the product structure of the semiconductor package structure 10', causing the internal structure to stretch up and down, resulting in delamination C being more likely to occur at the surface 14s with poor bonding force.

[0003] Referring back to Figure 1A and Figure 1B , although Figure 1B only shows the delamination C generated in the region A of the semiconductor package structure 10, it should be understood that delamination C can also occur in other regions of the semiconductor package structure 10. Further, the region A where the delamination C occurs will cause the solder (such as tin) in the solder connectors 15 to melt and flow to both sides of the molding compound 13 when passing through a thermal process (>240 °C), resulting in solder protrusion and electrical short circuit, thereby causing electrical failure of the product of the semiconductor package structure 10.

[0004] Next, referring to Figures 1F to 1G-2 , Figures 1F to 1G-2respectively show Figure 1B a scanning image of area A of the semiconductor package structure 10. Figure 1F A scanning image of area A is shown, from which Figure 1F it can be seen that delamination C is generated between the molding compound 13 and the passive component 14. Further, Figure 1F-1 and Figure 1F-2 show Figure 1F a scanning image of area R of Figures 1F-1 to 1F-2 from which delamination C can be clearly seen. In addition, Figure 1F-1 also specifically shows delamination C in the left area R1, the middle area R2, and the right area R3 in area R, and the height of the detected delamination C in the z direction is 1 - 3 μm. After that, referring to FIG. 1G and Figures 1G-1 to 1G-2 , FIG. 1G shows a scanning image of area A, Figure 1G-1 and Figure 1G-2 show a scanning image of area R' of FIG. 1G, and Figure 1G-1 and Figure 1G-2 show the detailed condition of the solder extrusion SE, and the thickness of the solder extrusion SE in the z direction is 1 - 3 μm, and the solder extrusion SE may occur on the entire surface (such as the surface 14s of the passive component 14) between the molding compound 13 and the passive component 14. For example, the surface x - y area of the surface 14s of the passive component 14 can be: 360 μm x 660 μm.

[0005] In summary, for the semiconductor package structure 10 applied to the power module 3D stacking structure, it faces the problem of delamination C of the molding compound 13. For example, after high - temperature treatment, surface structure stress causes delamination C of the molding compound 13, that is, large structure stress causes delamination between the molding compound - 13 and the passive component 14 because of the poor adhesion between the encapsulation material of the molding compound 13 and the ceramic material at the surface 14s of the passive component 14. Further, solder extrusion SE can be formed from this delamination C, and the solder extrusion SE further causes electrical failure of the semiconductor package structure 10. Specifically, in the 3D stacking structure of the current power supply device, that is, the semiconductor package structure 10, there is a situation of delamination C and solder extrusion SE between the molding compound 13 above and below the passive component 14, and the height of the delamination C in the z direction is 1 - 3 μm, the thickness of the solder extrusion SE in the Z direction is 1 - 3 μm, and it may occur on the entire surface 14s of the passive component 14, and the x - y area of the surface 14s can be: 360 μm x 660 μm.

[0006] To address this problem, there are two solutions in the prior art. The first is to change the properties of the encapsulation material such as the molding compound 13 that is joined to the passive component 14, but this easily changes the structural characteristics of the product of the semiconductor package structure 10 (such as hardness, moisture absorption rate, etc.). The second is to modify the surface roughness of the surface 14s of the passive component 14 to enhance the bonding force between the encapsulation material such as the molding compound 13 and the surface 14s of the passive component 14, but this technique has a risk of affecting the characteristics of the passive component 14 itself. Therefore, it is necessary to provide a semiconductor package structure with better performance to avoid the above-mentioned delamination and solder protrusion problems, and it is necessary to solve them in a way that does not change the structural characteristics of the product and the characteristics of the components. Summary of the Invention

[0007] This application provides a semiconductor package structure with better performance by increasing the bonding force between the molding compound and the passive component, and solves the problem of solder protrusion caused by delamination between the molding compound and the passive component.

[0008] Some embodiments of this application provide a semiconductor package structure, including: a first substrate; a second substrate; a passive component disposed between the first substrate and the second substrate, the passive component having two electrodes, wherein each of the two electrodes extends along a side portion of the passive component to surfaces of an upper surface and a lower surface of the passive component; a barrier, at least a portion of the barrier extending between the two electrodes; and a molding compound encapsulating the passive component and the barrier, wherein the molding compound encapsulates an upper surface of the barrier away from the passive component and a side surface connecting the upper surface and a lower surface opposite to the upper surface.

[0009] In some embodiments, the first substrate is connected to the second substrate through solder connectors, and the passive component is sandwiched between two adjacent solder connectors.

[0010] In some embodiments, the barrier is respectively disposed at ends of the corresponding electrodes of the two electrodes and extends beyond the corresponding electrodes.

[0011] In some embodiments, the molding compound further encapsulates a lower surface of the barrier.

[0012] In some embodiments, the barrier and the corresponding electrode form a stepped structure.

[0013] In some embodiments, a portion of the barrier that does not extend beyond the corresponding electrode is embedded between the corresponding solder connector and the corresponding electrode.

[0014] In some embodiments, the side surface of the barrier member further extends laterally beyond the outermost surface of the solder connection member.

[0015] In some embodiments, the distance between two adjacent solder connection members is greater than the distance between the corresponding barrier members.

[0016] In some embodiments, at the position between the two electrodes, there is a gap between the molding compound and the passive component.

[0017] In some embodiments, the barrier member is an adhesive layer, and the adhesive layer is disposed between the two electrodes and on the surface of the passive component.

[0018] In some embodiments, the adhesive layer is spaced apart from the two electrodes respectively.

[0019] In some embodiments, the barrier member is an organic structure, and the bonding force between the organic structure and the molding compound is greater than the bonding force between the molding compound and the passive component.

[0020] In some embodiments, the organic structure is spaced apart from the two electrodes respectively, and there is a gap at the position where the organic structure is spaced apart from the two electrodes.

[0021] In some embodiments, the molding compound further coats the solder connection member.

[0022] In some embodiments, the passive component is a capacitive element.

[0023] In some embodiments, there is no gap between the molding compound and the adhesive layer, between the adhesive layer and the passive component, and between the molding compound and the passive component.

[0024] In some embodiments, the number of the organic structures is multiple, and the multiple organic structures are arranged side by side between the two electrodes.

[0025] Some other embodiments of the present application provide a semiconductor package structure, including: a first substrate; a second substrate; a solder connection member connecting the first substrate to the second substrate; a passive component disposed between the first substrate and the second substrate and sandwiched between two adjacent solder connection members, wherein the passive component has two electrodes; a barrier member, at least a part of the barrier member extending between the two electrodes; and a molding compound coating the passive component, the barrier member and the solder connection member, wherein at the positions of the two electrodes, the barrier member extends beyond the lateral range of the solder connection member and at least fills part of the interval between the two adjacent solder connection members.

[0026] In some embodiments, the barrier members are respectively disposed at ends of corresponding ones of the two electrodes and extend beyond the corresponding electrodes, and the molding compound coats an upper surface of the barrier member remote from the passive component, a lower surface opposite to the upper surface, and side surfaces connecting the upper surface and the lower surface.

[0027] In some embodiments, the barrier member is disposed between the two electrodes and at a surface of the passive component, and wherein the barrier layer is an adhesive layer or an organic structure.

[0028] With the semiconductor package structure provided by the present application, the corresponding delamination and solder protrusion problems are solved in a manner that does not change the structural characteristics and component characteristics of the semiconductor package structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0030] Figures 1A to 1F 、 Figures 1F-1 to 1F-2 and Figures 1G-1 to 1G-2 show a semiconductor package structure in the prior art.

[0031] Figures 2A to 2D 、 Figures 3A to 3C and Figure 4A 、 Figure 4B-1 and Figure 4B-2 and Figure 4C show semiconductor package structures of some embodiments of the present application.

[0032] Figures 5 to 21 show a forming process of semiconductor package structures of some embodiments of the present application. DETAILED DESCRIPTION

[0033] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. In addition, when a numerical value or a numerical range is described with "substantially", "about", "substantially", "essentially", etc., unless otherwise specified, the term is intended to cover numerical values within ±10% of the described numerical value. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0034] Referring to Figures 2A to 2C , Figure 2AA semiconductor package structure 100 according to some embodiments of the present application is shown. Figure 2B is shown Figure 2A a top view of region B of Figure 2C is shown Figure 2A an enlarged view of region B of Figure 2A Referring to Figure 2A as can be seen, each of the two electrodes 104e extends along the side of the passive component 104 to the surface 104s of the upper and lower surfaces of the passive component 104; a barrier 106, at least a part of the barrier 106 extends between the two electrodes 104e; and a molding compound 103 that encapsulates the passive component 104 and the barrier 106. Further, the molding compound 103 encapsulates the upper surface 106t of the barrier 106 away from the passive component 104 and the side surface 106s connecting the upper surface 106t and the lower surface 106d opposite to the upper surface 106t. In Figures 2A to 2C the embodiment shown, the molding compound 103 further encapsulates the lower surface 106d of the barrier 106, so that the locking effect of the barrier 106 on the molding compound 103 is better.

[0035] As Figure 2A shown, the first substrate 101 is connected to the second substrate 102 through solder joints 105, and the passive component 104 is sandwiched between two adjacent solder joints 105. In some embodiments, the molding compound 103 further encapsulates the solder joints 105. As can be seen from ) the two electrodes 104e on the opposite ends of the passive component 104 are respectively embedded in the corresponding solder joints 105 and extend beyond the corresponding solder joints 105. Further, with further reference to Figure 2A the barrier 106 is respectively disposed at the end 104ed of the corresponding electrode of the two electrodes 104e and extends beyond the corresponding electrode 104e. In addition, the part of the barrier 106 that does not extend beyond the corresponding electrode 104e is embedded between the corresponding solder joint 105 and the corresponding electrode 104e. Further, the side surface 106s of the barrier 106 further extends laterally beyond the outermost surface 105s of the solder joint 105 to better block the solder flow of the solder joint 105. Further, the distance d2 between two adjacent solder joints 105 is greater than the distance d1 between the corresponding barriers 106.

[0036] Referring to Figures 2A to 2C fromFigure 2C As can be seen from the region L, the barrier 106 and the corresponding electrode 104e form a stepped structure, where the barrier 106 in the stepped structure extends beyond the corresponding electrode 104e, which can block the solder flow of the solder connection member 105 between the corresponding electrodes 104. In addition, in this case, the barrier 106 on the electrode 104e can be used as a stepped terminal to lock the molding compound 103, preventing the entire contact area between the molding compound 103 and the surface 104s of the passive component 104 from being lifted, and thus, no solder protrusion of the solder connection member 105 will occur. Specifically, through the semiconductor package structure 100 provided by the present application, locking of the molding compound 103 will occur between the electrode 104e and the surface 104s of the passive component 104, such that during thermal reflow, the delamination stress S causes a gap G to form between the molding compound 103 and the passive component 104 at a position between the two electrodes 104e, that is, there may be a gap G between the molding compound 103 and the passive component 104. Even if, in the vertical direction, the barrier 106 overlaps with the gap G, the region L below the barrier 106 cannot be separated by the delamination stress S, and thus, no solder protrusion will occur. Figure 2C shows a scan of the region B of the semiconductor package structure 100, from Figure 2D which it can be seen that no delamination has occurred between the molding compound 103 and the passive component 104, nor has any solder protrusion formed. In some embodiments, the electrode 104e is made of copper. In some embodiments, the barrier 106 can be made of any suitable metal, including but not limited to metals such as copper, gold, silver, etc. In some embodiments, the surface 104s of the passive component 104 is made of ceramic, and in a further embodiment, the passive component 104 is a capacitor component or an inductor component, etc. In the above embodiments, the first substrate 101 and the second substrate 102 can be any suitable substrate, such as a semiconductor substrate of silicon, or a printed circuit board, and in some embodiments, can also be an interposer, etc. In some embodiments, the solder connection member 105 is made of solder, etc.

[0037] Next, referring to Figure 2D , Figures 3A to 3C shows the semiconductor package structure 100’, ) shows a top view of the region B’ of the semiconductor package structure 100’, and Figure 3A shows an enlarged view of the region B’ of the semiconductor package structure 100’. In the embodiments of the present application, Figure 3B the semiconductor package structure 100’ shown in Figure 3C is similar to the semiconductor package structure 100 shown in Figure 3AIn the semiconductor package structure 100' shown, the barrier 106 is an adhesive layer, and this adhesive layer 106 is disposed between two electrodes 104e and on the surface 104s of the passive component 104. Further, from Figure 2A the top view of Figure 3A and the enlarged view of

[0038] it can be seen that the adhesive layer serving as the barrier 106 is spaced apart from the two electrodes 104e respectively, that is, there is a space between the side surface 106s of the barrier 106 and the end portion 104ed of the corresponding electrode 104e, and this space is filled with the molding compound 103. In the embodiment where the barrier 106 is an adhesive layer, an adhesive layer is added between the electrodes 104e and between the electrode 104e and the surface 104s of the passive component 104 such as ceramic, thereby enhancing the bonding force between the molding compound 103 and the surface 104s of the passive component 104 such as ceramic, so that the molding compound 103 in this region cannot be delaminated by the stress S during reflow, and thus, delamination will not occur, and solder protrusion will not occur even more. It can be seen that in this embodiment, there is no gap between the molding compound 103 and the adhesive layer serving as the barrier 106, between the adhesive layer serving as the barrier 106 and the passive component 104, and between the molding compound 103 and the passive component 104. In this embodiment, by the design of adding an adhesive layer (barrier 106) on the surface 104s of the passive component 104, and after being filled with the encapsulation material of the molding compound 103, the functional groups and hydrogen bonds of this adhesive layer will have the effect of increasing the bonding force (and also increasing the binding force) between the encapsulation material of the molding compound 103 and the passive component 104. In addition, in the extending direction of the solder connection 105, the thickness of the adhesive layer serving as the barrier layer 106 is in the range of 2 to 10 μm, and the adhesive layer serving as the barrier layer 106 may include a surfactant (such as a primer), and its components include but are not limited to epoxy-based silane coupling agents, amino-based silane coupling agents, and / or titanate coupling agents, etc. In a further embodiment, the melting point of the adhesive layer serving as the barrier 106 needs to be greater than the reflow temperature of the semiconductor package structure 100', or greater than the melting point of the solder connection 105. After that, referring to Figure 3B Figure 3C shows the semiconductor package structure 100'', Figures 4A to 4C and Figure 4A show the top view of region B'' of the semiconductor package structure 100'', and Figure 4B-1 shows the enlarged view of region B'' of the semiconductor package structure 100''. In the embodiment of the present application, Figure 4B-2 the semiconductor package structure 100'' shown is similar to Figure 4C the semiconductor package structure 100 shown, the difference being that in Figure 4AIn the semiconductor package structure 100 shown, the barrier 106 is an organic structure. In some embodiments, the bonding force between the organic structure serving as the barrier 106 and the molding compound 103 is greater than the bonding force between the molding compound 103 and the passive component 104. In the design of some embodiments, the coverage area of the organic structure serving as the barrier 106 is greater than 20% of the surface 104s of the passive component 104 such as ceramic. Further, referring to Figure 2A , the number of organic structures serving as the barrier 106 is plural, and the plural organic structures are arranged side by side between the two electrodes 104e. As can be seen from Figure 4A , the organic structures serving as the barrier 106 are respectively spaced apart from the two electrodes 104e, and further as can be seen from Figure 4B-2 , there is a gap G at the position where the organic structures serving as the barrier 106 are spaced apart from the two electrodes 104e. In the present embodiment, organic structures serving as the barrier 106 are added between the electrodes 104e and between the electrodes 104e and the surface 104s of the passive component 104 such as ceramic. With strong bonding force, the molding compound 103 in this region cannot be separated by the delamination stress S. Even if a gap G is generated around the organic structures serving as the barrier 106, that is, at the positions spaced apart from the corresponding electrodes of the two electrodes 104e, the solder of the solder connection 105 cannot form solder protrusion through the organic structures serving as the barrier 106. It can be seen that by arranging the organic structures between the electrodes 104e, the bonding force between the molding compound 103 and the organic structures is relatively strong. Even if there is a gap G (partial delamination), the solder of the solder connection 105 will be blocked by the organic structures and will not flow towards each other to cause bridging or form solder protrusion. In the present embodiment, by the design of adding the organic structure (barrier 106) on the surface 104s of the passive component 104 and filling it with the encapsulation material of the molding compound 103, the encapsulation material of the molding compound 103 and the organic structure itself have a high bonding force, which can avoid the delamination phenomenon. Further, the organic structures serving as the barrier 106 may include, but are not limited to, solder resist (SR), polypropylene (PP), etc.

[0039] Return to reference Figures 4A to 4C, some other embodiments of the present application further provide a semiconductor package structure 100 / 100’ / 100”, including: a first substrate 101; a second substrate 102; a solder connector 105 connecting the first substrate 101 to the second substrate 102; a passive component 104 disposed between the first substrate 101 and the second substrate 102 and sandwiched between two adjacent solder connectors 105, wherein the passive component 104 has two electrodes 104e; a barrier 106, at least a part of the barrier 106 extends between the two electrodes 104e; and a molding compound 103 covering the passive component 104, the barrier 106 and the solder connector 105. In some embodiments, at the positions of the two electrodes 104e, the barrier 106 extends beyond the lateral range of the solder connector 105 and at least fills part of the gap between two adjacent solder connectors 105. In some embodiments, with reference to Figure 4C , the barrier 106 is respectively disposed at the end portions 104ed of the corresponding electrodes among the two electrodes 104e and extends beyond the corresponding electrode 104e, and the molding compound 103 covers the upper surface 106t of the barrier 106 away from the passive component, the lower surface 106d opposite to the upper surface 106t, and the side surface 106s connecting the upper surface 106t and the lower surface 106d. In some embodiments, as Figures 2A to 4C and Figure 2A show, the barrier 106 is disposed between the two electrodes 104e and is located at the surface 104s of the passive component 104. Further, the barrier layer 106 is an adhesive layer or an organic structure.

[0040] For the above-provided semiconductor package structure 100 / 100’ / 100”, it can be applied between any two substrates, and multiple structures can be provided simultaneously to form a structure similar to that of Figure 3A , but without layering and solder protrusion, which will not be described in detail here.

[0041] Next, with reference to Figure 4A to introduce Figure 1C the formation process of the semiconductor package structure 100 shown.

[0042] With reference to Figures 5 to 10 , a hot plate 1001 is provided. The hot plate 1001 can be any suitable metal plate such as a steel plate, and a metal plate 1002 (serving as a heat spreader (CAP)), such as a copper plate, is provided on the hot plate 1001 as a tool. Further, a passive component 104 such as a capacitor element is placed on the metal plate 1002, and two electrodes 104e are provided at both ends thereof. And as Figure 2A shows, the passive component 104 is fixed in the groove of the metal plate 1002.

[0043] After that, referring to ), solder paste 107 is dispensed near the ends 104ed of the two exposed electrodes 104e of the passive component 104. A metal such as copper is placed on the solder paste 107 and extended beyond the ends 104ed of the corresponding electrodes 104e to form a barrier 106.

[0044] Refer to Figure 5 , the hot plate 1001 is removed, and Figure 5 the structure shown is flipped and placed on another metal plate 1003, and then placed on another hot plate 1004 and the metal plate 1002 is removed.

[0045] Next, as Figures 6 to 7 shown, solder paste 107 is dispensed through a process similar to Figure 8 and Figure 7 , and copper is placed on the solder paste 107 to form a barrier 106, thereby forming Figures 9 - 10 the structure shown.

[0046] Finally, the passive component 104 formed with the barrier 106 as shown Figure 6 is placed between the corresponding solder connectors 105 by a method commonly used in the art. After the first substrate 101 and the second substrate 102 are joined, a molding compound 103 is formed, and then reflowed to form Figure 7 the packaged structure 100 shown.

[0047] Refer to Figure 10 to introduce Figure 10 the formation process of the semiconductor packaged structure 100' shown, that is, the barrier layer 106 in the semiconductor packaged structure 100' is an adhesive layer.

[0048] Refer to Figure 2A , the passive component 104 is placed on a metal plate 100' such as a copper plate. Two electrodes 104e are provided at the ends of the passive component 104. A masking layer 1006 is provided on the passive component 104, and the masking layer 1006 exposes the portion between the two electrodes 104e for forming the adhesive layer as the barrier layer 106.

[0049] After that, refer to Figures 11 to 15 , an adhesive layer as the barrier layer 106 is formed between the two electrodes 104e by a spin coating process SC, and a corresponding adhesive layer 106' is also formed on the masking layer 1006, which will be removed after the adhesive layer as the barrier layer 106 is formed. In some embodiments, the masking layer 1006 can be a resist layer or any suitable masking layer.

[0050] Refer to Figure 3A, after forming the adhesive layer as the barrier layer 106, the masking layer 1006 and the adhesive layer 106' thereon are removed, the structure is flipped and placed on another metal plate 1007.

[0051] Next, referring to Figure 11 and Figure 12 , after removing the metal plate 1005, similar to Figure 13 , an adhesive layer as the barrier layer 106 is formed on the other side of the passive component 104 by spin-coating through the masking layer 1008. After that, the masking layer 1008 is removed, obtaining the structure shown in Figure 14 .

[0052] Finally, the passive component 104 formed with the barrier 106 shown in Figure 15 is placed between the corresponding solder joints 105 by a method commonly used in the art. After joining the first substrate 101 and the second substrate 102, a molding compound 103 is formed, and then through reflow, the packaged structure 100' shown in Figures 11 to 12 is formed.

[0053] Referring to Figure 15 to introduce the formation process of the semiconductor packaged structure 100" shown in Figure 15 , that is, the barrier layer 106 in the semiconductor packaged structure 100" is an organic structure.

[0054] Referring to Figure 3A , the passive component 104 is placed on a metal plate 1009 such as a copper plate, and two electrodes 104e are provided at the ends of the passive component 104. An organic material 106', such as a solder mask, is printed on the exposed surfaces of the passive component 104 and its corresponding electrodes 104e and the exposed surface of the metal plate 1009.

[0055] After that, as shown in Figures 16 to 21 , a masking layer 1010 is formed. In some embodiments, the masking layer 1010 can be a resist layer or any suitable masking layer. The masking layer 1010 exposes the organic material 106' (such as SR) that will form the barrier 106. Then, it is cured by UV light (ultraviolet light). In this embodiment, the UV light will cause a cross-linking reaction of the organic material 106', and the unexposed part will be decomposed and removed by a chemical agent later.

[0056] Next, as shown in Figure 4AAs shown, after curing the corresponding organic material, it is cleaned with a chemical agent to remove the unwanted organic material 106', thereby forming an organic structure serving as the barrier 106. In some embodiments, the chemical agent can be a wet etchant, such as a chlorine-containing etchant, a fluorine-containing etchant, or other commonly used etchants in the art, and the chemical agent does not remove the UV-cured portion of the organic material 106', that is, it is selective for this portion.

[0057] After that, referring to Figure 16 , the Figure 17 resulting structure is flipped and placed on another metal plate 1011. Referring to Figure 18 , the Figure 19 steps are repeated to form an organic structure serving as the barrier 106 on the other side of the passive component 104.

[0058] Finally, the passive component 104 formed with the barrier 106 as shown in Figure 18 is placed between the corresponding solder joints 105 by a commonly used method in the art. After joining the first substrate 101 and the second substrate 102, a molding compound 103 is formed, and then through reflow, the Figures 20 to 21 encapsulation structure 100” as shown is formed.

[0059] In summary, there are three designs in this application that can overcome the problems of delamination and solder protrusion existing in the prior art:

[0060] (1) The stepped terminal design as shown in Figures 16 to 18 (the barrier 106 and the electrode 104e form a step): By adding a design such as a metal layer as the barrier 106 at the end 104ed of the corresponding electrode 104e of the passive component 104, and after filling with the encapsulation material of the molding compound 103, there will be a locking effect between the encapsulation material of the molding compound 103 and the barrier 106 such as a metal layer, which can fix the molding compound 103 by the barrier 106 such as a metal layer, thereby avoiding delamination of the molding compound 103 and the surface 104s of the passive component 104 in this area, and further avoiding solder protrusion of the solder joint 105.

[0061] (2) The adhesive layer design serving as the barrier 106 as shown in Figure 21 : By adding a design of an adhesive layer (barrier 106) on the surface 104s of the passive component 104, and after filling with the encapsulation material of the molding compound 103, the functional groups and hydrogen bonds of the adhesive layer will have the effect of increasing the bonding force between the encapsulation material of the molding compound 103 and the passive component 104.

[0062] (3) As shown in Figure 4A Figure 2A Figure 3A Figure 4ADesign of the organic structure using the barrier 106: By adding the organic structure (barrier 106) on the surface 104s of the passive component 104, and after filling it with the encapsulation material of the molding compound 103, the encapsulation material of the molding compound 103 and the organic structure itself have a high bonding force, which can avoid the delamination phenomenon.

[0063] It can be seen that in this application, by physically or chemically modifying the surface 104s of the passive component 104, the problem of delamination caused by insufficient bonding force or stress is solved, and the bonding force between the encapsulation material of the molding compound 103 and the surface 104s (ceramic surface) of the passive component 104 is increased by 30%. Compared with the two existing technologies of changing the properties of the encapsulation material of the molding compound 103 and coarsening the surface roughness of the passive component 104 (both of these two technologies may affect the electrical performance and reliability characteristics of the product itself), this application improves the bonding force of the encapsulation material of the molding compound 103 to the passive component 104 itself without changing the electrical performance and reliability of the semiconductor package structure 100 / 100’ / 100”, indirectly improving the reliability properties of the product.

[0064] The features of several embodiments are outlined above so that those skilled in the art can better understand the aspects of the present utility model. Those skilled in the art should understand that they can easily use the present utility model as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present utility model, and various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of the present utility model.

Claims

1. A semiconductor package structure, characterized in that, Comprising: A first substrate; A second substrate; A passive component disposed between the first substrate and the second substrate, the passive component having two electrodes, wherein each of the two electrodes extends along a side portion of the passive component to surfaces of an upper surface and a lower surface of the passive component; A barrier member, at least a portion of the barrier member extending between the two electrodes; and A molding compound encapsulating the passive component and the barrier member, wherein the molding compound encapsulates an upper surface of the barrier member remote from the passive component and side surfaces connecting the upper surface and a lower surface opposite the upper surface.

2. The semiconductor package structure according to claim 1, wherein, The first substrate is connected to the second substrate by solder joints, and the passive component is sandwiched between two adjacent solder joints.

3. The semiconductor package structure according to claim 2, wherein The barrier member is respectively disposed at ends of corresponding ones of the two electrodes and extends beyond the corresponding electrode.

4. The semiconductor package structure according to claim 3, wherein The molding compound further encapsulates a lower surface of the barrier member.

5. The semiconductor package structure according to claim 3, wherein, The barrier member and the corresponding electrode form a stepped structure.

6. The semiconductor package structure according to claim 3, wherein A portion of the barrier member that does not extend beyond the corresponding electrode is embedded between the corresponding solder joint and the corresponding electrode.

7. The semiconductor package structure according to claim 3, wherein, Side surfaces of the barrier member further laterally extend beyond an outermost surface of the solder joint.

8. The semiconductor package structure according to claim 7, wherein At a position between the two electrodes, there is a gap between the molding compound and the passive component.

9. The semiconductor package structure according to claim 1, wherein The barrier member is an organic structure, wherein a bonding force between the organic structure and the molding compound is greater than a bonding force between the molding compound and the passive component.

10. The semiconductor package structure according to claim 9, wherein, The organic structure is spaced apart from each of the two electrodes respectively, and there is a gap at a position where the organic structure is spaced apart from the two electrodes.

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