Diamond ceramic semiconductor packaging tube shell and packaging structure of computing power chip

Abstract

The utility model relates to a packaging structure of a diamond ceramic semiconductor packaging tube shell and a computing power chip, the packaging tube shell comprises a substrate located at the bottom and a tube wall located at the periphery, the inner side of the tube shell substrate is provided with a multi-layer wiring substrate, the multi-layer wiring substrate comprises a multi-layer film structure of conductive film layers and insulating film layers, and the conductive film layers and the insulating film layers are alternately deposited. The top conductive film layer of the substrate also comprises a deposited first diamond film, and the first diamond film is provided with a bonding pad for welding a chip. The packaging structure of the computing power chip comprises a diamond ceramic packaging tube shell, a cover plate, the computing power chip and a second-type diamond film formed through deposition, the computing power chip is welded to a bonding pad of the first-type diamond film, and the computing power chip and the diamond ceramic packaging tube shell are connected into a whole through the second-type diamond film. The multi-layer wiring substrate with the thin film structure can effectively improve the high fidelity performance and the heat dissipation effect of the packaged chip, and enables the packaged chip to be more miniaturized.

Description

Technical Field

[0001] The utility model relates to a packaging structure of a semiconductor chip, in particular to a packaging structure of a computing power chip. Background Art

[0002] In the prior art, the packaging of a computing power chip is that the computing power chip is flip-chip welded on a substrate based on a PCB substrate, and then plastic-sealed resin (plastic-sealing glue) and ball planting at the bottom. The substrate is a multi-layer PCB board composed of an alternating layer of a layer of metal copper and a layer of resin material. The main disadvantages of the "plastic-sealing glue + PCB substrate" packaging structure of the computing power chip in the prior art are:

[0003] a. The thermal performance of the plastic-sealing material is poor: the thermal conductivity coefficient of the resin is 1-10 W / mK.

[0004] b. The heat dissipation performance of the multi-layer PCB substrate is poor: the thermal conductivity coefficient of the PCB board composed of the resin and the metal layer does not exceed 10 W / mK.

[0005] c. The computing power chip packaged by "plastic-sealing glue + PCT substrate" is not suitable for the military test requirements and automotive test requirements with high requirements for moisture sensitivity level (MSL), wide temperature range (-55~125 °C), and high and low temperature shock.

[0006] d. In order to better dissipate heat, its packaging size is large: based on a certain series of computing power chip packaging of X core 3C, the packaging size is 75×51.5×3.5 mm. Content of the Utility Model

[0007] The technical problem to be solved by the utility model is to provide a diamond ceramic semiconductor packaging shell with good heat dissipation performance and reduced packaging size and a packaging structure of a computing power chip.

[0008] The technical solution adopted by the utility model to solve its technical problems is: a diamond ceramic packaging shell, including a substrate located at the bottom and a tube wall located around. The substrate is provided with a plurality of through holes, and pads are arranged outside the through holes. A multi-layer wiring substrate is arranged inside the substrate. The multi-layer wiring substrate includes a multi-layer thin film structure formed by alternately laminating a deposited conductive film layer and an insulating film layer. On the top conductive film layer of the multi-layer wiring substrate, there is also a first type of diamond film formed by deposition, and pads for welding chips are arranged on the first type of diamond film.

[0009] Furthermore,

[0010] The thickness of the insulating film layer does not exceed 0.1 mm.

[0011] The thickness of the conductive film layer does not exceed 0.1 mm.

[0012] To solve its technical problems, the present utility model also provides a packaging structure for a computing power chip, which includes a cover plate, a computing power chip, and the aforementioned diamond ceramic packaging shell. The cover plate covers the diamond ceramic semiconductor packaging shell. In particular, it further includes a second type of diamond film formed by deposition. The computing power chip is welded to the pad of the first type of diamond film, and the second type of diamond film integrates the back of the computing power chip with the diamond ceramic packaging shell.

[0013] Furthermore,

[0014] There is nitrogen gas filled between the second type of diamond film and the cover plate.

[0015] The cover plate and the shell are sintered into one body.

[0016] The cover plate is made of diamond ceramic.

[0017] The present utility model uses a deposited thin film structure as the multi-layer wiring substrate, and the diamond-like carbon film used has both insulation and high heat dissipation effects. Compared with the prior art, the beneficial effects of the present utility model are: it is beneficial to realize the high-fidelity extraction of the interconnection signals of the semiconductor chip, especially the pins of the computing power chip, make the packaged chip smaller, and greatly improve the heat dissipation efficiency. Description of the Drawings

[0018] Figure 1 It is a schematic diagram of the packaging structure of the semiconductor chip in the preferred embodiment of the present utility model. Detailed Embodiments

[0019] Now, in combination with the drawings, detailed descriptions of the preferred embodiments of the present utility model will be given.

[0020] A diamond ceramic semiconductor packaging shell, as Figure 1 shown, includes a substrate 11 at the bottom and a tube wall around it. The substrate 11 is provided with a plurality of through holes 110, and pads 41 are provided outside the through holes. A multi-layer wiring substrate 3 is provided inside the shell substrate.

[0021] The multi-layer wiring substrate 3 is a multi-layer thin film structure formed by alternately laminating a deposited conductive film layer 35 and an insulating film layer 36. On the top conductive film layer of the multi-layer wiring substrate, there is also a first type of diamond film formed by deposition, and pads for welding chips are provided on the first type of diamond film. The thickness of the insulating film layer of the diamond ceramic semiconductor packaging shell does not exceed 0.1 mm, and the thickness of the conductive film layer does not exceed 0.1 mm.

[0022] See Figure 1, A computing power chip packaging structure, including a packaging shell 1 and a cover plate 2 made of diamond ceramics formed by mixing and sintering diamond polycrystalline powder, silicon powder, silicon dioxide and other materials. The thermal conductivity of the diamond ceramic shell and cover plate is not less than 550 W / mK. Copper is deposited in the through holes 110 of the substrate 11 of the shell, and a copper pad 41 is deposited on the outside of the shell substrate, which is also the external pin of the computing power chip packaging component. On the inner side 12 of the shell substrate, a multi-layer wiring substrate 3 with an alternating stack of a conductive film layer 35 and an insulating film layer 36 is formed through a deposition process. At the same time, assisted by photolithography and etching, the metal films of each layer are electrically connected to achieve multi-layer wiring interconnection. The bottom layer 31 of the multi-layer wiring substrate 3, that is, the contact layer with the shell substrate, is a conductive film layer; the top layer 32 of the multi-layer wiring substrate 3 is a diamond-like carbon (DLC) film (the first type of diamond film) realized by the lift off process, and pads for connecting the computing power chip are formed thereon.

[0023] After the computing power chip 4 is reversely welded to the pads on the top layer of the multi-layer wiring substrate of the diamond ceramic semiconductor packaging shell 1, that is, on the first type of diamond film, a high thermal conductivity DLC film is deposited on the entire top layer of the multi-layer wiring substrate and on the computing power chip 4 to form a packaging film layer 5 (the second type of diamond film), which is connected to the shell 1. Through the hermetic packaging process, nitrogen 6 (or other inert gases or vacuum pumping) is filled between the DLC packaging film layer (the second type of diamond film) and the cover plate, and the cover plate 2 seals the shell 1 into one body.

[0024] In this embodiment, the heat generated by the computing power chip 4 is conducted to the diamond ceramic shell through the high thermal conductivity first type of diamond film and the second type of diamond film. The heat dissipation is achieved by using the thermal conductivity of diamond ceramics (the thermal conductivity is not less than 550 W / mK), and its heat dissipation performance is far better than the thermal conductivity of 1 - 10 W / mK of plastic packaging materials and the thermal conductivity of 100 W / mK of silicon. The good heat dissipation performance enables the heat inside the chip to be quickly conducted out.

[0025] At the same time, based on the hermetic packaging of the ceramic shell filled with nitrogen, it has higher reliability, fully meets the requirements of automotive and military specifications, and other environmental reliability parameters also rank first among various packaging materials.

[0026] Based on the good heat dissipation performance and the thickness of each layer of the substrate formed by the deposition process not exceeding 0.1 mm, the diamond ceramic packaging in this embodiment can reduce the external dimensions to 60*40*3.5 mm or smaller.

[0027] Moreover, since the thickness of each conductive layer and insulating layer of the substrate is not greater than 0.1 mm, compared with the prior art, for the substrate of the same thickness, this embodiment can include more layers of conductive film layers, which is more conducive to high-fidelity extraction of the interconnection signals of the computing power chip pins.

[0028] In the prior art, alumina or aluminum nitride ceramics are used for encapsulation, and the deposition and multi-layer wiring technologies in the present utility model are not adopted, resulting in limited number of multi-layer wirings (at most 2 - 3 layers) and high impedance (the parasitic RLC is too large and the frequency cannot exceed 100 MHz). At the same time, the thermal conductivity of alumina is 20 - 30 W / mK, and the thermal conductivity of aluminum nitride is 170 W / mK, which is far from the thermal conductivity of diamond-like carbon film of 500 - 600 W / mK.

[0029] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present utility model and are not intended to limit it. For those skilled in the art, the technical solutions recorded in the above embodiments can be modified, or some of the technical features can be equivalently replaced; and these modifications and replacements should all fall within the protection scope of the appended claims of the present utility model.

Claims

1. A diamond ceramic semiconductor package housing, comprising a substrate at the bottom and a tube wall around it. The substrate is provided with a plurality of through holes, and pads are arranged outside the through holes. A multi-layer wiring substrate is arranged inside the substrate. It is characterized in that: The multi-layer wiring substrate includes a multi-layer thin film structure formed by alternately laminating a conductive film layer and an insulating film layer formed by deposition. On the top conductive film layer of the multi-layer wiring substrate, there is also a first type of diamond film formed by deposition, and pads for welding chips are arranged on the first type of diamond film.

2. The diamond ceramic semiconductor package housing according to claim 1, characterized in that: The thickness of the insulating film layer does not exceed 0.1 mm.

3. The diamond ceramic semiconductor package housing according to claim 1, characterized in that: The thickness of the conductive film layer does not exceed 0.1 mm.

4. A packaging structure for a computing power chip, comprising a cover plate, a computing power chip, and the diamond ceramic semiconductor package housing according to any one of claims 1 to 3. The cover plate covers the diamond ceramic semiconductor package housing. It is characterized in that: It further includes a second type of diamond film formed by deposition. The computing power chip is welded to the pads of the first type of diamond film, and the second type of diamond film connects the back of the computing power chip and the diamond ceramic semiconductor package housing into one body.

5. The packaging structure for a computing power chip according to claim 4, characterized in that: Nitrogen, inert gas or vacuum is filled between the second type of diamond film and the cover plate.

6. The packaging structure for a computing power chip according to claim 4, characterized in that: The cover plate and the housing are sintered into one body.

7. The packaging structure for a computing power chip according to claim 4, characterized in that: The cover plate is made of diamond ceramic.

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