Si-based SiC-Si epitaxial wafer structure
Through the Si-based SiC-Si heteroepitaxial sheet structure, the high cost and high interface defects of SiC-based SiC homoepitaxial sheet are solved, and low-cost and high-performance SiC device production is realized, suitable for high electron mobility transistors.
Patent Information
- Application Number
- CN202422347366.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-08-01
- Estimated Expiration
- 2034-09-26
AI Technical Summary
The existing SiC-based SiC homoepitaxial sheets have problems with high SiC substrate cost and high SiC/SiO2 interface defect density, which limits the performance and cost of the device.
The Si-based SiC-Si heteroepitaxial sheet structure is adopted, and SiC and Si epitaxial layers are deposited on it using a heavily doped Si substrate. The device is made in the Si epitaxial layer. The SiC epitaxial layer is only used as a pressure-resistant layer, and the epitaxial sheet is a three-layer sandwich structure to offset the lattice mismatch stress.
It reduces the cost and difficulty of device manufacturing, improves carrier mobility, reduces SiC/SiO2 interface defects, and improves the reliability and performance of the device.
Smart Images
Figure CN223182566U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductors, and particularly relates to a Si-based SiC-Si epitaxial wafer structure. Background Art
[0002] Currently, the epitaxial wafers commonly used in wide-bandgap SiC (silicon carbide) power devices are SiC-based SiC homoepitaxial wafers, that is, SiC epitaxial layers are directly epitaxially grown on SiC substrate wafers. Since the epitaxial layer and the substrate material are the same, they have excellent lattice matching, which helps to reduce interface defects and improve the performance of the device.
[0003] Generally, referring to Figure 1 and Figure 2 , existing SiC devices include a SiC substrate 1, a SiC epitaxy 2, and a SiO2 gate dielectric 3 (the SiC substrate is 300 - 500 um thick, the SiC epitaxy is 6 um - 20 um thick, and the SiO2 gate dielectric is 0.08 - 0.12 um thick). The technical process is as follows: The first step: Prepare the SiC substrate and clean it thoroughly. The price of the SiC substrate is more than 10 times that of the heavily doped Si substrate, which is the first pain point in current SiC wafer manufacturing. The second step: Deposit SiC epitaxy on the SiC substrate by chemical vapor deposition (CVD) process. The third step: Make a SiO2 gate dielectric on the epitaxial wafer. This step is to oxidize the surface layer of the SiC epitaxy to make the SiO2 layer. Due to the presence of carbon during oxidation, there are many interface defects between SiO2 and SiC, and the carrier mobility is low. This is the second pain point in current SiC wafer manufacturing.
[0004] As described above, SiC-based SiC homoepitaxial wafers have some significant disadvantages: high cost of SiC substrates and high density of SiC / SiO2 (silicon dioxide) interface defects. High cost of SiC substrates: The preparation process of SiC materials is relatively complex, and the raw material cost is relatively high, which directly leads to the high price of SiC substrates. When preparing SiC-based SiC homoepitaxial wafers, high-quality SiC substrates are required as the substrate, so the cost of the entire epitaxial wafer will also increase accordingly. The high cost limits the application of SiC-based SiC homoepitaxial wafers in a wider range of fields. High density of SiC / SiO2 interface defects: During the preparation process of SiC-based SiC homoepitaxial wafers, in order to form an effective insulating layer or perform other process treatments, SiO2 layers are often deposited or thermally oxidized and grown on the SiC epitaxial layer. However, due to the presence of C atoms between SiC and SiO2, high-density defects are easily formed at the SiC / SiO2 interface. These defects not only reduce the reliability of the device but may also affect the performance of the device. Therefore, there is an urgent need for an epitaxial wafer structure that overcomes the above defects. Summary of the Utility Model
[0005] A brief overview of the embodiments of the present utility model is given below to provide a basic understanding of certain aspects of the present utility model. It should be understood that the following overview is not an exhaustive overview of the present utility model. It is not intended to identify the key or important parts of the present utility model, nor is it intended to limit the scope of the present utility model. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description to be discussed later.
[0006] The idea of the present utility model is to provide a novel Si-based SiC-Si heteroepitaxial wafer for fabricating mainstream wide-bandgap SiC devices, such as SiC MPS (SBD), MOSFET, and IGBT. The disadvantages of SiC-based SiC epitaxial wafers are overcome through the following solutions: Firstly, the use of an Si-based substrate reduces the manufacturing cost. Secondly, since the Si epitaxial layer is the manufacturing layer for low-voltage power devices, the problems of high interface defect density and low carrier mobility at the SiC / SiO2 interface are completely overcome, reducing the difficulty and cost of device manufacturing processes and being fully compatible with the current Si-based power device processes. In this composite epitaxial wafer, the SiC layer only serves as a voltage-resistant drift layer (drift resistance Rdrift), and there is no need to fabricate active devices in the SiC epitaxial layer.
[0007] Specifically, the solution adopted by the present utility model is: an Si-based SiC-Si epitaxial wafer structure, including a substrate and an epitaxial layer sequentially deposited on the substrate. Among them, the substrate is a heavily doped Si (silicon) substrate; the epitaxial layer includes an SiC epitaxial layer and an Si epitaxial layer. The SiC epitaxial layer is located above the heavily doped Si substrate, and the Si epitaxial layer is located above the SiC epitaxial layer.
[0008] Preferably, the thickness of the heavily doped Si substrate is 650 - 750 μm.
[0009] Preferably, the thickness of the SiC epitaxial layer is 6 - 20 μm.
[0010] Preferably, the thickness of the Si epitaxial layer is 3 - 5 μm.
[0011] A SiO2 gate dielectric layer is further provided above the epitaxial layer. Preferably, the thickness of the SiO2 gate dielectric layer is 0.08 - 0.12 μm.
[0012] In the prior art, devices are fabricated within the SiC epitaxial layer, while in the present utility model, devices are fabricated within the Si epitaxial layer, and the SiC epitaxial layer is only used to increase the breakdown voltage of the devices. This solution significantly reduces the manufacturing cost and difficulty of SiC devices. For 22 kV high-voltage devices, only a SiC epitaxial layer with a thickness of approximately 20 μm (100 V / μm) is required. For low-voltage power devices, the fabrication on the Si epitaxial layer is exactly the same as the current Si-based power device process, without the need to improve other processes. In addition, the Si-based SiC-Si epitaxial wafer structure of this application is a three-layer sandwich structure of Si-SiC-Si, which is conducive to the mutual cancellation of lattice mismatch stress and improves the warpage of the epitaxial wafer. The heterojunction between SiC and Si is conducive to the control of the necessary carrier density. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The present utility model can be better understood by referring to the descriptions given below in conjunction with the accompanying drawings, in which the same or similar reference numerals are used throughout all the drawings to denote the same or similar components. The accompanying drawings, together with the following detailed description, are included in this specification and form a part of this specification, and are used to further illustrate the preferred embodiments of the present utility model and to explain the principles and advantages of the present utility model. In the drawings:
[0014] Figure 1 is a schematic diagram of the epitaxial layer structure in the prior art;
[0015] Figure 2 is for the application Figure 1 of the transistor structure schematic diagram of the epitaxial layer structure;
[0016] Figure 3 is a schematic diagram of the epitaxial layer structure of an embodiment of the present utility model;
[0017] Figure 4 is for the application Figure 3 of the transistor structure schematic diagram of the epitaxial layer structure. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0018] Embodiments of the present utility model will be described below with reference to the accompanying drawings. Elements and features described in one drawing or one embodiment of the present utility model can be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that, for the sake of clarity, the representation and description of components and processes that are irrelevant to the present utility model and are known to those of ordinary skill in the art are omitted in the drawings and the description.
[0019] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present utility model.
[0020] See Figure 3 , an embodiment of the present utility model provides a Si-based SiC-Si epitaxial wafer structure, which includes a heavily doped Si substrate 10 and a SiC epitaxial layer 21, a Si epitaxial layer 22, and a SiO2 gate dielectric layer 30 deposited thereon in sequence. The SiC epitaxial layer 21 and the Si epitaxial layer 22 form an epitaxial layer. The SiC epitaxial layer 21 is located above the heavily doped Si substrate 10, the Si epitaxial layer 22 is located above the SiC epitaxial layer 21, and the SiO2 gate dielectric layer 30 is located above the Si epitaxial layer 22.
[0021] In this embodiment, the thickness of the heavily doped Si substrate 10 is 650 - 750 μm, the thickness of the SiC epitaxial layer 21 is 6 - 20 μm, the thickness of the Si epitaxial layer 22 is 3 - 4 μm, and the thickness of the SiO2 gate dielectric layer 30 is 0.08 - 0.12 μm.
[0022] The specific process implementation steps of this Si-based SiC-Si epitaxial wafer structure are as follows:
[0023] Step 1: Preparation of the heavily doped Si substrate 10;
[0024] Step 2: Growing the SiC epitaxial layer 21 on the surface of the heavily doped Si substrate 10, which specifically includes the following processes: cleaning and etching of the heavily doped Si substrate 10, Si epitaxial transition layer, Si carbonization, SiC epitaxial transition layer, and finally forming the SiC epitaxial layer 21; the doping and thickness of the SiC epitaxial layer 21 are determined by the breakdown voltage level of the power device, and the epitaxial transition layer relieves the lattice mismatch stress and reduces the defect density;
[0025] Step 3: In-situ growing the Si epitaxial layer 22 on the surface of the SiC epitaxial layer 21, which specifically includes a Si epitaxial transition layer and Si epitaxy;
[0026] Step 4: Depositing the SiO2 gate dielectric layer 30 on the Si epitaxy, and the Si-based SiC-Si epitaxial wafer structure can be realized.
[0027] The present utility model has the following advantages by adopting the above technologies:
[0028] 1. In the prior art, devices are fabricated within SiC materials, while in this utility model patent, devices are fabricated within Si materials, and the SiC epitaxy is only used to increase the breakdown voltage of the devices.
[0029] 2. The manufacturing cost and difficulty of SiC devices are significantly reduced. For 22 kV high-voltage devices, only a SiC epitaxial layer with a thickness of approximately 20 μm (100 V / μm) is required. The fabrication of low-voltage power devices on the Si epitaxial layer 22 is exactly the same as the current Si-based power device process.
[0030] 3. This epitaxial wafer with a Si-SiC-Si three-layer sandwich structure is conducive to the mutual cancellation of lattice mismatch stress and improves the warpage of the epitaxial wafer. The heterojunction between SiC and Si is conducive to the control of the necessary carrier density.
[0031] The epitaxial wafer structure of this utility model can be widely applied to various high electron mobility transistors. Refer to Figure 4 , this high electron mobility transistor also includes a source electrode (S electrode), a drain electrode (D electrode), and a gate electrode (G electrode). The above Si-based SiC-Si epitaxial wafer structure is used to form key parts such as the channel layer and the source / drain regions.
[0032] Although the present utility model has been disclosed above through the description of specific embodiments of the present utility model, it should be understood that all the above embodiments and examples are exemplary and not restrictive. Those skilled in the art can design various modifications, improvements, or equivalents to the present utility model within the spirit and scope of the appended claims. These modifications, improvements, or equivalents should also be considered to be included within the protection scope of the present utility model.
Claims
1. A Si-based SiC-Si epitaxial wafer structure, characterized in that: It includes a substrate and an epitaxial layer sequentially deposited on the substrate. The substrate is a heavily doped Si substrate; the epitaxial layer includes a SiC epitaxial layer and a Si epitaxial layer. The SiC epitaxial layer is located above the heavily doped Si substrate, and the Si epitaxial layer is located above the SiC epitaxial layer.
2. The Si-based SiC-Si epitaxial wafer structure according to claim 1, characterized in that: The thickness of the heavily doped Si substrate is 650 - 750 μm.
3. The Si-based SiC-Si epitaxial wafer structure according to claim 1, wherein: The thickness of the SiC epitaxial layer is 6 - 20 μm.
4. The Si-based SiC-Si epitaxial wafer structure according to claim 1, characterized in that: The thickness of the Si epitaxial layer is 3 - 5 μm.
5. The Si-based SiC-Si epitaxial wafer structure according to claim 1, wherein: A SiO2 gate dielectric layer is further provided above the epitaxial layer, and the thickness of the SiO2 gate dielectric layer is 0.08 - 0.12 μm.