Display device

Abstract

A display device is provided. The display device includes: a circuit layer; and a light emitting element disposed on the circuit layer. The circuit layer includes: a semiconductor pattern; an insulating layer in which a contact hole is defined to expose a portion of the semiconductor pattern; a connection electrode disposed on the insulating layer and partially disposed in the contact hole; and an auxiliary electrode at least partially disposed in the contact hole and in contact with the connection electrode and the semiconductor pattern. In plan view, the connection electrode does not overlap a portion of the contact hole.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0099171, filed on July 28, 2023, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a display device and a method of manufacturing a display device, and more particularly, to a display device having high-resolution characteristics and a method of manufacturing a display device. Background Art

[0003] A display device includes a plurality of pixels and a driving circuit (e.g., a scan driving circuit and a data driving circuit) for controlling the plurality of pixels. Each of the plurality of pixels includes a light-emitting element and a pixel driving circuit for controlling the light-emitting element. The pixel driving circuit may include a plurality of transistors connected organically.

[0004] As the resolution of the display device gradually increases, the number of signal lines and connection electrodes connecting the light-emitting elements and transistors to be arranged per unit area increases, and the integration degree of the driving circuit included in the pixel increases. Summary of the Invention

[0005] Embodiments of the present disclosure provide a high-resolution display device for preventing connection defects between electrodes even when providing a small contact hole.

[0006] According to an embodiment, a display device includes: a circuit layer; and a light-emitting element disposed on the circuit layer. The circuit layer includes: a semiconductor pattern; an insulating layer in which a contact hole is defined to expose a part of the semiconductor pattern; a connection electrode disposed on the insulating layer and partially disposed in the contact hole; and an auxiliary electrode at least partially disposed in the contact hole and in contact with the connection electrode and the semiconductor pattern. In a plan view, the connection electrode does not overlap a part of the contact hole.

[0007] The auxiliary electrode may include: a first auxiliary portion in contact with an inner surface of the insulating layer defining the contact hole and covering the entire inner surface of the insulating layer; a second auxiliary portion in contact with the above-mentioned part of the semiconductor pattern exposed from the insulating layer and covering the entire above-mentioned part of the semiconductor pattern; and a third auxiliary portion in contact with a part of an upper surface of the insulating layer.

[0008] The connection electrode may include: a first connection portion in contact with the third auxiliary portion; and a second connection portion extending downward from the first connection portion and in contact with the first auxiliary portion.

[0009] The outer surface of the auxiliary electrode and the outer surface of the connection electrode may be aligned with each other. The outer surface of the auxiliary electrode may be included in the third auxiliary portion, and the outer surface of the connection electrode may be included in the first connection portion.

[0010] The connection electrode may include: a first - 1 connection electrode layer disposed on the auxiliary electrode and including aluminum; and a second - 1 connection electrode layer disposed on the first - 1 connection electrode layer and including titanium.

[0011] The display device may further include a dummy electrode disposed in the contact hole on the second auxiliary portion. The dummy electrode may include: a first - 1 dummy electrode layer spaced apart from the first - 1 connection electrode layer and including the same material as the first - 1 connection electrode layer; and a second - 1 dummy electrode layer disposed on the first - 1 dummy electrode layer, spaced apart from the second - 1 connection electrode layer and including the same material as the second - 1 connection electrode layer.

[0012] The entirety of the auxiliary electrode may be disposed in the contact hole and may cover the entire inner surface of the insulating layer defining the contact hole, and the semiconductor pattern may include a portion exposed from the auxiliary electrode.

[0013] The connection electrode may include: a lower connection electrode layer in contact with the upper surface of the insulating layer and including titanium; a first - 2 connection electrode layer disposed on the lower connection electrode layer and including aluminum; and a second - 2 connection electrode layer disposed on the first - 2 connection electrode layer and including titanium.

[0014] The display device may further include a dummy electrode disposed in the contact hole on the upper surface of the semiconductor pattern. The edge of the dummy electrode may be in contact with the auxiliary electrode.

[0015] The dummy electrode may include: a lower dummy electrode layer in contact with the upper surface of the semiconductor pattern, including the same material as the lower connection electrode layer and spaced apart from the lower connection electrode layer; a first - 2 dummy electrode layer disposed on the lower dummy electrode layer, spaced apart from the first - 2 connection electrode layer and including the same material as the first - 2 connection electrode layer; and a second - 2 dummy electrode layer disposed on the first - 2 dummy electrode layer, spaced apart from the second - 2 connection electrode layer and including the same material as the second - 2 connection electrode layer.

[0016] The auxiliary electrode may include tungsten.

[0017] The inner surface of the insulating layer defining the contact hole may have a slope of 80 degrees to 90 degrees with respect to the upper surface of the semiconductor pattern, and in a cross - sectional view, the contact hole may have a width less than or equal to 2.0 micrometers.

[0018] According to an embodiment, a display device includes: a circuit layer; and a light-emitting element disposed on the circuit layer. The circuit layer includes: a semiconductor pattern; an insulating layer in which a contact hole is defined to expose a part of the semiconductor pattern; a connection electrode disposed on the insulating layer and partially disposed in the contact hole; a dummy electrode disposed on the semiconductor pattern, in the contact hole, and spaced apart from the connection electrode; and an auxiliary electrode at least partially disposed in the contact hole and in contact with the connection electrode and the dummy electrode.

[0019] According to an embodiment, a method of manufacturing a display device includes: providing a semiconductor pattern and an insulating layer, defining a contact hole in the insulating layer to expose a part of the semiconductor pattern; forming a preliminary auxiliary electrode on the insulating layer; forming a preliminary connection electrode on the insulating layer; etching the preliminary connection electrode to form a connection electrode partially disposed in the contact hole; and etching the preliminary auxiliary electrode to form an auxiliary electrode at least partially disposed in the contact hole. The auxiliary electrode is in contact with the connection electrode and the semiconductor pattern, and in a plan view, the connection electrode does not overlap with a part of the contact hole.

[0020] The method may further include: forming a photoresist pattern overlapping the contact hole on the preliminary connection electrode before the etching of the preliminary connection electrode and after the formation of the preliminary connection electrode. The etching of the preliminary auxiliary electrode may be performed simultaneously with the etching of the preliminary connection electrode.

[0021] The formation of the preliminary connection electrode may include: forming a first-1 conductive layer including aluminum on the preliminary auxiliary electrode; and forming a second-1 conductive layer including titanium on the first-1 conductive layer.

[0022] The etching of the preliminary auxiliary electrode may be performed before the formation of the preliminary connection electrode and after the formation of the preliminary auxiliary electrode, and the etching of the preliminary auxiliary electrode may be performed by a blanket anisotropic etching process.

[0023] The formation of the preliminary connection electrode may include: forming a lower conductive layer including titanium on the insulating layer; forming a first-2 conductive layer including aluminum on the lower conductive layer; and forming a second-2 conductive layer including titanium on the first-2 conductive layer.

[0024] A dummy electrode including the same material as that of the connection electrode, disposed in the contact hole, and spaced apart from the connection electrode may be additionally formed during the formation of the preliminary connection electrode.

[0025] The formation of the preliminary auxiliary electrode may be performed by a chemical vapor deposition process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0027] Figure 1A is a perspective view showing a display device according to an embodiment of the present disclosure.

[0028] Figure 1B is an exploded perspective view showing a display device according to an embodiment of the present disclosure.

[0029] Figure 1C and Figure 1D is a schematic cross-sectional view showing a display module according to an embodiment of the present disclosure.

[0030] Figure 2A is a perspective view showing a display device according to an embodiment of the present disclosure.

[0031] Figure 2B is an exploded perspective view showing a display device according to an embodiment of the present disclosure.

[0032] Figure 3 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0033] Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0034] Figure 5 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0035] Figure 6 is an enlarged cross-sectional view of a part of a display panel according to an embodiment of the present disclosure.

[0036] Figure 7 is a cross-sectional view of a partial configuration of a display device according to an embodiment of the present disclosure.

[0037] Figure 8 is a cross-sectional view of a partial configuration of a display device according to an embodiment of the present disclosure.

[0038] Figures 9A to 9F is a cross-sectional view showing some of the steps of a method for manufacturing a display device according to an embodiment of the present disclosure.

[0039] Figures 10A to 10F is a cross-sectional view showing some of the steps of a method for manufacturing a display device according to an embodiment of the present disclosure. Detailed Description

[0040] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on" another component, "connected to" or "coupled to" another component, this means that the component can be directly on the other component, directly connected to or coupled to the other component, or a third component can be present between the component and the other component.

[0041] Like reference numerals refer to like components. Additionally, in the drawings, the thickness, ratios, and sizes of components are exaggerated for effective description. The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, "a," "the," and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, "element" has the same meaning as "at least one element" unless the context clearly indicates otherwise. "At least one" should not be construed as limited to "one." "Or" means "and / or." As used herein, the term "and / or" includes all of the combinations of one or more of the related components.

[0042] Terms such as "first" and "second" may be used to describe various components, but the components should not be limited by these terms. These terms may be used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of the present disclosure, and similarly, a second component may also be referred to as a first component. Singular forms of terms may include plural forms unless otherwise stated.

[0043] Additionally, terms such as "below," "beneath," "above," and "on" are used to describe the relationships of components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0044] It should be understood that when used herein, terms such as "comprising," "including," and "having" specify the presence of the stated features, quantities, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Such terms as defined in a commonly used dictionary should be interpreted as having a meaning equivalent to the contextual meaning in the relevant technical field and should not be interpreted as having an idealized or overly formal meaning unless expressly so defined in this application.

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0047] Figure 1A is a perspective view showing a display device according to an embodiment of the present disclosure. Figure 1B is an exploded perspective view showing a display device according to an embodiment of the present disclosure. Figure 1C and Figure 1Dis a schematic cross-sectional view showing a display module according to an embodiment of the present disclosure.

[0048] The display device DD may be a device that is activated depending on an electrical signal. For example, the display device DD may be a television, a monitor, a billboard, a gaming machine, a personal computer, a laptop computer, a mobile phone, a tablet computer, an in-vehicle navigation unit, or a wearable device. However, the embodiments are not limited thereto. In Figure 1A and Figure 1B , a head-mounted display (“HMD”) is shown as an example of the display device DD. A head-mounted display may be an electronic device that is worn on a user's head and provides a screen on which an image or video is displayed to the user. The head-mounted display may include a see-through type HMD that provides augmented reality (“AR”) to the user based on an actual external object and a see-closed type HMD that provides virtual reality (“VR”) to the user using a screen independent of the external object.

[0049] Referring to Figure 1A and Figure 1B , the display device DD may include a display module DM and a lens unit LS opposite to the display module DM. In addition, the display device DD may include a main frame MFR, a cover frame CFR, and a fixing part FP.

[0050] The main frame MFR may be a part that is worn on a user's face. The main frame MFR may have a shape corresponding to the shape of the user's head (face). In an embodiment, for example, the length of the fixing part FP may be adjusted depending on the circumference of the user's head. The fixing part FP may be a structure that facilitates the installation of the main frame MFR and may include a strap or a hoop, etc. However, the embodiments are not limited thereto, and the fixing part FP may include various forms such as a helmet or temple arms that are coupled to the main frame MFR.

[0051] The main frame MFR may be coupled to the cover frame CFR and may provide a receiving space in which the lens unit LS and the display module DM are installed.

[0052] The lens unit LS may be disposed between the display module DM and the user. The lens unit LS may transmit light emitted from the display module DM and may provide the light to the user. In an embodiment, for example, the lens unit LS may include various types of lenses such as a multi-channel lens, a convex lens, a concave lens, a spherical lens, an aspherical lens, a single lens, a compound lens, a normal lens, a narrow-angle lens, a wide-angle lens, a fixed-focus lens, and a zoom lens.

[0053] The lens unit LS may include a first lens LS1 and a second lens LS2. The first lens LS1 and the second lens LS2 may be arranged to correspond to the positions of the user's left and right eyes. The first lens LS1 and the second lens LS2 may be accommodated in the main frame MFR.

[0054] The display module DM may be provided in a state fixed to the main frame MFR. Alternatively, the display module DM may be provided in a state detachable from the main frame MFR. The display module DM may provide an image to the user, and the image may include a still image and a moving image. The display module DM will be described in more detail below.

[0055] The cover frame CFR may be provided on one surface of the display module DM and may protect the display module DM. The cover frame CFR and the lens unit LS may be spaced apart from each other, with the display module DM between the cover frame CFR and the lens unit LS.

[0056] Although a first direction DR1, a second direction DR2, and a third direction DR3 are shown in Figure 1A and the subsequent drawings, the directions indicated by the first to third directions DR1, DR2, and DR3 described in this specification may be relative concepts and may be changed to other directions. In addition, the directions indicated by the first to third directions DR1, DR2, and DR3 may be described as the first to third directions and may be assigned the same reference numerals. In this specification, the first direction DR1 and the second direction DR2 may be orthogonal to each other, and the third direction DR3 may be the normal direction of the plane defined by the first direction DR1 and the second direction DR2.

[0057] The thickness direction of the display device DD may be a direction parallel to the third direction DR3, which is the normal direction of the plane defined by the first direction DR1 and the second direction DR2. In this specification, the front surface (or upper surface) and the rear surface (or lower surface) of the components constituting the display device DD may be defined based on the third direction DR3. In this specification, the term "plane" refers to a plane parallel to the plane defined by the first direction DR1 and the second direction DR2, and the "plan view" is a view in the thickness direction (i.e., the third direction DR3) of the display device DD. In this specification, the term "section" refers to a section parallel to the third direction DR3, and the "section view" is a view of an object cut by a plane parallel to the thickness direction (i.e., the third direction DR3).

[0058] Reference Figure 1C and Figure 1D , the display modules DM and DM-1 according to embodiments of the present disclosure may include a display panel DP, a window member WM, and an optical member OP.

[0059] The display panel DP may be a component that basically generates an image. The image generated by the display panel DP can be visually recognized by a user from the outside.

[0060] The display panel DP may be an emissive display panel and is not particularly limited. In an embodiment, for example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The organic light-emitting display panel may be a display panel in which the emission layer includes an organic light-emitting material. The inorganic light-emitting display panel may be a display panel in which the emission layer includes quantum dots, quantum rods, or micro LEDs. Hereinafter, an example in which the display panel DP is an organic light-emitting display panel will be described.

[0061] The window member WM may be disposed on the display panel DP. The window member WM may include an optically transparent insulating material. In an embodiment, for example, the window member WM may include glass or plastic. The window member WM may have a multi-layer structure or a single-layer structure. In an embodiment, for example, the window member WM may include a plurality of plastic films joined by an adhesive, or may include a glass substrate and a plastic film joined by an adhesive.

[0062] The optical member OP may be disposed on the display panel DP. The optical member OP may be a polarizing member, a color filter, or a wavelength filter. The optical member OP can improve the display characteristics of the display panel DP by controlling the light incident on the optical member OP.

[0063] As Figure 1C shown, in the display module DM of one embodiment, the optical member OP may be disposed on the window member WM. At the same time, as Figure 1D shown, in the display module DM-1 of another embodiment, the optical member OP may be disposed between the window member WM and the display panel DP. Alternatively, different from the embodiments shown in Figure 1C and Figure 1D the optical member OP may be omitted.

[0064] Figure 2A is a perspective view showing a display device according to an embodiment of the present disclosure. Figure 2B is an exploded perspective view showing a display device according to an embodiment of the present disclosure.

[0065] Figure 2A and Figure 2B show a display device DDa according to an embodiment of the present disclosure. In Figure 2A and Figure 2B a mobile phone is shown as an example of the display device DDa.

[0066] The display device DDa can display an image IM through the active area AA-D. The active area AA-D can include a plane defined by a first direction DR1 and a second direction DR2. The peripheral area NAA-D is adjacent to the active area AA-D. The peripheral area NAA-D can surround the active area AA-D. However, the peripheral area NAA-D can be disposed adjacent to only one side of the active area AA-D, or can be omitted.

[0067] The display device DDa according to this embodiment can include a housing HAU and a display module DMa. The display module DMa according to this embodiment can include a display panel DPa and a window member WMa.

[0068] The window member WMa can cover the entire outer side of the display panel DPa. The window member WMa can include a transmissive area TA and a border area BZA. The front surface FS of the window member WMa including the transmissive area TA and the border area BZA can correspond to the front surface of the display device DDa. The transmissive area TA can correspond to Figure 2A the active area AA-D of the display device DDa shown in Figure 2A and the border area BZA can correspond to

[0069] the peripheral area NAA-D of the display device DDa shown in

[0070] The display panel DPa can include an active area AA and a peripheral area NAA. The active area AA can be an area that is activated depending on an electrical signal. In this embodiment, the active area AA can be an area where the image IM is displayed. The active area AA of the display panel DPa can correspond to Figure 2A the active area AA-D of the display device DDa shown in Figure 2A and the peripheral area NAA of the display panel DPa can correspond to

[0071] Although in Figure 2A and Figure 2BAlthough not shown in the figure, the input sensing unit may be provided on the display panel DPa. The input sensing unit may sense an external input applied from the outside. The external input may be a user input. The user input may include various types of external inputs such as a part of the user's body, light, heat, a pen, or pressure. The input sensing unit may be directly provided on the display panel DPa or may be coupled to the display panel DPa through a separate adhesive member.

[0072] When a component (or region, layer, part, etc.) is described as being "directly provided" on another component, it means that a third component is not provided between the one component and the other component. That is, when a component is "directly provided" on another component, it means that the one component is "in contact" with the other component.

[0073] The housing HAU may accommodate the display panel DPa. The housing HAU may be coupled to the window member WMa.

[0074] has been referred to Figure 2A and Figure 2B The descriptions of the active area AA-D and the peripheral area NAA-D of the display device DDa, the transmissive area TA and the border area BZA of the window member WMa, and the active area AA and the peripheral area NAA of the display panel DPa may be equally applicable to the display device DD, the window member WM, and the display panel DP described above with reference to Figures 1A to 1D the descriptions.

[0075] Figure 3 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. In Figure 3 the cross-section of the display panel DP viewed in the first direction DR1 is shown.

[0076] Referring to Figure 3 the display panel DP may include a base layer BL, a circuit layer DP-CL provided on the base layer BL, a display element layer DP-OLED provided on the circuit layer DP-CL, and a thin film encapsulation layer TFE provided on the display element layer DP-OLED.

[0077] The base layer BL may include a display area DA and a non-display area NDA around the display area DA. The display area DA may correspond to the active area AA of the display panel DPa shown in Figure 2B and the non-display area NDA may correspond to the peripheral area NAA of the display panel DPa shown in Figure 2B The base layer BL may include a flexible plastic material such as polyimide ("PI"). The display element layer DP-OLED may be provided on the display area DA.

[0078] Multiple pixels may be provided in the circuit layer DP-CL and the display element layer DP-OLED. Each of the pixels may include a transistor provided in the circuit layer DP-CL and a light-emitting element provided in the display element layer DP-OLED and connected to the transistor. The configuration of the pixels will be described in detail below.

[0079] The thin-film encapsulation layer TFE may be provided on the circuit layer DP-CL to cover the display element layer DP-OLED. The thin-film encapsulation layer TFE may protect the pixels from moisture, oxygen, and external foreign substances.

[0080] Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0081] Reference Figure 4 , the display device DD (see FIG. 1) may include a display panel DP, a scan driver SDV, a data driver DDV, an emission driver EDV, and a plurality of pads PD.

[0082] The display panel DP may have a rectangular shape with a long side extending in the first direction DR1 and a short side extending in the second direction DR2. However, the shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0083] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a first power line PL1 and a second power line PL2, and a connection line CNL. Here, "m" and "n" are natural numbers greater than zero.

[0084] The pixels PX may be provided in the display area DA. The scan driver SDV and the emission driver EDV may be provided in the non-display area NDA adjacent to the long side of the display panel DP, respectively. The data driver DDV may be provided in the non-display area NDA adjacent to one of the short sides of the display panel DP. When viewed from above the plane, the data driver DDV may be adjacent to the lower end of the display panel DP.

[0085] The scan lines SL1 to SLm may extend in the second direction DR2 and may be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the first direction DR1 and may be connected to the pixels PX and the data driver DDV. The emission lines EL1 to ELm may extend in the second direction DR2 and may be connected to the pixels PX and the emission driver EDV.

[0086] The first power line PL1 can extend in the first direction DR1 and can be disposed in the non-display area NDA. The first power line PL1 can be disposed between the display area DA and the emission driver EDV.

[0087] The connection line CNL can extend in the second direction DR2 and can be arranged and connected to the first power line PL1 and the pixel PX in the first direction DR1. The first voltage can be applied to the pixel PX through the first power line PL1 and the connection line CNL connected to each other. The connection line CNL can be substantially defined as the portion of the first power line PL1 that receives the first voltage.

[0088] The second power line PL2 can be disposed in the non-display area NDA and can extend along the long side of the display panel DP and the other short side of the display panel DP where the data driver DDV is not provided. The second power line PL2 can be disposed outside the scan driver SDV and the emission driver EDV.

[0089] Although not shown, the second power line PL2 can extend toward the display area DA and can be connected to the pixel PX. The second voltage having a level lower than the level of the first voltage can be applied to the pixel PX through the second power line PL2.

[0090] The first control line CSL1 can be connected to the scan driver SDV and can extend toward the lower end of the display panel DP. The second control line CSL2 can be connected to the emission driver EDV and can extend toward the lower end of the display panel DP. The data driver DDV can be disposed between the first control line CSL1 and the second control line CSL2.

[0091] The pad PD can be disposed in the non-display area NDA adjacent to the lower end of the display panel DP and can be closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV, the first power line PL1 and the second power line PL2, and the first control line CSL1 and the second control line CSL2 can be connected to the pad PD. The data lines DL1 to DLn can be connected to the data driver DDV, and the data driver DDV can be connected to the pad PD corresponding to the data lines DL1 to DLn.

[0092] Although not shown, the display device DD can further include a timing controller for controlling the operations of the scan driver SDV, the data driver DDV, and the emission driver EDV, and a voltage generator for generating the first voltage and the second voltage. The timing controller and the voltage generator can be connected to the corresponding pad PD through a printed circuit board.

[0093] The scan driver SDV can generate a plurality of scan signals, and the scan signals can be applied to the pixels PX through the scan lines SL1 to SLm. The data driver DDV can generate a plurality of data voltages, and the data voltages can be applied to the pixels PX through the data lines DL1 to DLn. The emission driver EDV can generate a plurality of emission signals, and the emission signals can be applied to the pixels PX through the emission lines EL1 to ELm.

[0094] The pixel PX can receive the data voltage in response to the scan signal. The pixel PX can display an image by emitting light having a luminance corresponding to the data voltage in response to the emission signal.

[0095] Figure 5 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure. In the embodiment, for example, the pixel PX connected to the i-th scan line SLi, the i-th emission line Eli, and the j-th data line DLj ij In Figure 5 is shown. Here, "i" and "j" are natural numbers greater than zero.

[0096] Reference Figure 5 shows that the pixel PX ij may include a light-emitting element OLED and a pixel driving circuit PDC electrically connected to the light-emitting element OLED. The pixel driving circuit PDC may include transistors T1 to T7 and a capacitor CAP. The transistors T1 to T7 and the capacitor CAP can control the amount of current flowing through the light-emitting element OLED, and the light-emitting element OLED can generate light having a predetermined luminance depending on the amount of current supplied thereto.

[0097] The i-th scan line SLi may include a first to a third scan line GWi, GCi, and GIi of the i-th. The first scan line GWi of the i-th receiving the i-th write scan signal GWSi may be defined as the i-th write scan line GWi. The second scan line GCi of the i-th receiving the i-th compensation scan signal GCSi may be defined as the i-th compensation scan line GCi. The third scan line GIi of the i-th receiving the i-th initialization scan signal GISi may be defined as the i-th initialization scan line GIi.

[0098] The transistors T1 to T7 may include first to seventh transistors T1 to T7. Each of the first to seventh transistors T1 to T7 may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, the source electrode, the drain electrode, and the gate electrode may be referred to as a source, a drain, and a gate, respectively.

[0099] The expression "electrically connected between a transistor and a signal line or electrically connected between transistors" used herein means that an electrode of a transistor is integrally formed with a signal line or an electrode of a transistor is connected to a signal line through a connection electrode.

[0100] The first to seventh transistors T1 to T7 may be transistors having an oxide semiconductor layer or transistors having a low-temperature polysilicon (“LTPS”) semiconductor layer. The first to seventh transistors T1 to T7 may be N-type transistors or P-type transistors. In an embodiment, for example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be PMOS transistors having an LTPS semiconductor layer, and the third transistor T3 and the fourth transistor T4 may be NMOS transistors having an oxide semiconductor layer. However, embodiments of the transistors T1 to T7 are not limited thereto. In addition, although a pixel driving circuit PDC including seven transistors T1 to T7 is shown as an example, the number of transistors included in the pixel driving circuit PDC is not limited thereto.

[0101] The light-emitting element OLED may be defined as an organic light-emitting element. The light-emitting element OLED may include a first electrode AE and a second electrode CE. In an embodiment, for example, the first electrode AE may be an anode, and the second electrode CE may be a cathode. The first electrode AE of the light-emitting element OLED may be electrically connected to a first voltage line VL1 that receives a first driving voltage ELVDD. The second electrode CE of the light-emitting element OLED may be electrically connected to a second voltage line VL2 that receives a second driving voltage ELVSS (or a common voltage).

[0102] The first transistor T1 may be electrically connected between a first voltage line VL1 that receives a first driving voltage ELVDD and the light-emitting element OLED. The first transistor T1 may include a source electrode connected to a second node ND2, a drain electrode connected to a third node ND3, and a gate electrode connected to a first node ND1. The first transistor T1 may be turned on by the voltage of the first node ND1. The first transistor T1 may receive a data voltage Vd transmitted through the j-th data line DLj depending on the switching operation of the second transistor T2, and may supply a driving current Id to the light-emitting element OLED. In this embodiment, the first transistor T1 may be defined as a driving transistor.

[0103] The second transistor T2 can be electrically connected between the j-th data line DLj and the first transistor T1. The second transistor T2 can include a source connected to the j-th data line DLj, a drain connected to the second node ND2, and a gate connected to the i-th first scan line GWi. The second transistor T2 and the first transistor T1 can be connected through the second node ND2. The second transistor T2 can be turned on by the i-th write scan signal GWSi applied through the i-th first scan line GWi. The data voltage Vd applied to the j-th data line DLj can be transmitted to the source of the first transistor T1 through the turned-on second transistor T2. In this embodiment, the second transistor T2 can be defined as a switching transistor.

[0104] The third transistor T3 can be electrically connected between the fourth transistor T4 and the first transistor T1. The third transistor T3 can include a source connected to the first node ND1, a drain connected to the third node ND3, and a gate connected to the i-th second scan line GCi. The third transistor T3 and the first transistor T1 can be connected through the third node ND3. The third transistor T3 can be turned on by the i-th compensation scan signal GCSi applied through the i-th second scan line GCi. The gate and the drain of the first transistor T1 can be electrically connected to each other through the turned-on third transistor T3, and the first transistor T1 can be diode-connected. In this embodiment, the third transistor T3 can be defined as a compensation transistor.

[0105] The fourth transistor T4 can be electrically connected between the first initialization line VIL1 receiving the first initialization voltage Vint1 and the third transistor T3. The fourth transistor T4 can include a source connected to the first initialization line VIL1, a drain connected to the first node ND1, and a gate connected to the i-th third scan line GIi. The fourth transistor T4 can be turned on by the i-th initialization scan signal GISi applied through the i-th third scan line GIi. The first initialization voltage Vint1 can be transmitted to the first node ND1 through the turned-on fourth transistor T4, and the potential of the gate of the first transistor T1 can be initialized. In this embodiment, the fourth transistor T4 can be defined as an initialization transistor.

[0106] The fifth transistor T5 can be electrically connected between the first voltage line VL1 receiving the first driving voltage ELVDD and the first transistor T1. The fifth transistor T5 can include a source connected to the first voltage line VL1, a drain connected to the second node ND2, and a gate connected to the i-th emission line ELi.

[0107] The sixth transistor T6 may be electrically connected between the first transistor T1 and the light-emitting element OLED. The sixth transistor T6 may include a source connected to the third node ND3, a drain connected to the first electrode AE of the light-emitting element OLED through the fourth node ND4, and a gate connected to the i-th emission line ELi.

[0108] The fifth transistor T5 and the sixth transistor T6 may be turned on by an emission signal ESi applied through the i-th emission line ELi. The light-emitting time of the light-emitting element OLED may be controlled by the emission signal ESi. When the fifth transistor T5 and the sixth transistor T6 are turned on, a drive current Id depending on the voltage difference between the gate voltage of the first transistor T1 and the first drive voltage ELVDD may be generated. The drive current Id may be supplied to the light-emitting element OLED through the sixth transistor T6, and the light-emitting element OLED may emit light. In this embodiment, the fifth transistor T5 and the sixth transistor T6 may be defined as emission control transistors.

[0109] The seventh transistor T7 may be electrically connected between the sixth transistor T6 and the second initialization line VIL2 receiving the second initialization voltage Vint2. The seventh transistor T7 may include a source connected to the fourth node ND4, a drain connected to the second initialization line VIL2, and a gate connected to the (i - 1)-th first scan line GWi-1. The gate of the seventh transistor T7 may be connected to the (i - 1)-th write scan line GWi-1 which is the write scan line before the i-th write scan line GWi. However, this is not limited thereto, and the gate of the seventh transistor T7 may be electrically connected to a separate fourth scan line.

[0110] The seventh transistor T7 may be turned on by the (i - 1)-th write scan signal GWSi-1 applied through the (i - 1)-th first scan line GWi-1. The second initialization voltage Vint2 may be transmitted to the fourth node ND4 through the turned-on seventh transistor T7. The second initialization voltage Vint2 may have the same level as the level of the first initialization voltage Vint1. However, this is not limited thereto, and the second initialization voltage Vint2 may have a level different from the level of the first initialization voltage Vint1. In this embodiment, the seventh transistor T7 may be defined as an initialization transistor.

[0111] The seventh transistor T7 can improve the pixel PX ijThe ability to express black. A part of the driving current Id may leak as a bypass current through the seventh transistor T7. When a black image is displayed, a current that reduces the amount of the bypass current leaking from the driving current Id through the seventh transistor T7 can be supplied to the light-emitting element OLED, and thus the black image can be clearly displayed. That is, an accurate black luminance image can be achieved through the seventh transistor T7, and thus the contrast of the display device DD (refer to FIG. 1) can be improved.

[0112] The capacitor CAP may include a first electrode receiving the first driving voltage ELVDD and a second electrode connected to the first node ND1. A voltage corresponding to the voltage difference between the first electrode and the second electrode of the capacitor CAP may be stored in the capacitor CAP. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 may be determined depending on the voltage stored in the capacitor CAP.

[0113] Figure 5 The configuration of the pixel driving circuit PDC shown is illustrative and is not limited thereto, and various changes and modifications can be made to the configuration of the pixel driving circuit PDC.

[0114] Figure 6 is an enlarged cross-sectional view of a part of a display panel according to an embodiment of the present disclosure.

[0115] In Figure 6 , some of the transistors of the light-emitting element OLED and the pixel driving circuit PDC (refer to Figure 5 ) connected to the light-emitting element OLED are shown. The above description can be applied to the components of the display panel DP shown in Figure 6 .

[0116] Refer to Figure 6 , the display panel DP may include a base layer BL, a circuit layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE.

[0117] The base layer BL may provide a base surface on which the circuit layer DP-CL is provided. The circuit layer DP-CL may include an insulating layer BFL and 10 to 80, transistors TR1 and TR2, and connection electrodes CNE11 to CNE13 and CNE2. The insulating layer BFL and 10 to 80 may include a buffer layer BFL and the first to eighth insulating layers 10 to 80 provided on the buffer layer BFL. However, the insulating layer included in the circuit layer DP-CL is not limited thereto and may vary depending on the configuration of the pixel driving circuit PDC (refer to Figure 5 ) included in the circuit layer DP-CL and the process of the circuit layer DP-CL.

[0118] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BF may include at least one inorganic layer. In an embodiment, for example, the buffer layer BFL may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern layer or the conductive pattern layer of the circuit layer DP-CL disposed on the base layer BL.

[0119] Each of the first to eighth insulating layers 10 to 80 may include an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the material of the inorganic layer is not limited thereto. In an embodiment, the organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, silicone resin, polyamide resin, and perylene resin. However, the material of the organic layer is not limited thereto.

[0120] The light-blocking pattern BML may be disposed on the buffer layer BFL. When the buffer layer BFL is omitted, the light-blocking pattern BML may be directly disposed on the base layer BL. The light-blocking pattern BML may include molybdenum. The light-blocking pattern BML may perform a shielding function. The light-blocking pattern BML may block the potential influence on the transistors T1 to T7 due to polarization between the insulating layers 10 to 80 disposed on the light-blocking pattern BML (refer to Figure 5 ).

[0121] In Figure 6 , the first-type transistor TR1 and the second-type transistor TR2 of the pixel driving circuit PDC (refer to Figure 5 ) are shown. In this embodiment, the first-type transistor TR1 may be a silicon thin-film transistor, and the second-type transistor TR2 may be an oxide thin-film transistor. The first-type transistor TR1 may be one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 described in Figure 5 , and the second-type transistor TR2 may be one of the third transistor T3 and the fourth transistor T4 described in Figure 5 . In this embodiment, the first-type transistor TR1 and the second-type transistor TR2 may be disposed in different layers.

[0122] A semiconductor pattern of a first type transistor TR1 (hereinafter referred to as a first semiconductor pattern SP1) may be disposed on a first insulating layer 10. The first semiconductor pattern SP1 may include a silicon semiconductor. In an embodiment, for example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. In an embodiment, for example, the first semiconductor pattern SP1 may include low-temperature polycrystalline silicon. However, the material included in the first semiconductor pattern SP1 is not limited thereto as long as the first semiconductor pattern SP1 has semiconductor characteristics.

[0123] Figure 6 Only a portion of the first semiconductor pattern SP1 disposed on the first insulating layer 10 is shown, and the first semiconductor pattern SP1 may be additionally disposed in other regions. The first semiconductor pattern SP1 may be arranged across a plurality of pixels PX according to a specific rule (refer to Figure 4 ). The first semiconductor pattern SP1 may have different electrical characteristics depending on whether the first semiconductor pattern SP1 is doped. The first semiconductor pattern SP1 may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region or may be a region doped less than the first region.

[0124] The conductivity of the first region may be higher than that of the second region, and the first region may substantially serve as an electrode or a signal line. The second region may substantially correspond to the active (or channel) region of the first type transistor TR1. In other words, a part of the first semiconductor pattern SP1 may be the active region of the first type transistor TR1, another part of the first semiconductor pattern SP1 may be the source or drain of the first type transistor TR1, and the remaining part of the first semiconductor pattern SP1 may be a connection electrode or a connection signal line. In the description of the semiconductor pattern, Figure 5 the source and drain of the transistor described in

[0125] The source region S1, the active region A1, and the drain region D1 of the first type transistor TR1 may be formed by the first semiconductor pattern SP1. In a cross-sectional view, the source region S1 and the drain region D1 may extend from the active region A1 in opposite directions.

[0126] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the light blocking pattern BML. The second insulating layer 20 may be disposed on the first insulating layer 10. The second insulating layer 20 may cover the first semiconductor pattern SP1.

[0127] The gate electrode of the first type of transistor TR1 (hereinafter referred to as the first gate electrode GE1) may be disposed on the second insulating layer 20. In a plan view, the first gate electrode GE1 may overlap with the active region A1. In an embodiment, the first gate electrode GE1 may be used as a mask in the process of doping the first semiconductor pattern SP1.

[0128] Although Figure 6 An example is shown in which the first type of transistor TR1 has a top gate structure in which the first gate electrode GE1 is disposed on the first semiconductor pattern SP1, but the embodiment is not limited thereto, and in another embodiment, the first type of transistor TR1 may have a bottom gate structure in which the first gate electrode GE1 is disposed under the first semiconductor pattern SP1.

[0129] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may cover the first gate electrode GE1.

[0130] The scan line SL may be disposed on the third insulating layer 30. The scan line SL may correspond to a part of the above-described first to third scan lines GWi, GCi, and GIi (refer to Figure 5 ).

[0131] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may cover the scan line SL.

[0132] The semiconductor pattern of the second type of transistor TR2 (hereinafter referred to as the second semiconductor pattern SP2) may be disposed on the fourth insulating layer 40. The second semiconductor pattern SP2 may include an oxide semiconductor containing a metal oxide. The oxide semiconductor may include oxides of zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or may include a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. The oxide semiconductor may include indium tin oxide (“ITO”), indium gallium zinc oxide (“IGZO”), zinc oxide (ZnO), indium zinc oxide (“IZO”), zinc indium oxide (“ZIO”), indium oxide (InO x )), titanium oxide (TiO x )), indium zinc tin oxide (“IZTO”), or zinc tin oxide (“ZTO”). However, the embodiment is not necessarily limited thereto.

[0133] Depending on whether the metal oxide is reduced, the second semiconductor pattern SP2 may include a plurality of regions having different electrical characteristics. The region of the second semiconductor pattern SP2 where the metal oxide is reduced (hereinafter referred to as the reduced region) has a higher conductivity than the region of the second semiconductor pattern SP2 where the metal oxide is not reduced (hereinafter referred to as the non-reduced region). The reduced region may substantially serve as the source or drain of a transistor. The non-reduced region may substantially correspond to the active (or channel) region of the transistor.

[0134] The source region S2, the active region A2, and the drain region D2 of the second type transistor TR2 may be formed of the second semiconductor pattern SP2. In a cross-sectional view, the source region S2 and the drain region D2 may extend from the active region A2 in opposite directions.

[0135] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may cover the second semiconductor pattern SP2.

[0136] The gate electrode of the second type transistor TR2 (hereinafter referred to as the second gate electrode GE2) may be disposed on the fifth insulating layer 50. In a plan view, the second gate electrode GE2 may overlap with the active region A2. In an embodiment, the second gate electrode GE2 may be used as a mask in the process of doping the second semiconductor pattern SP2.

[0137] In an embodiment, the second semiconductor pattern SP2 may overlap with a portion of the scan line SL disposed below the second semiconductor pattern SP2 in a plan view. The portion of the scan line SL that overlaps with the second semiconductor pattern SP2 in a plan view may be used as the gate of the second type transistor TR2 together with the second gate electrode GE2. In this case, the gates of the second type transistors TR2 may be formed in pairs. Accordingly, the gates of the second type transistors TR2 may have a sufficient amount of gate charge and may switch at a high speed. In addition, since the scan line SL overlaps with the second semiconductor pattern SP2 in a plan view, the second semiconductor pattern SP2 can be prevented from being damaged by light introduced from below the display panel DP. However, the structure of the second type transistor TR2 is illustrative, and the embodiment is not limited thereto.

[0138] The second semiconductor pattern SP2 of the second type transistor TR2 and the first semiconductor pattern SP1 of the first type transistor TR1 may be disposed in different layers. However, this is illustrative, and all the semiconductor patterns of the transistors included in the pixel driving circuit PDC (refer to Figure 5 ) may be disposed in the same layer.

[0139] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may cover the second gate electrode GE2.

[0140] The connection electrodes CNE11, CNE12, CNE13, and CNE2 may include a first - 1 connection electrode CNE11, a first - 2 connection electrode CNE12, a first - 3 connection electrode CNE13, and a second connection electrode CNE2. The first - 1 connection electrode CNE11, the first - 2 connection electrode CNE12, and the first - 3 connection electrode CNE13 may be disposed on the sixth insulating layer 60. The first - 1 connection electrode CNE11, the first - 2 connection electrode CNE12, and the first - 3 connection electrode CNE13 may be disposed on the sixth insulating layer 60 so as to be spaced apart from each other in a plan view. In Figure 6 , for convenience, the connection electrodes CNE11, CNE12, and CNE13 are shown to overlap the entirety of the contact holes CNT - 11, CNT - 12a, CNT - 12b, and CNT - 13 and have a flat upper surface in a plan view. However, the connection electrodes CNE11, CNE12, and CNE13 of the embodiment may be disposed along the inner surfaces of the contact holes CNT - 11, CNT - 12a, CNT - 12b, and CNT - 13 and may not overlap the central portions of the contact holes CNT - 11, CNT - 12a, CNT - 12b, and CNT - 13 in a plan view. In this embodiment, auxiliary electrodes may be additionally disposed in at least some of the contact holes CNT - 11, CNT - 12a, CNT - 12b, and CNT - 13, and a detailed description thereof will be given below.

[0141] The first - 1 connection electrode CNE11 may be connected to the drain region D1 of the first - type transistor TR1. The first - 1 connection electrode CNE11 may be connected to the drain region D1 through the contact hole CNT - 11 that passes through the second to sixth insulating layers 20 to 60.

[0142] The first - 2 connection electrode CNE12 may be connected to the source region S1 of the first - type transistor TR1. The first - 2 connection electrode CNE12 may be connected to the source region S1 through the contact hole CNT - 12a that passes through the second to sixth insulating layers 20 to 60.

[0143] The first - 2 connection electrode CNE12 may extend and may overlap the drain region D2 of the second - type transistor TR2 in a plan view. The first - 2 connection electrode CNE12 may be connected to the drain region D2 through the contact hole CNT - 12b that passes through the fifth insulating layer 50 and the sixth insulating layer 60. Accordingly, the second semiconductor pattern SP2 of the second - type transistor TR2 and the first semiconductor pattern SP1 of the first - type transistor TR1 disposed in different layers may be electrically connected to each other through the first - 2 connection electrode CNE12.

[0144] The first to third connection electrodes CNE13 may be connected to the source region S2 of the second type transistor TR2. The first to third connection electrodes CNE13 may be connected to the source region S2 through contact holes CNT-13 that pass through the fifth insulating layer 50 and the sixth insulating layer 60.

[0145] The seventh insulating layer 70 may be provided on the sixth insulating layer 60. The seventh insulating layer 70 may cover the first to first connection electrodes CNE11, the first to second connection electrodes CNE12, and the first to third connection electrodes CNE13.

[0146] The second connection electrode CNE2 may be provided on the seventh insulating layer 70. Additionally, although not separately shown, some of the signal lines included in the display panel DP may be provided on the seventh insulating layer 70.

[0147] The second connection electrode CNE2 may be connected to the first to first connection electrode CNE11 through a contact hole CNT-2 that passes through the seventh insulating layer 70. The second connection electrode CNE2 may be connected to the drain region D1 of the first type transistor TR1 through the first to first connection electrode CNE11. In an embodiment, Figure 6 the first type transistor TR1 shown in may correspond to Figure 5 the sixth transistor T6 connected to the first electrode AE in. However, the embodiment is not limited thereto, and the second connection electrode CNE2 may be omitted, or in another embodiment, an additional connection electrode provided between the second connection electrode CNE2 and the first to first connection electrode CNE11 may be further provided in the circuit layer DP-CL.

[0148] The eighth insulating layer 80 may be provided on the seventh insulating layer 70. The eighth insulating layer 80 may cover the second connection electrode CNE2.

[0149] At least one of the seventh insulating layer 70 and the eighth insulating layer 80 may include an organic layer. The organic layer may provide a flat surface while covering particles present on the surface of the layer provided under the organic layer or covering steps between components provided under the organic layer. Additionally, the organic layer may relieve stress between components provided above and below the organic layer.

[0150] The display element layer DP-OLED may be provided on the circuit layer DP-CL. The display element layer DP-OLED may include a pixel defining layer PDL and a light emitting element OLED. The light emitting element OLED may include a first electrode AE, an emission layer EM, and a second electrode CE.

[0151] The light-emitting element OLED may include an organic light-emitting element, a quantum dot light-emitting element, a micro LED light-emitting element, or a nano LED light-emitting element. However, the embodiments are not limited thereto, and the light-emitting element OLED may include various embodiments as long as it generates light or controls the amount of light depending on an electrical signal.

[0152] The light-emitting element OLED may be electrically connected to a transistor of a corresponding pixel driving circuit PDC (refer to Figure 5 ). Figure 6 An example is shown in which the light-emitting element OLED is electrically connected to a corresponding transistor (e.g., Figure 5 the sixth transistor T6).

[0153] The first electrode AE of the light-emitting element OLED may be disposed on the uppermost layer of the circuit layer DP-CL. In an embodiment, for example, the first electrode AE may be disposed on the eighth insulating layer 80. The first electrode AE may be connected to a corresponding second connection electrode CNE2 through a contact hole CNT-U passing through the eighth insulating layer 80. The first electrode AE may be electrically connected to the first-type transistor TR1 through the second connection electrode CNE2 and the 1-1 connection electrode CNE11.

[0154] The pixel defining layer PDL may be disposed on the uppermost layer of the circuit layer DP-CL. In an embodiment, for example, the pixel defining layer PDL may be disposed on the eighth insulating layer 80. A light-emitting opening PX-OP for exposing a part of the first electrode AE may be defined in the pixel defining layer PDL. The display area DA of the display panel DP (refer to Figure 4 ) may include an emission area PXA and a non-emission area NPXA. In this embodiment, the part of the first electrode AE exposed through the light-emitting opening PX-OP may correspond to the emission area PXA. The area where the pixel defining layer PDL is disposed may correspond to the non-emission area NPXA. In a plan view, the non-emission area NPXA may surround the emission area PXA and may define the boundary of the emission area PXA.

[0155] The pixel defining layer PDL may include a polymer resin. In an embodiment, for example, the pixel defining layer PDL may include a polyacrylate resin or a polyimide resin. However, it is not limited thereto, and the pixel defining layer PDL may further include an inorganic material.

[0156] The pixel defining layer PDL may further include a light absorption material. In an embodiment, for example, the pixel defining layer PDL may include a black colorant such as a black dye or a black pigment. In an embodiment, for example, the black colorant may include carbon black, a metal such as chromium, or an oxide thereof. However, the embodiments are not necessarily limited thereto.

[0157] The emission layer EM can be disposed on the first electrode AE. The emission layer EM of the light-emitting element OLED can be arranged to correspond to the light-emitting opening PX-OP, and can be formed in an emission pattern spaced apart with respect to a plurality of light-emitting elements in a plan view. However, not limited thereto, the emission layer EM can be formed of an integrated film and can be used as a common layer for a plurality of light-emitting elements. The emission layer EM can include an organic light-emitting material and / or an inorganic light-emitting material. In an embodiment, for example, the emission layer EM can include a fluorescent material, a phosphorescent material, a metal-organic composite light-emitting material, or a quantum dot. The emission layer EM can emit one of red light, green light, and blue light.

[0158] The second electrode CE can be disposed on the emission layer EM and the pixel defining layer PDL. The second electrode CE can overlap with the emission region PXA and the non-emission region NPXA. The second electrode CE can be commonly disposed with respect to a plurality of pixels PX (refer to Figure 4 ), and a common voltage can be provided to the plurality of pixels PX through the second electrode CE (refer to Figure 4 ).

[0159] Although not shown, the light-emitting element OLED can further include an emission control layer disposed between the first electrode AE and the second electrode CE. In an embodiment, for example, the emission control layer can include a hole control layer disposed between the first electrode AE and the emission layer EM and an electron control layer disposed between the emission layer EM and the second electrode CE. The hole control layer can include a hole injection layer, a hole transport layer, or an electron blocking layer, and the electron control layer can include an electron injection layer, an electron transport layer, or a hole blocking layer.

[0160] The thin film encapsulation layer TFE can be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE can seal the light-emitting element OLED. The thin film encapsulation layer TFE can include at least one of an inorganic film and an organic film. In an embodiment, the thin film encapsulation layer TFE can include an inorganic film and an organic film disposed between the inorganic films.

[0161] The inorganic film of the thin film encapsulation layer TFE can protect the light-emitting element OLED from moisture and / or oxygen. The inorganic film can include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the material of the inorganic film is not limited thereto.

[0162] The organic film of the thin film encapsulation layer TFE can protect the light-emitting element OLED from foreign substances such as dust particles. The organic film can include an acrylic resin. However, the material of the organic film is not limited thereto.

[0163] Figure 7 is a cross-sectional view of a partial configuration of a display device according to an embodiment of the present disclosure. Figure 7 is related toFigure 6 An enlarged view of a portion corresponding to the region AA’ shown in, and Figure 7 shows a cross-section within the circuit layer DP-CL (refer to Figure 6 ). In Figure 7 , a contact hole CNT passing through the insulating layer ISL within the circuit layer DP-CL (refer to Figure 6 ) is shown. In the description Figure 7 , components that are the same as or similar to those described with reference to Figures 1A to 6 will be assigned the same or similar reference numerals, and repeated descriptions will be omitted.

[0164] Refer to Figure 7 . According to this embodiment, the contact hole CNT may expose a portion of the semiconductor pattern SP. Figure 7 The semiconductor pattern SP of Figure 6 may be the first semiconductor pattern SP1 of the first type transistor TR1 in Figure 6 or the second semiconductor pattern SP2 of the second type transistor TR2 in

[0165] When Figure 7 the semiconductor pattern SP corresponds to the first semiconductor pattern SP1 of Figure 6 , the insulating layer ISL of Figure 7 may correspond to the second to sixth insulating layers 20 to 60 of Figure 6 . Figure 7 The contact hole CNT of Figure 6 may be a contact hole defined to pass through the second to sixth insulating layers 20 to 60 in Figure 6 (for example, the contact holes CNT-11 and CNT-12a of

[0166] When Figure 7 the semiconductor pattern SP corresponds to the second semiconductor pattern SP2 of Figure 6 , the insulating layer ISL of Figure 7 may correspond to the fifth insulating layer 50 and the sixth insulating layer 60 of Figure 6 . Figure 7 The contact hole CNT of Figure 6 may be a contact hole defined to pass through the fifth insulating layer 50 and the sixth insulating layer 60 in Figure 6 (for example, the contact holes CNT-12b and CNT-13 of

[0167] In this specification, the contact hole CNT may include a sidewall and a bottom surface. The sidewall of the contact hole CNT may correspond to the inner surface S-I of the insulating layer ISL that defines the contact hole CNT, and the bottom surface of the contact hole CNT may correspond to the upper surface U-S of the semiconductor pattern SP exposed from the insulating layer ISL.

[0168] The slope of the inner surface S-I of the defined contact hole CNT of the insulating layer ISL (or the sidewall of the contact hole CNT) can be substantially vertical. In an embodiment, the inner surface S-I of the insulating layer ISL can have a slope of 80 degrees to 90 degrees. The "slope" of the inner surface S-I of the insulating layer ISL can be defined as the angle θ formed by the inner surface S-I of the insulating layer ISL with respect to the upper surface U-S of the semiconductor pattern SP. Since the slope of the inner surface S-I of the insulating layer ISL is substantially vertical, the width difference between the upper side and the lower side of the contact hole CNT can be minimized. Accordingly, in the process of reducing the size of the contact hole CNT, the reduction of the exposed area of the semiconductor pattern SP can be minimized, and high resolution can be more easily achieved.

[0169] In an embodiment, the contact hole CNT can have a width w-CNT of 2.0 micrometers or less. In an embodiment, for example, the contact hole CNT can have a width w-CNT of 1.0 micrometer to 2.0 micrometers. The "width w-CNT" of the contact hole CNT can be defined as the maximum width of the contact hole CNT in a direction perpendicular to the third direction DR3 (e.g., the first direction DR1). In an embodiment, the contact hole CNT can have a circular shape in a plan view, and the width w-CNT of the contact hole CNT can correspond to the maximum diameter of the contact hole CNT in the plan view.

[0170] The display panel DP according to the present disclosure (refer to Figure 6 ) can further include an auxiliary electrode AXE disposed at least partially in the contact hole CNT. The auxiliary electrode AXE according to this embodiment can include a first auxiliary portion P1-A, a second auxiliary portion P2-A, and a third auxiliary portion P3-A.

[0171] The first auxiliary portion P1-A can be a portion in contact with the inner surface S-I of the defined contact hole CNT of the insulating layer ISL. The first auxiliary portion P1-A can cover the entire inner surface S-I of the defined contact hole CNT of the insulating layer ISL (or the sidewall of the contact hole CNT). The second auxiliary portion P2-A can be a portion in contact with the semiconductor pattern SP exposed from the insulating layer ISL through the contact hole CNT. The second auxiliary portion P2-A can cover the entire upper surface U-S (or the bottom surface of the contact hole CNT) of the semiconductor pattern SP exposed from the insulating layer ISL. The third auxiliary portion P3-A can be a portion in contact with a part of the upper surface U-I of the insulating layer ISL.

[0172] In this specification, for ease of description, the first to third auxiliary portions P1-A, P2-A, and P3-A are defined by dividing the regions of the auxiliary electrode AXE. The first to third auxiliary portions P1-A, P2-A, and P3-A substantially form one component.

[0173] In an embodiment, the auxiliary electrode AXE may include tungsten (W). Tungsten may have excellent step coverage. Tungsten can be easily deposited by a deposition process (e.g., a chemical vapor deposition (“CVD”) process) that can provide excellent step coverage characteristics. Accordingly, even if the inner surface S-I of the contact hole CNT defined by the insulating layer ISL has a substantially vertical slope, the auxiliary electrode AXE can cover the entire inner surface S-I of the insulating layer ISL (or the sidewall of the contact hole CNT), and the first auxiliary portion P1-A and the second auxiliary portion P2-A may not be separated.

[0174] The auxiliary electrode AXE may be deposited in the form of a thin film and may cover the sidewall and the bottom surface of the contact hole CNT. In an embodiment, the auxiliary electrode AXE may have to a thickness t-AXE. When the auxiliary electrode AXE has a thickness t-AXE less than , the electrical connection with the semiconductor pattern SP and the connection electrode CNE may be unstable. The auxiliary electrode AXE according to an embodiment may include a material having a higher resistance than the resistance of the connection electrode CNE. When the auxiliary electrode AXE has a thickness t-AXE greater than , the total resistance of the electrode electrically connected to the semiconductor pattern SP may be increased, and thus the power consumption may be increased.

[0175] The connection electrode CNE may include a first connection portion P1-C and a second connection portion P2-C.

[0176] The first connection portion P1-C may be a portion disposed on the insulating layer ISL. The first connection portion P1-C may contact the third auxiliary portion P3-A of the auxiliary electrode AXE. The first connection portion P1-C may cover the entire third auxiliary portion P3-A. In a plan view, a part of the first connection portion P1-C may overlap a part of the contact hole CNT.

[0177] The second connection portion P2-C may be a portion extending downward from the first connection portion P1-C and disposed in the contact hole CNT. The second connection portion P2-C may contact the first auxiliary portion P1-A of the auxiliary electrode AXE. The second connection portion P2-C may cover only a part of the first auxiliary portion P1-A. That is, the remaining part of the first auxiliary portion P1-A may be exposed and not covered by the connection electrode CNE. Since the second connection portion P2-C extends downward, the second connection portion P2-C may have a decreasing thickness.

[0178] In this specification, for ease of description, the first connection portion P1-C and the second connection portion P2-C are defined by dividing the region of the connection electrode CNE. The first connection portion P1-C and the second connection portion P2-C substantially form a single component.

[0179] In a plan view, the connection electrode CNE may overlap an outer portion of the contact hole CNT, but may not overlap an inner portion of the contact hole CNT. The "outer portion" of the contact hole CNT may refer to a portion of the contact hole CNT adjacent to the sidewall of the contact hole CNT, and the "inner portion" of the contact hole CNT may refer to a portion of the contact hole CNT adjacent to the center of the contact hole CNT.

[0180] In this embodiment, the connection electrode CNE may include a first-to-first connection electrode layer L1a-C and a second-to-first connection electrode layer L2a-C. The first-to-first connection electrode layer L1a-C may be directly disposed on the first auxiliary portion P1-A and the third auxiliary portion P3-A of the auxiliary electrode AXE. The second-to-first connection electrode layer L2a-C may be directly disposed on the first-to-first connection electrode layer L1a-C.

[0181] In this embodiment, the first connection portion P1-C may include a portion of the first-to-first connection electrode layer L1a-C disposed on the insulating layer ISL (hereinafter referred to as the first-to-first sub-portion 11) and a portion of the second-to-first connection electrode layer L2a-C disposed on the insulating layer ISL (hereinafter referred to as the second-to-first sub-portion 21). The second connection portion P2-C may include a portion of the first-to-first connection electrode layer L1a-C disposed in the contact hole CNT (hereinafter referred to as the third-to-first sub-portion 31) and a portion of the second-to-first connection electrode layer L2a-C disposed in the contact hole CNT (hereinafter referred to as the fourth-to-first sub-portion 41).

[0182] The first-to-first connection electrode layer L1a-C may have an average thickness greater than the average thickness of the second-to-first connection electrode layer L2a-C. The first-to-first connection electrode layer L1a-C may have an average thickness greater than the average thickness of the auxiliary electrode AXE. In this specification, in the first connection portion P1-C, the thickness of the connection electrode CNE may refer to the thickness in the third direction DR3, and in the second connection portion P2-C, the thickness of the connection electrode CNE may refer to the thickness in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2. In the second auxiliary portion P2-A and the third auxiliary portion P3-A, the thickness of the auxiliary electrode AXE may refer to the thickness in the third direction DR3, and in the first auxiliary portion P1-A, the thickness of the auxiliary electrode AXE may refer to the thickness in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0183] Each of the 1-1st connecting electrode layer L1a-C and the 2-1st connecting electrode layer L2a-C may include a conductive material. The 1-1st connecting electrode layer L1a-C may include a first conductive material, and the 2-1st connecting electrode layer L2a-C may include a second conductive material different from the first conductive material. In an embodiment, the first conductive material may have a higher conductivity than the second conductive material. In addition, in an embodiment, the first conductive material may have a lower resistance than the second conductive material. In an embodiment, for example, the 1-1st connecting electrode layer L1a-C may include aluminum (Al), and the 2-1st connecting electrode layer L2a-C may include titanium (Ti).

[0184] According to the circuit layer DP-CL of this embodiment (refer to Figure 6 ) may further include a dummy electrode DME disposed in the contact hole CNT. The dummy electrode DME may be directly disposed on the second auxiliary portion P2-A of the auxiliary electrode AXE in the contact hole CNT. The dummy electrode DME may cover the entirety of the second auxiliary portion P2-A.

[0185] In this embodiment, the dummy electrode DME may include a 1st dummy electrode layer L1a-D and a 2nd dummy electrode layer L2a-D. The 1st dummy electrode layer L1a-D may be directly disposed on the second auxiliary portion P2-A, and the 2nd dummy electrode layer L2a-D may be directly disposed on the 1st dummy electrode layer L1a-D.

[0186] The dummy electrode DME may be spaced apart from the connection electrode CNE. The dummy electrode DME may be formed simultaneously with the connection electrode CNE during a process of forming the connection electrode CNE. The dummy electrode DME may be separated from the connection electrode CNE. The dummy electrode DME may be provided at least in an inner portion of the contact hole CNT that does not overlap with the connection electrode CNE in a plan view.

[0187] The 1-1st dummy electrode layer L1a-D may be formed to be separate from the 1-1st connection electrode layer L1a-C. The 1-1st dummy electrode layer L1a-D may include the same material as the 1-1st connection electrode layer L1a-C. The 2-1st dummy electrode layer L2a-D may be formed to be separate from the 2-1st connection electrode layer L2a-C. The 2-1st dummy electrode layer L2a-D may include the same material as the 2-1st connection electrode layer L2a-C. In an embodiment, the 1-1st dummy electrode layer L1a-D may include aluminum, and the 2-1st dummy electrode layer L2a-D may include titanium.

[0188] When the contact hole CNT has a small size and the slope of the sidewall of the contact hole CNT is substantially vertical, the connection electrode CNE may protrude, and thus a shadow effect may occur. In the deposition process for forming the connection electrode CNE, the deposition material may not reach the end portion at the lower side (i.e., the bottom) of the contact hole CNT. Accordingly, in the process of forming the connection electrode CNE, a dummy electrode DME separated from the connection electrode CNE may be formed together.

[0189] According to this embodiment, by providing an auxiliary electrode AXE including a portion in contact with the connection electrode CNE (i.e., the first auxiliary portion P1-A and the third auxiliary portion P3-A) and a portion in contact with the upper surface U-S of the semiconductor pattern SP (i.e., the second auxiliary portion P2-A), the connection electrode CNE can be electrically connected to the semiconductor pattern SP through the auxiliary electrode AXE. Accordingly, even if the connection electrode CNE only covers a part of the sidewall of the contact hole CNT and has a shape disconnected from the semiconductor pattern SP in the contact hole CNT, connection defects of the connection electrode CNE can be effectively prevented through the auxiliary electrode AXE.

[0190] In this embodiment, the auxiliary electrode AXE can be in direct contact with the semiconductor pattern SP. In an embodiment, the auxiliary electrode AXE can include tungsten, and the semiconductor pattern SP can include polysilicon. Tungsten can form a stable ohmic contact with polysilicon. Accordingly, the auxiliary electrode AXE and the semiconductor pattern SP can ensure stable contact characteristics, and thus a pixel driving circuit PDC having stable electrical characteristics (refer to Figure 5 ) and a display device DD including the pixel driving circuit PDC (refer to Figure 5 ) can be provided.

[0191] Figure 8 is a cross-sectional view of a partial configuration of a display device according to an embodiment of the present disclosure. Figure 8 is an enlarged view of a portion corresponding to the region AA' shown in Figure 6 , where Figure 8 shows a cross-section within the circuit layer DP-CL (refer to Figure 6 ). In Figure 8 , a contact hole CNT passing through an insulating layer ISL within the circuit layer DP-CL (refer to Figure 6 ) is shown. When describing Figure 8 , components that are the same as or similar to those described with reference to Figures 1A to 7 will be assigned the same or similar reference numerals, and repeated descriptions will be omitted.

[0192] Refer to Figure 8, according to this embodiment, the auxiliary electrode AXE' can be entirely disposed within the contact hole CNT. The auxiliary electrode AXE' can be in contact with the inner surface S-I of the insulating layer ISL that defines the contact hole CNT. The auxiliary electrode AXE' can cover the entirety of the inner surface S-I of the insulating layer ISL that defines the contact hole CNT (or the sidewall of the contact hole CNT). At the same time, according to this embodiment, the auxiliary electrode AXE' can be provided in the form of a thin film that only covers the inner surface S-I of the insulating layer ISL. The lower edge of the auxiliary electrode AXE' can be in contact with the semiconductor pattern SP. The upper surface U-S of the semiconductor pattern SP can be exposed through the auxiliary electrode AXE'. Additionally, according to this embodiment, the auxiliary electrode AXE' can not cover the upper surface U-I of the insulating layer ISL. That is to say, Figure 8 the auxiliary electrode AXE' in Figure 7 can only include the first auxiliary portion P1-A of the auxiliary electrode AXE in

[0193] In an embodiment, the auxiliary electrode AXE' can include tungsten (W). Tungsten can have excellent step coverage. Tungsten can be easily deposited through a deposition process that can provide excellent step coverage characteristics (e.g., chemical vapor deposition (“CVD”) process). Accordingly, even if the inner surface S-I of the insulating layer ISL that defines the contact hole CNT has a substantially vertical slope, the auxiliary electrode AXE' can cover the entirety of the inner surface S-I of the insulating layer ISL (or the sidewall of the contact hole CNT).

[0194] The connection electrode CNE' can include a first connection portion P1-C' disposed on the insulating layer ISL and a second connection portion P2-C' disposed within the contact hole CNT. The first connection portion P1-C' can be in contact with a portion of the upper surface U-I of the insulating layer ISL. The second connection portion P2-C' can be in contact with the auxiliary electrode AXE'. The second connection portion P2-C' can only cover a portion of the auxiliary electrode AXE'.

[0195] In this specification, for ease of description, the first connection portion P1-C' and the second connection portion P2-C' are defined by dividing the region of the connection electrode CNE'. The first connection portion P1-C' and the second connection portion P2-C' substantially form a single component.

[0196] In this embodiment, the connection electrode CNE' may include a lower connection electrode layer LL-C, a first-second connection electrode layer L1b-C, and a second-second connection electrode layer L2b-C. The portion of the lower connection electrode layer LL-C included in the first connection portion P1-C' may be directly disposed on the upper surface U-I of the insulating layer ISL, and the portion of the lower connection electrode layer LL-C included in the second connection portion P2-C' may be in contact with a part of the auxiliary electrode AXE' and may cover this part of the auxiliary electrode AXE'. The first-second connection electrode layer L1b-C may be directly disposed on the lower connection electrode layer LL-C, and the second-second connection electrode layer L2b-C may be directly disposed on the first-second connection electrode layer L1b-C.

[0197] In this embodiment, the first connection portion P1-C' may include the portion of the lower connection electrode layer LL-C disposed on the insulating layer ISL (hereinafter referred to as the first lower sub-portion B1), the portion of the first-second connection electrode layer L1b-C disposed on the insulating layer ISL (hereinafter referred to as the first-second sub-portion 12), and the portion of the second-second connection electrode layer L2b-C disposed on the insulating layer ISL (hereinafter referred to as the second-second sub-portion 22). The second connection portion P2-C' may include the portion of the lower connection electrode layer LL-C disposed in the contact hole CNT (hereinafter referred to as the second lower sub-portion B2), the portion of the first-second connection electrode layer L1b-C disposed in the contact hole CNT (hereinafter referred to as the third-second sub-portion 32), and the portion of the second-second connection electrode layer L2b-C disposed in the contact hole CNT (hereinafter referred to as the fourth-second sub-portion 42).

[0198] The first-second connection electrode layer L1b-C may have an average thickness greater than the average thickness of the lower connection electrode layer LL-C and the second-second connection electrode layer L2b-C. The first-second connection electrode layer L1b-C may have an average thickness greater than the average thickness of the auxiliary electrode AXE'.

[0199] Each of the lower connection electrode layer LL-C, the first-second connection electrode layer L1b-C, and the second-second connection electrode layer L2b-C may include a conductive material. The first-second connection electrode layer L1b-C may include a first conductive material, and the lower connection electrode layer LL-C and the second-second connection electrode layer L2b-C may include a second conductive material different from the first conductive material. The lower connection electrode layer LL-C may include the same material as that of the second-second connection electrode layer L2b-C. In an embodiment, the first conductive material may have a higher conductivity than the second conductive material. Further, in an embodiment, the first conductive material may have a lower resistance than the second conductive material. In an embodiment, for example, the first-second connection electrode layer L1b-C may include aluminum, and each of the lower connection electrode layer LL-C and the second-second connection electrode layer L2b-C may include titanium.

[0200] [[ID=__3]]The dummy electrode DME’ may be directly disposed on the upper surface U-S of the semiconductor pattern SP exposed from the insulating layer ISL and on the auxiliary electrode AXE’ in the contact hole CNT. The dummy electrode DME’ may cover the entire exposed upper surface U-S of the semiconductor pattern SP. An edge of the dummy electrode DME’ adjacent to the sidewall of the contact hole CNT may be in contact with the auxiliary electrode AXE’.

[0201] The dummy electrode DME’ may include a lower dummy electrode layer LL-D, a first-second dummy electrode layer L1b-D, and a second-second dummy electrode layer L2b-D. The lower dummy electrode layer LL-D may be directly disposed on the upper surface U-S of the semiconductor pattern SP, the first-second dummy electrode layer L1b-D may be directly disposed on the lower dummy electrode layer LL-D, and the second-second dummy electrode layer L2b-D may be directly disposed on the first-second dummy electrode layer L1b-D.

[0202] The lower dummy electrode layer LL-D may be formed separately from the lower connection electrode layer LL-C, the first-second dummy electrode layer L1b-D may be formed separately from the first-second connection electrode layer L1b-C, and the second-second dummy electrode layer L2b-D may be formed separately from the second-second connection electrode layer L2b-C. The lower dummy electrode layer LL-D may include the same material as that of the lower connection electrode layer LL-C, the first-second dummy electrode layer L1b-D may include the same material as that of the first-second connection electrode layer L1b-C, and the second-second dummy electrode layer L2b-D may include the same material as that of the second-second connection electrode layer L2b-C. In an embodiment, the first-second dummy electrode layer L1b-D may include aluminum, and each of the lower dummy electrode layer LL-D and the second-second dummy electrode layer L2b-D may include titanium.

[0203] According to this embodiment, the dummy electrode DME' can be in direct contact with the semiconductor pattern SP. However, by providing the auxiliary electrode AXE' including a portion in contact with the dummy electrode DME' and a portion in contact with the connection electrode CNE', the connection electrode CNE' can be electrically connected to the semiconductor pattern SP through the auxiliary electrode AXE' and the dummy electrode DME'. Accordingly, even if a shadow effect occurs and the connection electrode CNE' only covers a part of the sidewall of the contact hole CNT and has a shape disconnected from the semiconductor pattern SP in the contact hole CNT, connection defects of the connection electrode CNE' can be effectively prevented through the auxiliary electrode AXE'.

[0204] In this embodiment, the dummy electrode DME' can be in direct contact with the semiconductor pattern SP. In the embodiment, the lower dummy electrode layer LL-D of the dummy electrode DME' can include titanium, and the semiconductor pattern SP can include polysilicon. Titanium can form a stable ohmic contact with polysilicon. Accordingly, the dummy electrode DME' and the semiconductor pattern SP can ensure stable contact characteristics, and thus a pixel driving circuit PDC having stable electrical characteristics (refer to Figure 5 ) and a display device DD including the pixel driving circuit PDC (refer to Figure 5 ) (refer to FIG. 1) can be provided.

[0205] Although the connection form between the semiconductor pattern SP and the electrode in the contact hole CNT exposing the semiconductor pattern SP has been described with reference to Figure 7 and Figure 8 , the embodiment is not necessarily limited thereto, and other contact holes exposing other electrodes or electrode layers having conductivity can have a structure including the above-described connection form in the contact hole CNT referred to above with reference to Figure 7 or Figure 8 .

[0206] Hereinafter, a method for manufacturing a display device according to an embodiment will be described with reference to the accompanying drawings. When describing the method for manufacturing a display device according to an embodiment, repetitive descriptions identical to those of the description of the display device will be omitted.

[0207] Figures 9A to 9F is a cross-sectional view showing some of the steps of a method for manufacturing a display device according to an embodiment of the present disclosure.

[0208] The method for manufacturing a display device according to this embodiment may include: providing a semiconductor pattern and an insulating layer in which contact holes are defined to expose a part of the semiconductor pattern; forming a preliminary auxiliary electrode on the insulating layer; forming a preliminary connection electrode on the insulating layer; etching the preliminary connection electrode to form a connection electrode partially disposed in the contact holes; and etching the preliminary auxiliary electrode to form an auxiliary electrode at least partially disposed in the contact holes. The auxiliary electrode may be in contact with the connection electrode and the semiconductor pattern, and in a plan view, the connection electrode may not overlap with a part (e.g., an inner part) of the contact hole.

[0209] Reference Figure 9A , the method for manufacturing a display device according to this embodiment may include providing an insulating layer ISL in which contact holes CNT are defined.

[0210] The insulating layer ISL may be a component covering a part of the semiconductor pattern SP. The semiconductor pattern SP may be provided in a state in which a part of the semiconductor pattern SP is exposed from the insulating layer ISL through the contact holes CNT.

[0211] The inner surface S-I of the insulating layer ISL defining the contact holes CNT (or the sidewall of the contact holes CNT) may have a substantially vertical slope. In an embodiment, the inner surface S-I of the insulating layer ISL defining the contact holes CNT may have a slope of 80 degrees to 90 degrees.

[0212] Reference Figure 9B , the method for manufacturing a display device according to this embodiment may further include forming a preliminary auxiliary electrode AXE-I. The preliminary auxiliary electrode AXE-I may be formed on the insulating layer ISL.

[0213] The preliminary auxiliary electrode AXE-I may be formed by a deposition process. In an embodiment, the deposition process of the preliminary auxiliary electrode AXE-I may be performed by a chemical vapor deposition (“CVD”) process. The chemical vapor deposition process may provide excellent step coverage characteristics. Accordingly, the preliminary auxiliary electrode AXE-I may be deposited to cover all of the upper surface U-I of the insulating layer ISL, the inner surface S-I of the insulating layer ISL defining the contact holes CNT, and the exposed upper surface U-S of the semiconductor pattern SP. That is, the preliminary auxiliary electrode AXE-I may be deposited to cover both the sidewall and the bottom surface of the contact holes CNT.

[0214] In an embodiment, the preliminary auxiliary electrode AXE-I may include tungsten (W). Tungsten may be a material that can be easily deposited by a chemical vapor deposition process. Accordingly, the preliminary auxiliary electrode AXE-I may be easily formed by a chemical vapor deposition process and may have excellent step coverage.

[0215] The preliminary auxiliary electrode AXE-I may include a first auxiliary portion P1-A, a second auxiliary portion P2-A, and a third preliminary auxiliary portion P3-AI. The first auxiliary portion P1-A may cover the entire inner surface S-I of the insulating layer ISL that defines the contact hole CNT (or the sidewall of the contact hole CNT). The second auxiliary portion P2-A may cover the entire upper surface U-S of the semiconductor pattern SP that is exposed from the insulating layer ISL (or the bottom surface of the contact hole CNT). The third preliminary auxiliary portion P3-AI may cover the entire upper surface U-I of the insulating layer ISL.

[0216] Reference Figure 9C , the method for manufacturing a display device according to this embodiment may further include a step of forming a preliminary connection electrode CNE-I. The preliminary connection electrode CNE-I may be formed on the preliminary auxiliary electrode AXE-I.

[0217] In this embodiment, the step of forming the preliminary connection electrode CNE-I may include a step of forming a first 1-1 preliminary connection electrode layer L1a-CI (or a first 1-1 conductive layer) and a step of forming a second 2-1 preliminary connection electrode layer L2a-CI (or a second 2-1 conductive layer). The first 1-1 preliminary connection electrode layer L1a-CI may be formed on the preliminary auxiliary electrode AXE-I, and the second 2-1 preliminary connection electrode layer L2a-CI may be formed on the first 1-1 preliminary connection electrode layer L1a-CI.

[0218] The step of forming the first 1-1 preliminary connection electrode layer L1a-CI may be performed by a deposition process of a first conductive material, and the step of forming the second 2-1 preliminary connection electrode layer L2a-CI may be performed by a deposition process of a second conductive material. The first conductive material and the second conductive material may include different materials. In an embodiment, for example, the first conductive material may include aluminum, and the second conductive material may include titanium. In an embodiment, both the deposition process of the first conductive material and the deposition process of the second conductive material may be performed by a sputtering process.

[0219] The preliminary connection electrode CNE-I may include a first preliminary connection part P1-CI and a second connection part P2-C. The first preliminary connection part P1-CI may cover the entire third preliminary auxiliary part P3-AI of the preliminary auxiliary electrode AXE-I. A part of the first preliminary connection part P1-CI may be formed to overlap with a part of the contact hole CNT in a plan view. That is, the preliminary connection electrode CNE-I may protrude. "Protrude" may mean that since a large amount of material is deposited on the upper part of the insulating layer ISL during the deposition process of the preliminary connection electrode CNE-I, the deposited preliminary connection electrode CNE-I protrudes toward the part overlapping with the contact hole CNT in the plan view. In this embodiment, the first preliminary connection part P1-CI may include a part of the 1-1 preliminary connection electrode layer L1a-CI disposed on the insulating layer ISL (hereinafter, referred to as the 1-1 preliminary sub-part 11-I) and a part of the 2-1 preliminary connection electrode layer L2a-CI disposed on the insulating layer ISL (hereinafter, referred to as the 2-1 preliminary sub-part 21-I).

[0220] The second connection part P2-C may be a part formed in the contact hole CNT. Due to the protrusion of the preliminary connection electrode CNE-I, a shadow effect may occur. Accordingly, the first conductive material and the second conductive material may not be deposited near the end of the lower side (i.e., the bottom) of the contact hole CNT. The second connection part P2-C may only cover a part of the first auxiliary part P1-A. Accordingly, in a plan view, the preliminary connection electrode CNE-I may not overlap with the remaining part of the contact hole CNT except for the part overlapping with the protrusion. In the embodiment, the second connection part P2-C may include the 3-1 sub-part 31 of the 1-1 preliminary connection electrode layer L1a-CI and the 4-1 sub-part 41 of the 2-1 preliminary connection electrode layer L2a-CI.

[0221] According to this embodiment, in the step of forming the 1-1 preliminary connection electrode layer L1a-CI, the 1-1 dummy electrode layer L1a-D may be formed together. In the step of forming the 1-1 preliminary connection electrode layer L1a-CI, the first conductive material may not be deposited near the end of the lower side (i.e., the bottom) of the contact hole CNT, and the first conductive material deposited near the bottom surface of the contact hole CNT may be formed as the 1-1 dummy electrode layer L1a-D separated from the 1-1 preliminary connection electrode layer L1a-CI.

[0222] The 1-1 dummy electrode layer L1a-D may include the same material as that of the 1-1 preliminary connection electrode layer L1a-CI. The 1-1 dummy electrode layer L1a-D may be directly disposed on the second auxiliary part P2-A.

[0223] According to this embodiment, in the step of forming the 2-1 preliminary connection electrode layer L2a-CI, the 2-1 dummy electrode layer L2a-D can be formed together. In the step of forming the 2-1 preliminary connection electrode layer L2a-CI, the second conductive material may not be deposited near the end portion on the lower side (i.e., the bottom) of the contact hole CNT, and the second conductive material deposited near the bottom surface of the contact hole CNT can be formed as the 2-1 dummy electrode layer L2a-D separated from the 2-1 preliminary connection electrode layer L2a-CI.

[0224] The 2-1 dummy electrode layer L2a-D can include the same material as that of the 2-1 preliminary connection electrode layer L2a-CI. The 2-1 dummy electrode layer L2a-D can be directly disposed on the 1-1 dummy electrode layer L1a-D.

[0225] Accordingly, in the step of forming the preliminary connection electrode CNE-I, the dummy electrode DME including the 1-1 dummy electrode layer L1a-D and the 2-1 dummy electrode layer L2a-D can be formed together.

[0226] Reference Figure 9D , the method for manufacturing a display device according to this embodiment may further include the step of providing a photoresist pattern PR.

[0227] The photoresist pattern PR can be formed on the preliminary connection electrode CNE-I. The photoresist pattern PR can be formed by forming a photoresist layer on the preliminary connection electrode CNE-I and then subjecting the photoresist layer to patterning using a photomask. Through the patterning process, the photoresist pattern PR overlapping with the contact hole CNT in the plan view can be formed. A part of the photoresist pattern PR can be formed in the contact hole CNT.

[0228] Reference Figure 9D and Figure 9E , the method for manufacturing a display device according to this embodiment may further include the step of etching the preliminary connection electrode CNE-I and the preliminary auxiliary electrode AXE-I. In this embodiment, the step of etching the preliminary connection electrode CNE-I and the step of etching the preliminary auxiliary electrode AXE-I can be performed simultaneously.

[0229] The step of etching the preliminary connection electrode CNE-I and the preliminary auxiliary electrode AXE-I can be performed by a dry etching process using the photoresist pattern PR as a mask.

[0230] Through the step of etching the preliminary connection electrode CNE-I and the preliminary auxiliary electrode AXE-I, the connection electrode CNE can be formed from the preliminary connection electrode CNE-I, and the auxiliary electrode AXE can be formed from the preliminary auxiliary electrode AXE-I.

[0231] A portion of the preliminary connection electrode CNE-I may be exposed from the photoresist pattern PR and may be removed, and the first connection portion P1-C may be formed from the first preliminary connection portion P1-CI. Accordingly, the connection electrode CNE including the first connection portion P1-C and the second connection portion P2-C may be formed.

[0232] In this embodiment, a portion of the 1-1 preliminary sub-portion 11-I of the 1-1 preliminary connection electrode layer L1a-CI and a portion of the 2-1 preliminary sub-portion 21-I of the 2-1 preliminary connection electrode layer L2a-CI may be removed. The 1-1 sub-portion 11 and the 2-1 sub-portion 21 may be formed from the 1-1 preliminary sub-portion 11-I and the 2-1 preliminary sub-portion 21-I, respectively. Accordingly, the 1-1 connection electrode layer L1a-C and the 2-1 connection electrode layer L2a-C may be formed from the 1-1 preliminary connection electrode layer L1a-CI and the 2-1 preliminary connection electrode layer L2a-CI, respectively, and the connection electrode CNE including the 1-1 connection electrode layer L1a-C and the 2-1 connection electrode layer L2a-C may be formed. The first connection portion P1-C may include the 1-1 sub-portion 11 of the 1-1 connection electrode layer L1a-C and the 2-1 sub-portion 21 of the 2-1 connection electrode layer L2a-C.

[0233] A portion of the third preliminary auxiliary portion P3-AI of the preliminary auxiliary electrode AXE-I may be exposed from the photoresist pattern PR and may be removed, and the third auxiliary portion P3-A may be formed from the third preliminary auxiliary portion P3-AI. Accordingly, the auxiliary electrode AXE including the first to third auxiliary portions P1-A, P2-A, and P3-A may be formed. A portion of the upper surface U-I of the insulating layer ISL may be exposed from the auxiliary electrode AXE.

[0234] The outer surface O-C of the connection electrode CNE and the outer surface O-A of the auxiliary electrode AXE may be substantially aligned with each other. The outer surface O-C of the connection electrode CNE may be included in the first connection portion P1-C, and the outer surface O-A of the auxiliary electrode AXE may be included in the third auxiliary portion P3-A.

[0235] In the embodiment, the steps of etching the preliminary connection electrode CNE-I and the preliminary auxiliary electrode AXE-I may be performed by batch etching. That is, by one dry etching process, the connection electrode CNE and the auxiliary electrode AXE may be formed from the preliminary connection electrode CNE-I and the preliminary auxiliary electrode AXE-I, respectively.

[0236] Reference Figure 9E and Figure 9F, the method for manufacturing a display device according to this embodiment may further include the step of removing the photoresist pattern PR. By Figures 9A to 9F The connection electrode CNE, the auxiliary electrode AXE, and the dummy electrode DME formed by the step of Figure 7 may correspond to the connection electrode CNE, the auxiliary electrode AXE, and the dummy electrode DME described above with reference to

[0237] In this embodiment, the connection electrode CNE may be electrically connected to the semiconductor pattern SP through the auxiliary electrode AXE. The auxiliary electrode AXE according to this embodiment may be provided in the form of a thin film and may be formed by a deposition process capable of providing excellent step coverage characteristics. Therefore, even if the connection electrode CNE is formed in a shape that is disconnected from the semiconductor pattern SP in the contact hole CNT, the connection electrode CNE can be electrically connected to the semiconductor pattern SP through the auxiliary electrode AXE. Accordingly, even if a shadow effect occurs due to protrusion in the process of forming the connection electrode CNE, the connection electrode CNE can be stably connected to the semiconductor pattern SP through the auxiliary electrode AXE.

[0238] Figures 10A to 10F is a cross-sectional view showing some of the steps of the method for manufacturing a display device according to an embodiment of the present disclosure.

[0239] Referring to Figure 10A and Figure 10B , the method for manufacturing a display device according to this embodiment may include an etching step of the preliminary auxiliary electrode AXE’-I before the step of forming the preliminary connection electrode CNE’-I (refer to Figure 10C ) and after the step of forming the preliminary auxiliary electrode AXE’-I.

[0240] The step of etching the preliminary auxiliary electrode AXE’-I may be performed by a blanket anisotropic etching process. That is, according to this embodiment, a mask such as a photoresist pattern may not be used in the step of etching the preliminary auxiliary electrode AXE’-I. The blanket anisotropic etching process of the preliminary auxiliary electrode AXE’-I may be performed by a dry etching process. In an embodiment, the dry etching process of the preliminary auxiliary electrode AXE’-I may be performed by a plasma etching process. In an embodiment, for example, the dry etching process of the preliminary auxiliary electrode AXE’-I may be performed by an inductively coupled plasma (“ICP”) etching process.

[0241] In the step of etching the preliminary auxiliary electrode AXE'-I, the portion of the preliminary auxiliary electrode AXE'-I disposed on the upper surface U-I of the insulating layer ISL and the portion of the preliminary auxiliary electrode AXE'-I disposed on the upper surface U-S of the semiconductor pattern SP exposed from the insulating layer ISL can be removed, and the portion of the preliminary auxiliary electrode AXE'-I covering the inner surface S-I of the defined contact hole CNT of the insulating layer ISL and extending in a substantially vertical direction along the inner surface S-I of the insulating layer ISL can be retained. Accordingly, the auxiliary electrode AXE' can be formed from the preliminary auxiliary electrode AXE'-I.

[0242] The auxiliary electrode AXE' according to this embodiment can be provided in the form of a thin film that only covers the inner surface S-I of the insulating layer ISL (or the sidewall of the contact hole CNT). Meanwhile, in this embodiment, the upper surface U-S of the semiconductor pattern SP can be exposed from the auxiliary electrode AXE'.

[0243] Reference Figure 10C , the method for manufacturing a display device according to this embodiment can further include the step of forming a preliminary connection electrode CNE'-I. The preliminary connection electrode CNE'-I can be formed on the insulating layer ISL and the auxiliary electrode AXE'.

[0244] In this embodiment, the step of forming the preliminary connection electrode CNE'-I can include the step of forming a lower preliminary connection electrode layer LL-CI (or a lower conductive layer), the step of forming a first-second preliminary connection electrode layer L1b-CI (or a first-second conductive layer), and the step of forming a second-second preliminary connection electrode layer L2b-CI (or a second-second conductive layer). The lower preliminary connection electrode layer LL-CI can be formed on the insulating layer ISL and the auxiliary electrode AXE', the first-second preliminary connection electrode layer L1b-CI can be formed on the lower preliminary connection electrode layer LL-CI, and the second-second preliminary connection electrode layer L2b-CI can be formed on the first-second preliminary connection electrode layer L1b-CI.

[0245] The step of forming the first-second preliminary connection electrode layer L1b-CI can be performed by a deposition process of a first conductive material, and the step of forming the lower preliminary connection electrode layer LL-CI and the step of forming the second-second preliminary connection electrode layer L2b-CI can be performed by a deposition process of a second conductive material. The first conductive material and the second conductive material can include different materials. In an embodiment, for example, the first conductive material can include aluminum, and the second conductive material can include titanium. In an embodiment, both the deposition process of the first conductive material and the deposition process of the second conductive material can be performed by a sputtering process.

[0246] The preliminary connection electrode CNE’-I may include a first preliminary connection part P1-CI’ and a second connection part P2-C’. The first preliminary connection part P1-CI’ may cover the entire upper surface U-I of the insulating layer ISL. A part of the first preliminary connection part P1-CI’ may be formed to overlap with a part of the contact hole CNT in a plan view. That is, the preliminary connection electrode CNE’-I may protrude. In this embodiment, the first preliminary connection part P1-CI’ may include a part of the lower preliminary connection electrode layer LL-CI disposed on the insulating layer ISL (hereinafter, referred to as the first lower preliminary sub-part B1-I), a part of the 1-2 preliminary connection electrode layer L1b-CI disposed on the insulating layer ISL (hereinafter, referred to as the 1-2 preliminary sub-part 12-I), and a part of the 2-2 preliminary connection electrode layer L2b-CI disposed on the insulating layer ISL (hereinafter, referred to as the 2-2 preliminary sub-part 22-I).

[0247] The second connection part P2-C’ may be a part formed in the contact hole CNT. Due to the protrusion of the preliminary connection electrode CNE’-I, a shadow effect may occur. Accordingly, the first conductive material and the second conductive material may not be deposited near the end of the lower side (i.e., the bottom) of the contact hole CNT. The second connection part P2-C’ may only cover a part of the auxiliary electrode AXE’. In this embodiment, the second connection part P2-C’ may include a second lower sub-part B2 of the lower preliminary connection electrode layer LL-CI, a 3-2 sub-part 32 of the 1-2 preliminary connection electrode layer L1b-CI, and a 4-2 sub-part 42 of the 2-2 preliminary connection electrode layer L2b-CI.

[0248] According to this embodiment, in the step of forming the lower preliminary connection electrode layer LL-CI, a lower dummy electrode layer LL-D separated from the lower preliminary connection electrode layer LL-CI may be formed together. The lower dummy electrode layer LL-D may include the same material as that of the lower preliminary connection electrode layer LL-CI. The lower dummy electrode layer LL-D may be directly disposed on the exposed upper surface U-S of the semiconductor pattern SP.

[0249] In the step of forming the 1-2 preliminary connection electrode layer L1b-CI, a 1-2 dummy electrode layer L1b-D separated from the 1-2 preliminary connection electrode layer L1b-CI may be formed together. The 1-2 dummy electrode layer L1b-D may include the same material as that of the 1-2 preliminary connection electrode layer L1b-CI. The 1-2 dummy electrode layer L1b-D may be directly disposed on the lower dummy electrode layer LL-D.

[0250] In the step of forming the second - second preliminary connection electrode layer L2b - CI, a second - second dummy electrode layer L2b - D separated from the second - second preliminary connection electrode layer L2b - CI can be formed together. The second - second dummy electrode layer L2b - D can include the same material as that of the second - second preliminary connection electrode layer L2b - CI. The second - second dummy electrode layer L2b - D can be directly disposed on the first - second dummy electrode layer L1b - D.

[0251] Accordingly, in the step of forming the preliminary connection electrode CNE’ - I, a dummy electrode DME’ including a lower dummy electrode layer LL - D, the first - second dummy electrode layer L1b - D, and the second - second dummy electrode layer L2b - D can be formed together.

[0252] Reference Figure 10D , the method for manufacturing a display device according to this embodiment can further include the step of providing a photoresist pattern PR. The description given above with reference to Figure 9D can be equally applied to the step of providing the photoresist pattern PR.

[0253] Reference Figure 10E and Figure 10F , the method for manufacturing a display device according to this embodiment can further include the step of etching the preliminary connection electrode CNE’ - I. In this embodiment, the step of etching the preliminary connection electrode CNE’ - I can be performed after forming the auxiliary electrode AXE’.

[0254] The step of etching the preliminary connection electrode CNE’ - I can be performed by a dry etching process using the photoresist pattern PR as a mask.

[0255] By the step of etching the preliminary connection electrode CNE’ - I, the connection electrode CNE’ can be formed from the preliminary connection electrode CNE’ - I. A part of the preliminary connection electrode CNE’ - I can be exposed from the photoresist pattern PR and can be removed, and the first connection part P1 - C’ can be formed from the first preliminary connection part P1 - CI’. Accordingly, the connection electrode CNE’ including the first connection part P1 - C’ and the second connection part P2 - C’ can be formed.

[0256] In this embodiment, the first lower preliminary sub - part B1 - I of the lower preliminary connection electrode layer LL - CI, the 1 - 2 preliminary sub - part 12 - I of the 1 - 2 preliminary connection electrode layer L1b - CI, and the 2 - 2 preliminary sub - part 22 - I of the 2 - 2 preliminary connection electrode layer L2b - CI can be partially removed. The first lower sub - part B1, the 1 - 2 sub - part 12, and the 2 - 2 sub - part 22 can be formed by the first lower preliminary sub - part B1 - I, the 1 - 2 preliminary sub - part 12 - I, and the 2 - 2 preliminary sub - part 22 - I respectively. Correspondingly, the lower connection electrode layer LL - C, the 1 - 2 connection electrode layer L1b - C, and the 2 - 2 connection electrode layer L2b - C can be formed by the lower preliminary connection electrode layer LL - CI, the 1 - 2 preliminary connection electrode layer L1b - CI, and the 2 - 2 preliminary connection electrode layer L2b - CI respectively. Correspondingly, the connection electrode CNE' including the lower connection electrode layer LL - C, the 1 - 2 connection electrode layer L1b - C, and the 2 - 2 connection electrode layer L2b - C can be formed. The first connection part P1 - C' can include the first lower sub - part B1 of the lower connection electrode layer LL - C, the 1 - 2 sub - part 12 of the 1 - 2 connection electrode layer L1b - C, and the 2 - 2 sub - part 22 of the 2 - 2 connection electrode layer L2b - C.

[0257] Reference Figure 10E and Figure 10F , the method for manufacturing a display device according to this embodiment can further include the step of removing the photoresist pattern PR. The connection electrode CNE', the auxiliary electrode AXE', and the dummy electrode DME' formed by Figures 10A to 10F the steps can correspond to the connection electrode CNE', the auxiliary electrode AXE', and the dummy electrode DME' described above with reference to Figure 8 .

[0258] In this embodiment, the connection electrode CNE' can be electrically connected to the semiconductor pattern SP through the auxiliary electrode AXE' and the dummy electrode DME'. The auxiliary electrode AXE' according to this embodiment can be provided in the form of a thin film and can be formed by a deposition process capable of providing excellent step coverage characteristics. Correspondingly, the auxiliary electrode AXE' can include a part in contact with both the connection electrode CNE' and the dummy electrode DME'. Even if the connection electrode CNE' is formed in a shape that is disconnected from the semiconductor pattern SP in the contact hole CNT, the connection electrode CNE' can be electrically connected to the semiconductor pattern SP through the auxiliary electrode AXE'. Correspondingly, even if a shadow effect occurs due to protrusion during the process of forming the connection electrode CNE, the connection electrode CNE' can be stably connected to the semiconductor pattern SP through the auxiliary electrode AXE.

[0259] According to the present disclosure, in a display device and a method for manufacturing a display device, an auxiliary electrode may be provided on a sidewall of a contact hole. Accordingly, connection defects between electrodes may be prevented or reduced.

[0260] In addition, in a display device and a method for manufacturing a display device according to the present disclosure, a connection electrode may be stably connected to a semiconductor pattern. Accordingly, stable electrical characteristics may be ensured.

[0261] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display device, comprising: A circuit layer; And A light-emitting element disposed on the circuit layer, Wherein, the circuit layer includes: A semiconductor pattern; An insulating layer in which a contact hole is defined to expose a part of the semiconductor pattern; A connection electrode disposed on the insulating layer and partially disposed in the contact hole; and An auxiliary electrode at least partially disposed in the contact hole and in contact with the connection electrode and the semiconductor pattern, and Wherein, in a plan view, the connection electrode does not overlap with a part of the contact hole.

2. The display device according to claim 1, wherein, The auxiliary electrode includes: A first auxiliary portion in contact with an inner surface of the insulating layer defining the contact hole and covering the entire inner surface of the insulating layer; A second auxiliary portion in contact with the exposed part of the semiconductor pattern from the insulating layer and covering the entire part of the semiconductor pattern; and A third auxiliary portion in contact with a part of an upper surface of the insulating layer.

3. The display device according to claim 2, wherein, The connection electrode includes: A first connection portion in contact with the third auxiliary portion; and A second connection portion extending downward from the first connection portion and in contact with the first auxiliary portion.

4. The display device according to claim 3, wherein, An outer surface of the auxiliary electrode and an outer surface of the connection electrode are aligned with each other, Wherein, the outer surface of the auxiliary electrode is included in the third auxiliary portion, and Wherein, the outer surface of the connection electrode is included in the first connection portion.

5. The display device according to claim 2, wherein, The connection electrode includes: A 1-1 connection electrode layer disposed on the auxiliary electrode; and A 2-1 connection electrode layer disposed on the 1-1 connection electrode layer.

6. The display device according to claim 5, further comprising: A dummy electrode disposed on the second auxiliary portion and in the contact hole, Wherein, the dummy electrode includes: A 1-1 dummy electrode layer spaced apart from the 1-1 connection electrode layer; and A 2-1 dummy electrode layer disposed on the 1-1 dummy electrode layer and spaced apart from the 2-1 connection electrode layer.

7. The display device according to claim 1, wherein, All of the auxiliary electrode is disposed in the contact hole and covers the entire inner surface of the insulating layer defining the contact hole, and Wherein, the semiconductor pattern includes a part exposed from the auxiliary electrode.

8. The display device according to claim 7, wherein, The connection electrode includes: A lower connection electrode layer in contact with an upper surface of the insulating layer; A 1-2 connection electrode layer disposed on the lower connection electrode layer; and A 2-2 connection electrode layer disposed on the 1-2 connection electrode layer.

9. The display device according to claim 8, further comprising: A dummy electrode disposed on an upper surface of the semiconductor pattern and in the contact hole, Wherein, an edge of the dummy electrode is in contact with the auxiliary electrode.

10. The display device according to claim 9, wherein The dummy electrode includes: A lower dummy electrode layer in contact with the upper surface of the semiconductor pattern and spaced apart from the lower connection electrode layer; A 1-2 dummy electrode layer disposed on the lower dummy electrode layer and spaced apart from the 1-2 connection electrode layer; and The second dummy electrode layer is disposed on the first dummy electrode layer and spaced apart from the second connection electrode layer.

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