Signal processing system of Beidou base station receiver

Abstract

The utility model discloses a signal processing system of a Beidou base station receiver. The signal processing system comprises a main control board, a GNSS OEM board, a man-machine interface module, and a wireless transmission module, a radio frequency front end, a signal processing unit and a power supply management module which are arranged on the main control board. The radio frequency front end is connected with an external antenna, the output end of the radio frequency front end is connected with the signal processing unit, and the signal processing unit is further connected with the GNSS OEM board, the wireless transmission module and the human-computer interface module through interfaces. The system has the advantages that the accuracy of a positioning result is improved by reducing the noise characteristic of a received signal through the radio frequency front end, so that the positioning is more accurate; through cooperation of a radio frequency front end, an SNB1008 chip, an FPGA chip, a DSP chip and a processor, detection, identification, processing and comparison are respectively carried out on collected Beidou, GPS and GLONASS satellite signals. Hardware on the signal processing system can be controlled through software application, software and hardware combination is achieved, and various preset functions are achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of signal processing, in particular to a signal processing system for a Beidou reference station receiver. Background Art

[0002] In recent years, the Ministry of Transport has successfully promoted the use of the Beidou system in various sectors, including road, aviation, maritime, inland waterways, and postal services. However, this system's application has been characterized by an overreliance on GPS, with signals and equipment primarily utilizing a dual-mode Beidou / GPS system. While this model has its objective and practical reasons, it is detrimental to the independent development of the Beidou system.

[0003] At present, most of the base station receivers used in the Beidou high-precision service infrastructure on the market are designed to be GNSS multi-mode compatible and do not have the function of receiving signals from satellite navigation systems other than Beidou satellite signals. Utility Model Content

[0004] The technical problem to be solved by the utility model is that the existing receiver does not have the function of receiving other satellite navigation system signals except Beidou satellite signals.

[0005] The technical solutions adopted are:

[0006] A signal processing system for a BeiDou reference station receiver, comprising a main control board, a GNSS OEM board, a human-machine interface module, and a wireless transmission module, a radio frequency front end, a signal processing unit, and a power management module arranged on the main control board;

[0007] The power management module is used to provide power support for the entire signal processing system to ensure the smooth operation of the signal processing system;

[0008] A radio frequency front end and a signal processing unit, wherein the input end of the radio frequency front end is connected to the external antenna, and the output end of the radio frequency front end is connected to the signal processing unit;

[0009] The signal processing unit is interconnected with the GNSS OEM board, the wireless transmission module, and the human-machine interface module through interfaces.

[0010] In a further preferred embodiment of the technical solution of the present utility model, the RF front end includes a filter, an LNA, two first AMPs, a second AMP, two LPFs, two VGAs, two ADCs, an oscillator, a PLL and a time driver;

[0011] The input end of the filter is connected to the external antenna, the output end of the filter is connected to the input end of the LNA, the output end of the LNA is mixed with the output end of the second AMP, and the mixed signal is divided into two signals, which are respectively input into two first AMPs, the output ends of the two first AMPs are respectively connected to the input end of an LPF, the output end of an LPF is connected to the input end of a VGA, the output end of a VGA is connected to the input end of an ADC, and the output ends of the two ADCs are respectively connected to the signal processing unit;

[0012] The input end of the second AMP is connected to the oscillator, the output end of the second AMP is also connected to the input end of the PLL, the output end of the PLL is connected to the input end of the time driver, and the output end of the time driver is connected to the signal processing unit.

[0013] In a further preferred embodiment of the technical solution of the present invention, the signal processing unit includes an SNB1008 chip, an FPGA chip, a DSP chip and a processor. The SNB1008 chip is connected to the output ends of two ADCs and is used to process Beidou, GPS, and GLONASS signals. The SNB1008 chip is connected to the FPGA chip, and the DSP chip is respectively connected to the FPGA chip, the output end of the time driver, and the processor. The processor is also respectively interconnected with the GNSS OEM board, the human-machine interface module, and the wireless transmission module.

[0014] In a further optimization of the technical solution of the utility model, the processor adopts an ARM9 chip, and the ARM9 chip is also externally connected with a DDR2 and a NANDFLASH.

[0015] In a further embodiment of the technical solution of the present invention, the signal processing system further includes an external real-time clock module, which is connected to the power management module and the processor respectively for time synchronization.

[0016] In a further embodiment of the technical solution of the present invention, the signal processing system further includes a watchdog timer, which is connected to the power management module and the processor respectively, and is used to monitor whether the signal processing system is operating normally.

[0017] In a further embodiment of the technical solution of the present invention, the signal processing system also includes an interrupt controller, which is connected to the processor and the power management module respectively, and is used to provide routing and control of internal interrupt sources and external interrupt sources to processor interrupts for the entire signal processing system.

[0018] In a further embodiment of the technical solution of the present invention, the signal processing system further includes an external storage module, which is connected to the power management module and the processor respectively. The external storage module includes a memory controller, a read-only memory, a static random access memory, and an embedded FLASH.

[0019] In a further preferred embodiment of the technical solution of the present invention, the signal processing system further includes a CPLD, and the CPLD is interconnected with the processor and multiple modules on the signal processing system respectively.

[0020] In a further optimization of the technical solution of the present utility model, the signal processing system adopts an AMBA bus connection method.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The utility model reduces the noise characteristics of the received signal through the radio frequency front end, thereby increasing the accuracy of the positioning result and making the positioning more accurate.

[0023] 2. The utility model realizes detection, identification, processing and comparison of collected Beidou, GPS and GLONASS satellite signals respectively through the cooperation of RF front end, SNB1008 chip, FPGA chip, DSP chip and processor.

[0024] 3. The present invention can control the hardware on the signal processing system through software application, realize the combination of software and hardware, and achieve various predetermined functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a partial structural diagram of the main control board of the signal processing system of this embodiment. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. Example

[0027] A signal processing system for a Beidou reference station receiver in this embodiment includes a main control board, a GNSS OEM board, a human-machine interface module, and a wireless transmission module, a radio frequency front end, a signal processing unit, a power management module, an external real-time clock module, a watchdog timer, an interrupt controller, and an external storage module arranged on the main control board.

[0028] The signal processing unit is interconnected with the GNSS OEM board, wireless transmission module, human-machine interface module, power management module, external real-time clock module, watchdog timer, interrupt controller and external storage module through interfaces to ensure the smooth operation of the entire signal processing system.

[0029] The interface includes a UART module, an SPI module, a GPIO module, an EBI module, an SDIO module, a serial port module, and a USB module. The UART module, the SPI module, the GPIO module, the EBI module, the SDIO module, the serial port module, and the USB module are all arranged on the main control board.

[0030] The UART module is used to connect the processor to an external PC. The external PC is connected to the UART module through an RS-232 level conversion module to ensure level compatibility, making it easier for the external PC to debug the processor through the UART module. At the same time, the processor outputs processing results to the external PC through the UART module.

[0031] The RS-232 level conversion module is arranged on the main control board and is connected to the processor and the power management module respectively.

[0032] GPIO is used to control the input or output of the IO pin.

[0033] The RF front end and signal processing unit, the input end of the RF front end is connected to the external antenna, receives different satellite signals and performs preliminary processing on the signals, and the output end of the RF front end is connected to the signal processing unit to transmit the preliminary processed signals to the signal processing unit for further processing;

[0034] In this embodiment, Figure 1 As shown, the RF front end includes a filter, an LNA, two first AMPs, a second AMP, two LPFs, two VGAs, two ADCs, an oscillator, a PLL and a time driver;

[0035] The input end of the filter is connected to the external antenna, the output end of the filter is connected to the input end of the LNA, the output end of the LNA is mixed with the output end of the second AMP, and the mixed signal is divided into two signals, which are respectively input into two first AMPs, the output ends of the two first AMPs are respectively connected to the input end of an LPF, the output end of an LPF is connected to the input end of a VGA, the output end of a VGA is connected to the input end of an ADC, and the output ends of the two ADCs are respectively connected to the signal processing unit;

[0036] The input end of the second AMP is connected to the oscillator, the output end of the second AMP is also connected to the input end of the PLL, the output end of the PLL is connected to the input end of the time driver, and the output end of the time driver is connected to the signal processing unit.

[0037] The signal processing unit includes an SNB1008 chip, an FPGA chip, a DSP chip and a processor.

[0038] In the RF front end, the signal flows as follows: the external antenna receives the signal, which is a spread spectrum modulated signal. The signal is input into the filter by the external antenna, filtered, and then output to the LNA for amplification and noise reduction.

[0039] At this time, the local oscillator signal generated by the oscillator is amplified and output by the second AMP. The signal output by the second AMP is divided into two paths, one of which is input into the frequency synthesizer. The frequency synthesizer controls the frequency of the signal. The signal output by the frequency synthesizer is multiplied by the signal output by the LNA to achieve down-conversion, and the high-frequency signal is reduced to an intermediate frequency signal, which is convenient for discrete sampling. The signal after the frequency reduction is divided into two paths and output to the first AMP for amplification, and then respectively input into the corresponding LPF. The signal after the frequency reduction is further filtered. The signals output by the two LPFs are respectively input into the corresponding VGA for gain. The signals after the gain output by the VGA are respectively input into the corresponding ADC for analog-to-digital conversion. The ADC can output in-phase and quadrature circuit sampling data, and can choose 1 or 2-bit I / Q sampling, or can choose to output up to 3-bit I-channel output. The output level can be set to conventional CMOS level or differential level output. The two ADCs are connected to the SNB1008 chip respectively. The SNB1008 chip inputs the ADC digital signal into the SNB1008 chip to process the Beidou, GPS, and GLONASS signals, and converts the signal received by the RF front end into a digital signal for subsequent processing.

[0040] The SNB1008 chip's method for processing BeiDou, GPS, and GLONASS signals is an existing technology.

[0041] Another signal output by the second AMP is input into the PLL to generate a new frequency output to the time driver. The time driver is connected to the DSP chip to ensure that the entire signal processing system has an accurate and synchronized clock signal.

[0042] The SNB1008 chip is connected to the FPGA chip through the SPI interface module. The FPGA chip provides a sampling clock for the SNB1008 chip. At the same time, the SNB1008 chip is configured through the FPGA chip to filter the digital signals received from the SNB1008 chip in real time and convert the digital signals obtained from the SNB1008 chip into a format suitable for DSP chip processing.

[0043] The parallel processing capability of FPGA chips enables them to perform multiple signal processing tasks simultaneously, improving overall speed.

[0044] The FPGA chip is connected to the DSP chip through a serial interface module. The FPGA chip transfers the complex signal processing tasks to the DSP chip for processing. At the same time, the DSP chip extracts features, decodes, and demodulates the digital signals pre-processed by the FPGA chip.

[0045] The FPGA chip transfers complex signal processing tasks to the DSP chip for processing, which can effectively reduce the power consumption of the entire signal processing system and speed up the efficiency of signal processing.

[0046] The DSP chip is connected to the processor through a USB module. The processor also communicates and exchanges information with the GNSS OEM board, wireless transmission module, human-machine interface module, power management module, external real-time clock module, watchdog timer, interrupt controller and external storage module through interfaces. The processor receives data and signals processed by the DSP chip and stores them in the external storage module. Combined with the external data collected by the wireless transmission module, the processor solves and locates the data and signals processed by the DSP chip and displays them on the corresponding human-machine interface module.

[0047] In this embodiment, the method for processing digital signals by the FPGA chip, DSP chip and processor is the existing technology.

[0048] The power management module includes a power supply, a power switch and a control unit. The power supply is connected to the power switch, and the power switch manages the power supply.

[0049] The power supply, the power switch and the control unit are connected to each other.

[0050] The power switch uses FDS4935A to manage the battery-powered switch.

[0051] The power supply is connected to the GNSS OEM board, human-machine interface module, wireless transmission module, external real-time clock module, watchdog timer, interrupt controller, external storage module, CPLD and processor through the control unit and power lines to control and supply power to them.

[0052] The input of the GNSS OEM board uses a feedthrough capacitor to isolate the noise from the power line crosstalk, thereby preventing it from affecting the performance of the entire signal processing system.

[0053] The human-machine interface module includes a display screen, a buzzer and buttons; the processor is connected to the display screen, the buzzer and the buttons through the SPI interface respectively.

[0054] The wireless transmission module includes a radio unit, a Bluetooth unit, a WiFi unit, a 3G unit, and a 4G unit. In this embodiment, the radio unit and the Bluetooth unit are connected to the processor through a serial port module, respectively. The WiFi unit and the 4G unit are connected to the processor through an SDIO interface module. The 3G unit is interconnected with the processor through a USB interface, thereby realizing communication between the wireless transmission module and the processor, making it easier for the processor to obtain relevant external environment information.

[0055] In this embodiment, the processor adopts an ARM9 chip, and the ARM9 chip is connected to a DDR2 and a NANDFLASH respectively through an EBI interface module.

[0056] NANDFLASH is mainly used for memory storage.

[0057] The interrupt controller provides routing and control of internal and external interrupt sources to the processor for the signal processing system.

[0058] The signal processing system can also be reset by hardware. External debugging tools can reset the processor's JTAG interface through the processor's nRESET pin. This signal processing system accepts external reset signals to reset the processor, interrupt controller, external real-time clock and watchdog timer. The watchdog timer can also generate a reset signal to reset the processor and interrupt controller.

[0059] The watchdog timer is used to monitor whether the signal processing system is operating normally.

[0060] The external storage module includes a memory controller, a read-only memory, a static random access memory, and an embedded FLASH. The storage controller is connected to the read-only memory, the static random access memory, and the embedded FLASH respectively. The read-only memory and the embedded FLASH are used for data and code storage, and the static random access memory is used for data cache and code execution.

[0061] The CPLD is interconnected with multiple modules on the processor and signal processing system respectively, and is used to flexibly manage the communication between various devices on the main control board, serial port data switching and power control according to the needs of the processor.

[0062] The external real-time clock module is connected to the power management module and the processor respectively for time synchronization.

[0063] The signal processing system uses the AMBA bus connection method. The AHB bus connects the processor and the memory controller to ensure efficient transmission between the processor and the memory controller. The APB bus is used to connect the low-power circuits in the signal processing system.

[0064] In this embodiment, the input clock frequency of the signal processing system is 48 MHz. The input is directly used as the input clock of the processor and also as the clock of the AHB bus. The clock obtained by dividing the input clock by 2 is used as the APB bus clock. The APB bus clock is set as the input clock of the UART module. The clocks of the external real-time clock and the watchdog timer are obtained by dividing the external 32.768 kHz clock.

[0065] The above embodiments are only for illustrating the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A signal processing system for a BeiDou reference station receiver, characterized in that: The signal processing system includes a main control board, a GNSS OEM board, a human-machine interface module, and a wireless transmission module, a radio frequency front end, a signal processing unit, and a power management module arranged on the main control board; The power management module is used to provide power support for the entire signal processing system to ensure the smooth operation of the signal processing system; A radio frequency front end and a signal processing unit, wherein the input end of the radio frequency front end is connected to the external antenna, and the output end of the radio frequency front end is connected to the signal processing unit; The signal processing unit is interconnected with the GNSS OEM board, the wireless transmission module, and the human-machine interface module through interfaces.

2. The signal processing system for a BeiDou reference station receiver according to claim 1, wherein: The RF front end includes filters, LNA, two first AMPs, second AMP, two LPFs, two VGAs, two ADCs, oscillators, PLLs, and time drivers; The input end of the filter is connected to the external antenna, the output end of the filter is connected to the input end of the LNA, the output end of the LNA is mixed with the output end of the second AMP, and the mixed signal is divided into two signals, which are respectively input into two first AMPs, the output ends of the two first AMPs are respectively connected to the input end of an LPF, the output end of an LPF is connected to the input end of a VGA, the output end of a VGA is connected to the input end of an ADC, and the output ends of the two ADCs are respectively connected to the signal processing unit; The input end of the second AMP is connected to the oscillator, the output end of the second AMP is also connected to the input end of the PLL, the output end of the PLL is connected to the input end of the time driver, and the output end of the time driver is connected to the signal processing unit.

3. The signal processing system for a BeiDou reference station receiver according to claim 2, wherein: The signal processing unit includes an SNB1008 chip, an FPGA chip, a DSP chip, and a processor. The SNB1008 chip is connected to the output ends of two ADCs and is used to process Beidou, GPS, and GLONASS signals. The SNB1008 chip is connected to the FPGA chip. The DSP chip is connected to the FPGA chip, the output end of the time driver, and the processor respectively. The processor is also interconnected with the GNSS OEM board, the human-machine interface module, and the wireless transmission module.

4. The signal processing system for a BeiDou reference station receiver according to claim 3, wherein: The processor uses an ARM9 chip, which also has an external DDR2 and a NANDFLASH.

5. The signal processing system for a BeiDou reference station receiver according to claim 4, wherein: The signal processing system further comprises an external real-time clock module, which is connected to the power management module and the processor respectively.

6. The signal processing system for a BeiDou reference station receiver according to claim 4, wherein: The signal processing system further comprises a watchdog timer, which is connected to the power management module and the processor respectively.

7. The signal processing system for a BeiDou reference station receiver according to claim 4, wherein: The signal processing system further comprises an interrupt controller, which is connected to the processor and the power management module respectively.

8. A signal processing system for a BeiDou reference station receiver according to claim 4, characterized in that: The signal processing system further comprises an external storage module, which is connected to the power management module and the processor respectively. The external storage module comprises a memory controller, a read-only memory, a static random access memory, and an embedded FLASH.

9. A signal processing system for a BeiDou reference station receiver according to claim 4, characterized in that: The signal processing system further comprises a CPLD, which is interconnected with the processor and multiple modules on the signal processing system respectively.

10. The signal processing system for a BeiDou reference station receiver according to claim 4, wherein: The signal processing system adopts the connection mode of AMBA bus.

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