Clock domain crossing synchronization circuit and electronic system

Abstract

The utility model relates to a clock domain crossing synchronization circuit and an electronic system. Clock domain crossing synchronization circuits and methods include generating a destination domain current buffer signal in a destination clock domain. The destination region current buffer signal indicates either the first data buffer or the second data buffer in the source clock domain as a current buffer used during a current data transfer period. The destination domain current buffer signal is synchronized and a source domain current buffer signal indicative of the current buffer is generated. A source data transfer request signal is generated based on the synchronized source domain current buffer signal and the source data transfer request signal to generate a destination domain data transfer request signal. When the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal, transfer of data between memories in the destination clock domain is delayed to a subsequent data transfer cycle.

Description

Technical Field

[0001] The present disclosure relates generally to synchronization of data signals in a system having multiple clock domains, and more particularly to clock domain crossing circuits and methods that ensure correct data signal order when transferring data signals across clock domains. Background Art

[0002] In some electronic environments, data must be transferred between two different clock domains, which will be referred to herein as the destination clock domain and the source clock domain. Each clock domain corresponds to a collection of components or circuits driven by the same clock signal or a set of related clock signals (e.g., a set of clock signals derived from the same source or root clock signal). Clock domain crossings, where data signals must be transferred between the source and destination clock domains, can lead to metastability, data loss, and data consistency issues.

[0003] A clock domain crossing circuit system for synchronizing data signals between a source clock domain and a destination clock domain may include a double buffer in the source clock domain to increase the bandwidth of the interface provided by the clock domain crossing circuit system. In this case, the destination clock domain must be able to determine the correct one of the double buffers to transfer data to or from to ensure data consistency and to ensure that data transfer requests from the source clock domain are not missed in the destination clock domain. Although conventional clock domain crossing circuit systems include synchronization circuit systems for synchronizing data transfer requests (i.e., read and write requests) generated in the source clock domain and associated with one of the double buffers, these conventional synchronization circuits may not be able to correctly order (i.e., preserve the order) the data transfer requests in the destination clock domain. This can result in the use of the wrong one of the double buffers (i.e., data inconsistency) or the complete loss of data transfer requests from the source clock domain (data loss). Thus, improved clock domain crossing circuits and methods are needed for such electronic environments. Utility Model Content

[0004] The present disclosure provides a clock domain crossing synchronization circuit, comprising: a destination current buffer generator in a destination clock domain, the destination current buffer generator being configured to generate a destination domain current buffer signal, the destination domain current buffer signal having a value indicating whether a first data buffer or a second data buffer is a current buffer to be used in a current data transfer cycle; a first synchronization circuit being configured to receive the destination current buffer signal and generate a corresponding synchronized destination current buffer signal in a source clock domain; a source current buffer generator being configured to generate a source domain current buffer signal based on the synchronized destination current buffer signal, wherein the source domain current buffer signal has a value indicating a current buffer; a source data transfer request generator being configured to receive the source domain current buffer signal and generate a corresponding synchronized destination current buffer signal based on the source domain current buffer signal; The front buffer signal generates a source data transfer request signal in the source clock domain, and the generated source data transfer request signal is associated with the current buffer indicated by the source domain current buffer signal; a second synchronization circuit is configured to receive the source data transfer request signal and generate a corresponding synchronized source data transfer request signal in the destination clock domain; and a destination data transfer request and delay generator in the destination clock domain is configured to receive the synchronized source data transfer request signal and the destination domain current buffer signal, and the destination data transfer request and delay generator is configured to delay the transfer of data between the memory in the destination clock domain and the current buffer to a subsequent data transfer cycle when the current buffer indicated by the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

[0005] For example, each of the first synchronization circuit and the second synchronization circuit includes a plurality of flip-flops connected in series.

[0006] For example, the synchronous destination domain data transfer request signal includes a write first buffer signal and a write second buffer signal, and wherein the destination data transfer request and delay generator includes: a first pulse generator coupled to receive the write first buffer signal and configured to generate a write first buffer pulse signal in response to the write first buffer signal; a second pulse generator coupled to receive the write second buffer signal and configured to generate a write second buffer pulse signal in response to the write second buffer signal; a first transfer request delay circuit having a first input coupled to receive the destination domain current buffer signal and a second input coupled to receive the write first buffer pulse signal, the first transfer request delay circuit being configured to drive the delayed write first buffer signal to be valid in response to the write first buffer pulse signal becoming valid and the destination domain current buffer signal indicating that the second buffer is the current buffer in the destination clock domain; a second transfer request delay circuit having a first input coupled to receive the destination domain current buffer signal and a second input coupled to receive the write second buffer pulse signal, the second transfer request delay circuit being configured to drive the delayed write first buffer signal to be valid in response to the write second buffer pulse signal becoming valid and the destination domain current buffer signal indicating that the second buffer is the current buffer in the destination clock domain a domain current buffer signal indicating that the first buffer is the current buffer in the destination clock domain and driving the delayed write second buffer signal to be valid; and output logic, coupled to the first pulse generator and the second pulse generator to receive the write first buffer pulse signal and the write second buffer pulse signal, and coupled to the first transfer request delay circuit and the second transfer request delay circuit to receive the delayed write first buffer signal and the delayed write second buffer signal, the output logic being configured to generate a first buffer write request pulse signal in response to the write first buffer pulse signal or the delayed write first buffer signal being valid, and to generate a second buffer write request pulse signal in response to the write second buffer pulse signal or the delayed write second buffer signal being valid; and a selection circuit, coupled to the output logic and having a control input coupled to receive the destination domain current buffer signal, the selection circuit being configured to provide the first buffer write request pulse signal to the memory when the destination domain current buffer signal indicates that the first buffer is the current buffer in the destination clock domain, and to provide the second buffer write request pulse signal to the memory when the destination domain current buffer signal indicates that the second buffer is the current buffer in the destination clock domain.

[0007] For example, each of the first pulse generator and the second pulse generator includes: a trigger having an output terminal and having an input terminal coupled to receive a corresponding one of the write first buffer signal or the write second buffer signal; and an XOR gate having a first input terminal coupled to receive a corresponding one of the write first buffer signal or the write second buffer signal and a second input terminal coupled to the output terminal of the trigger, the XOR gate having an output terminal configured to generate a corresponding write first buffer pulse signal or a write second buffer pulse signal.

[0008] For example, the output logic includes: a first OR gate having a first input terminal coupled to receive a write first buffer pulse signal and a delayed write first buffer signal, and configured to generate a first buffer write request pulse signal at an output terminal; and a second OR gate having a first input terminal coupled to receive a write second buffer pulse signal and a delayed write second buffer signal, and configured to generate a second buffer write request signal at an output terminal.

[0009] For example, the selection circuit includes a multiplexer having a first input coupled to the output of the first OR gate, a second input coupled to the output of the second OR gate, an output coupled to the memory, and a control input coupled to receive the destination domain current buffer signal.

[0010] For example, the destination current buffer generator includes: a trigger having an input terminal and an output terminal; and a multiplexer having a first input terminal coupled to the output terminal of the trigger, a second input terminal receiving the output of the trigger through an inverter, an output terminal coupled to the input terminal of the trigger, and a control input terminal coupled to receive a data transfer request signal from a destination data transfer request and a delay generator.

[0011] For example, the source data transfer request signal includes a first buffer source write request signal and a second buffer source write request signal, and wherein the source data transfer request generator includes: a first trigger, including an input terminal and having an output terminal configured to generate the first buffer source write request signal; a second trigger, including an input terminal and having an output terminal configured to generate the second buffer source write request signal; and a logic circuit system, configured to receive the data transfer current buffer signal and the source domain current buffer signal, and coupled to the input terminals of the first trigger and the second trigger, the logic circuit system is configured to provide a valid signal to the input terminal of the first trigger in response to the data transfer current buffer signal becoming valid and the source domain current buffer signal indicating that the first data buffer is the current buffer, and to provide a valid signal to the input terminal of the second trigger in response to the data transfer current buffer signal becoming valid and the source domain current buffer signal indicating that the second data buffer is the current buffer, and the logic circuit system is also configured to provide an invalid signal on the input terminals of the first trigger and the second trigger in response to the first buffer source data transfer request signal and the second buffer source data transfer request signal becoming valid, respectively.

[0012] For example, the logic circuit system includes: an inverter having an input terminal coupled to receive a source domain current buffer signal and having an output terminal; a first AND gate having a first input terminal coupled to receive a write current buffer signal and a second input terminal coupled to the output terminal of the inverter, and having an output terminal; a first multiplexer having a select input terminal coupled to the output terminal of the first AND gate, a first input terminal coupled to the output terminal of a first flip-flop, a second input terminal, and an output terminal coupled to the input terminal of the first flip-flop; a second inverter having an output terminal coupled to the second input terminal of the first multiplexer and having an output terminal coupled to the first flip-flop to receive an input terminal of a first buffer source write request signal; a second AND gate having a first input terminal coupled to receive a write current buffer signal and a second input terminal coupled to receive a source domain current buffer signal, and having an output terminal; a second multiplexer having a selection input terminal coupled to the output terminal of the second AND gate, a first input terminal coupled to the output terminal of the second flip-flop, a second input terminal, and an output terminal coupled to the input terminal of the second flip-flop; and a third inverter having an output terminal coupled to the second input terminal of the second multiplexer and an input terminal coupled to the output terminal of the second flip-flop to receive the second buffer source write request signal.

[0013] For example, the source domain current buffer generator includes: a first multiplexer having a first input terminal coupled to receive a synchronized destination current buffer signal, a second input terminal, an output terminal, and a control input terminal coupled to receive a start new data transfer signal; a trigger having an input terminal coupled to the output terminal of the first multiplexer and an output terminal on which the source domain current buffer signal is provided; a second multiplexer having a first input terminal coupled to the output terminal of the trigger, a second input terminal, an output terminal coupled to the second input terminal of the first multiplexer, and a control input terminal coupled to receive a write current buffer signal; and an inverter having an input terminal coupled to the output terminal of the trigger and an output terminal coupled to the second input terminal of the second multiplexer.

[0014] The present disclosure provides an electronic system comprising: a first-in-first-out (FIFO) memory in a destination clock domain; a double buffer in a source clock domain, comprising a first data buffer and a second data buffer; and a clock domain crossing synchronization circuit, comprising: a destination current buffer generator in the destination clock domain, the destination current buffer generator being configured to generate a destination domain current buffer signal, the destination domain current buffer signal having a value indicating whether the first data buffer or the second data buffer is a current buffer to be used in a current data transfer cycle; a first synchronization circuit being configured to receive the destination current buffer signal and generate a synchronized destination current buffer signal in the source clock domain; a source current buffer generator in the source clock domain, the source current buffer generator being configured to generate a source domain current buffer signal based on the synchronized destination current buffer signal, wherein the source domain current buffer signal has a first value indicating the first data buffer and a value indicating whether the second data buffer is a current buffer to be used in a current data transfer cycle a second value of the device; a source data transfer request generator, configured to receive the source domain current buffer signal and generate a source data transfer request signal in the source clock domain based on the source domain current buffer signal, the generated source data transfer request signal being associated with one of the first data buffer or the second data buffer corresponding to the value of the source domain current buffer signal; a second synchronization circuit, configured to receive the source data transfer request signal and generate a synchronized destination domain data transfer request signal in the destination clock domain; and a destination data transfer request and delay generator in the destination clock domain, configured to receive the synchronized source data transfer request signal and the destination domain current buffer signal, the destination data transfer request and delay generator being configured to delay the transfer of data between the memory in the destination clock domain and the current buffer to a subsequent data transfer cycle when the current buffer indicated by the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

[0015] For example, the source clock domain is a secure digital clock domain, and wherein the destination clock domain is a high-level hardware bus clock domain.

[0016] According to one embodiment of the present disclosure, a method includes generating a destination-domain current buffer signal in a destination clock domain, the destination-domain current buffer signal having a value indicating which of a first data buffer and a second data buffer in a source clock domain is the current buffer to be used during a current data transfer cycle. The method includes synchronizing the destination-domain current buffer signal in the source clock domain to generate a synchronized destination-domain current buffer signal, and generating a source-domain current buffer signal based on the synchronized destination-domain current buffer signal. The generated source-domain current buffer signal has a value indicating the current buffer. The method also includes generating a source data transfer request signal in the source clock domain based on the source-domain current buffer signal, wherein the source data transfer request signal is associated with the current buffer indicated by the source-domain current buffer signal. The source data transfer request signal is synchronized in the destination clock domain to generate the destination-domain data transfer request signal, and the method includes delaying the transfer of data between FIFO memories in the destination clock domain to a subsequent data transfer cycle when the current buffer associated with the destination-domain data transfer request signal does not correspond to the current buffer indicated by the destination-domain current buffer signal.

[0017] According to another embodiment of the present disclosure, a clock domain crossing synchronization circuit includes a destination current buffer generator in a destination clock domain. The destination current buffer generator is configured to generate a destination domain current buffer signal having a value indicating whether a first data buffer or a second data buffer is a current buffer to be used in a current data transfer cycle. A first synchronization circuit is configured to receive the destination current buffer signal and generate a corresponding synchronized destination current buffer signal in a source clock domain. A source current buffer generator is configured to generate a source domain current buffer signal based on the synchronized destination current buffer signal, wherein the source domain current buffer signal has a value indicating the current buffer. A source data transfer request generator is configured to receive the source domain current buffer signal and generate a source data transfer request signal in the source clock domain based on the source domain current buffer signal. The generated source data transfer request signal is associated with the current buffer indicated by the source domain current buffer signal. A second synchronization circuit is configured to receive the source data transfer request signal and generate a corresponding synchronized destination domain data transfer request signal in the destination clock domain. A destination data transfer request and delay generator in the destination clock domain is configured to receive the synchronized source data transfer request signal and the destination domain current buffer signal. The destination data transfer request and delay generator is configured to delay the transfer of data between the memory in the destination clock domain and the current buffer to a subsequent data transfer cycle when the current buffer indicated by the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

[0018] According to another embodiment of the present disclosure, an electronic system includes a clock domain crossing synchronization circuit, a first-in-first-out (FIFO) memory forming a memory in a destination clock domain, and a double buffer including a first data buffer and a second data buffer in a source clock domain. The source clock domain may be a secure digital (SD) clock domain, and the destination clock domain may be an advanced bus hardware (AHB) bus clock domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1A is a functional block diagram illustrating an example environment of an electronic system in which clock domain crossing synchronous circuits according to embodiments of the present disclosure may be implemented.

[0021] Figure 1B is a diagram illustrating an embodiment according to the present disclosure Figure 1A A more detailed functional block diagram of the electronic system.

[0022] Figure 2 is a signal timing diagram illustrating the loss of correct order of data transfer requests that may occur with conventional clock domain crossing circuitry in the electronic system of FIG. 1 .

[0023] Figure 3 is a functional block diagram of a clock domain crossing synchronization circuit according to an embodiment of the present disclosure.

[0024] Figure 4A and Figure 4B is a more detailed functional block diagram of a write clock domain crossing synchronization circuit according to an embodiment of the present disclosure.

[0025] Figure 5 is a signal timing diagram illustrating the operation of the write clock domain crossing synchronization circuit of FIG. 4 in a first example of delayed write data transfer.

[0026] Figure 6 is a signal timing diagram illustrating operation of the write clock domain crossing synchronization circuit of FIG. 4 in a second example of delayed write data transfer.

[0027] Figure 7A and Figure 7B is a more detailed functional block diagram of a read clock domain crossing synchronization circuit according to an embodiment of the present disclosure.

[0028] Figure 8 is a flowchart illustrating a clock domain crossing synchronization method according to an embodiment of the present disclosure.

[0029] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0030] In the following description, one or more specific details are set forth to provide an understanding of examples of the embodiments. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0031] References to "an embodiment" or "one embodiment" in the framework of this description are intended to indicate that a particular configuration, structure, or feature described in connection with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this description are not necessarily referring to the same embodiment. Furthermore, particular configurations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0032] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0033] An electronic system can be implemented as a system on a chip (SoC), which is an integrated circuit that includes all the necessary components of the system, often including, for example, components associated with different and asynchronous clock domains. Clock domain crossing occurs when data is transferred across clock domains, such as from a flip-flop driven by a source domain clock (source flip-flop) to a flip-flop driven by a destination domain clock (destination flip-flop). Depending on the relationship between the clocks, problems may arise in the data transfer between the source flip-flop and the destination flip-flop. As an example, if the transition at the output of the source flip-flop occurs very close to the valid edge of the second clock, a setup or hold violation may occur at the destination flip-flop. This can cause the output of the second flip-flop to oscillate, become unstable, and may not settle to a stable value before the next valid edge of the second clock. This situation is called metastability and is a potential problem when clock domain crossing, while data inconsistency and data loss issues can also arise when clock domain crossing.

[0034] Figure 1A is a functional block diagram illustrating an example environment 10 of an electronic system 100 in which clock domain crossing synchronization circuits according to embodiments of the present disclosure may be implemented. Figure 1AThe specific example environment 10 of the electronic system 100 in FIG. 1 is a Secure Digital (SD) environment, where the source clock domain SCD is the SD clock domain and the destination clock domain DCD is the Advanced Hardware Bus (AHB) clock domain. Secure Digital (SD) is a proprietary format for various types of memory cards used in mobile devices, and SD Input / Output (SDIO) cards are an extension of this standard and include IO functionality in addition to memory storage, as well as a built-in controller that allows them to communicate with a host device HST and provide extended functionality beyond just memory storage.

[0035] In the SDIO environment 10, the electronic system 100 can be part of the intellectual property (IP) core 12 of an SDIO slave device in an SDIO card 14, where the SDIO card can include multiple SDIO slave devices and the IP core is a functional block of a reusable electronic circuit system. The IP core 12 of each SDIO slave device (which can be referred to as an SDIO slave device IP core 12) includes additional electronic circuit system 16 and the electronic system 100. This additional electronic circuit system 16 (including the electronic system 100) can be formed by suitable hardware, firmware or software, or a combination thereof. The additional electronic circuit system 16 included in each SDIO slave device IP core 12 processes requests received from the host device HST, such as data transfer requests (e.g., read and write requests). More specifically, the SDIO host controller 18 in the host device HST supplies requests, such as data transfer requests (e.g., read and write requests), to the SDIO slave device IP core 12 in the SDIO card 14 via the SDIO bus 20. The additional electronic circuit system 16 in the SDIO slave IP core 12 processes the data transfer request from the host device HST and generates signals that are supplied to control the operation of the electronic system 100 to handle the transfer of the requested data component. The signals generated by the SDIO slave IP core 12 include a start new data transfer request signal SNDT and a data transfer current buffer signal DTCB, which will be referred to as Figure 3 -7 is described in more detail.

[0036] Figure 1B According to one embodiment of the present disclosure Figure 1A 1 is a more detailed functional block diagram of an electronic system 100. The electronic system 100 has a source clock domain SCD and a destination clock domain DCD, wherein a vertical dashed line 102 represents a boundary or crossing between the two clock domains. Figure 1A The SDIO environment 10 is an example of an environment in which an electronic system 100 includes a memory. Figure 1B The FIFO memory 104 is located in the destination clock domain DCD and is used to transfer data to the source clock domain SCD through the double buffers WRDB and RDDB in the source clock domain.

[0037] In this environment, the use of a single FIFO memory 104 reduces the size of the clock domain crossing synchronization circuitry required to interface the SD and AHB clock domains. The clock domain crossing synchronization circuitry utilizes dual buffers WRDB, RDDB to transfer data between the SD and AHB domains in an alternating or "ping-pong" manner, and in this way the dual buffers increase the bandwidth of the data transfer interface between the two clock domains.

[0038] In operation, the host device HST ( Figure 1A ) sends a host data transfer request to the SDIO card 14 via the SDIO bus 20 in the form of a host read request and a host write request. The additional electronic circuit system 16 processes the request and generates signals, including Figure 1A , thereby controlling the operation of the electronic system 100 in handling received requests. More specifically, the additional electronic circuit system 16 provides data transfer control signals DTCS to the controller 106 of the electronic system 100 in the source clock domain SCD, where the data transfer control signals include a write control signal WRCS and a read control signal RDCS. The host device HST and the controller 106 operate in the source clock domain SCD.

[0039] The controller 106 includes a receive (RX) submodule 108 for processing write control signals WRCS generated by the additional electronic circuitry 16 in response to write requests received from the host device HST. The controller 106 also includes a transmit (TX) submodule 110 for processing read control signals RDCS generated by the additional electronic circuitry 16 in response to read requests received from the host device HST. A write double buffer WRDB is included in the RX submodule 108, and a read double buffer RDDB is included in the TX submodule 110. Each double buffer WRDB, RDDB includes two data buffers, designated as data buffers B0 and B1 in FIG. The submodules 108, 110 in the source clock domain SCD are clocked by the source domain clock signal SCK, while the controllers 112, 114 and the FIFO memory 104 in the destination clock domain DCD are clocked by the destination domain clock signal DCK.

[0040] When processing a host write request, the SDIO card 14 ( Figure 1A ) receives a write request from the host device HST via the SDIO bus 20. The SDIO bus 20 ( Figure 1A ) is directly connected between the RX submodule 108 and the TX submodule 110, and the host write request includes the write data WR_DATA from the host device HST. The write data WR_DATA from the host device HST is supplied to the RX submodule 108 through the SDIO bus 20, as shown in FIG. Figure 1BAs seen in FIG. , the additional electronic circuitry 16 supplies a WRCS signal to the RX submodule 108 to indicate to the RX submodule that it will receive write data WR-DATA and will need to process the write data as part of a write request. In response to the WRCS signal, the RX submodule 108 issues an internal write request WR-REQ and write data WR-DATA from the buffer B0 or B1 of the double buffer WRDB designated as the current buffer during a given data transfer cycle. The operation of the data buffers B0 and B1 of the write double buffer WRDB and the read data buffer RDDB will be described in more detail below. The internal write request WR-REQ and write data WR-DATA are issued in the SCD clock domain to the FIFO write controller 112 in the destination clock domain DCD (e.g., the AHB clock domain). The FIFO write controller 112 processes the internal WR-REQ request and write data WR-DATA and handles writing the WR-DATA data from the current buffer B0 or B1 of the write double buffer WRDB to the FIFO memory 104. The FIFO read controller 114 processes the received read data as part of a read request, as will now be described in greater detail below.

[0041] Similarly, when processing a host read request, the SDIO card 14 receives the read request from the host device HST via the SDIO bus 20. The host read request includes the read data RD_DATA from the host device HST. The read data RD_DATA from the host device HST is transmitted via the SDIO bus 20 ( Figure 1A ) is supplied to the TX submodule 110, such as Figure 1B As seen in FIG. Additional electronic circuitry 16 supplies an RDCS signal to TX submodule 110, indicating that it will receive read data RD_DATA and will need to process the read data as part of a read request. In response to the RDCS signal, RX submodule 110 issues an internal read request RD-REQ from the SCD clock domain to FIFO read controller 114 in the DCD clock domain. The FIFO read controller processes the internal RD-REQ request and accesses the read RD-DATA in FIFO memory 104. The read data is provided to buffers B0 and B1 of the read double buffer RDDB in TX submodule 110 as the current buffer. Thereafter, TX submodule 110 provides the read data RD-DATA for transmission from SDIO card 14 to host device HST via SDIO bus 20.

[0042] When transferring data signals between the SD and AHB clock domains, synchronization techniques must be implemented to prevent metastability, data loss, and data consistency issues, as mentioned above. Recall that in an SD environment, the SD clock domain is the source clock domain (SCD), while the AHB clock domain is the destination clock domain. Therefore, write requests WR-REQ and read requests RD-REQ from submodules 108 and 110 in the SD clock domain must be resynchronized in the AHB clock domain to ensure proper operation. Thus, although not explicitly shown in FIG1 , each of the RX and TX submodules 108 and 110 and the FIFO write controller 112 and FIFO read controller 114 includes portions of clock domain cross-synchronization circuitry for resynchronizing signals transferred between the SD and AHB clock domains. Additional submodules SM, such as the additional RX submodule 108 and TX submodule 110, can be connected to each of the FIFO write controller 112 and FIFO read controller 114.

[0043] Figure 2 FIG1 is a signal timing diagram illustrating the loss of the correct order of data transfer requests that may occur using conventional synchronization techniques implemented with conventional clock domain crossing circuitry in the electronic system 100 of FIG1. Although not shown in FIG1, each of the write request WR-REQ and read request RD-REQ signals from the submodules 108 and 110 in the SD clock domain is directed to the current buffer in the buffers B0 and B1. Figure 2 The write request is illustrated by way of example. The RX submodule 108 generates a write request WR-REQ, which includes a source domain write first buffer signal SDWRB0 and a source domain write second buffer signal SDWRB1. The RX submodule 108 activates only the buffer signals WRB0 and WRB1 for one of the buffers B0 and B1 that is the current buffer. Figure 2 In the example shown in FIG, the source domain write first buffer signal SDWRB0 is first activated at time t0, at which time buffer B0 is indicated as the current buffer in the source clock domain SCD. The source domain write second buffer signal SDWRB1 is then activated at time t1, at which time buffer B1 is indicated as the current buffer in the source clock domain SCD.

[0044] Conventional clock domain synchronization circuitry in the FIFO write controller 112 resynchronizes the SDWRB0 and SDWRB1 signals in the destination clock domain to the synchronized source-domain write buffer signals SDWRB0-SYNC and SDWRB1-SYNC in the destination clock domain. However, this conventional clock domain synchronization circuitry cannot guarantee the correct order of the SDWRB0 and SDWRB1 signals. The conventional clock domain synchronization circuitry FIFO write controller 112 then generates destination-domain write buffer signals DDWRB0 and DDWRB1 based on or in response to the synchronized source-domain write buffer signals SDWRB0-SYNC and SDWRB1-SYNC. Thereafter, the FIFO write controller 112 applies the DDWRB0 and DDWRB1 signals to the FIFO memory 104 to store the write data contained in the current buffers B0 and B1 of the write double buffer WRDB in the FIFO memory.

[0045] like Figure 2 As shown in FIG, conventional clock domain crossing circuitry in the FIFO write controller 112 may not correctly preserve the order of the source domain write buffer signals SDWRB0-SYNC, SDWRB1-SYNC generated in the destination clock domain DCD. This in turn also results in incorrect generation of the DDWRB0, DDWRB1 signals. Figure 2 The diagram illustrates a possible scenario in which both the synchronized source-domain write buffer signal SDWRB0 and the synchronized source-domain write buffer signal SDWRB1-SYNC occur at the same time t2 in the destination clock domain DCD. The signals in the destination clock domain DCD are synchronized with the destination-domain clock signal DCK, but because both the DDWRB0 and DDWRB1 signals occur at time t2, proper operation may not occur. The write operation associated with one of the DDWRB0 and DDWRB1 signals and the write data stored in the corresponding data buffers B0 and B1 may be lost, or the order of the write operations may be reversed.

[0046] Embodiments of the present disclosure are directed to clock domain cross-synchronization circuits and methods for ensuring the correct order of signals and operations in an electronic environment, such as the electronic system 100 of FIG. 1 , wherein data is transferred between a FIFO memory 104 in a destination clock domain (DCD) and a current buffer in a source clock domain (SCD). The current buffer is one of the data buffers B0 and B1 in the dual buffers WRDB and RDDB that is used to transfer data during or within the current data transfer cycle. Embodiments of the present disclosure transfer the current buffer in the destination clock domain (DCD) to the source clock domain (SCD) at the start of a data transfer, thereby setting the current buffer in the source clock domain to be equal to the current buffer in the destination clock domain. Thereafter, when a read or write data transfer request signal is transmitted from the source clock domain (SCD) to the destination clock domain (DCD), the synchronization circuit detects whether the transmitted data transfer request signal is associated with the current buffer in the destination clock domain. If the data transfer request signal is associated with the current buffer, the data transfer is performed within the current data transfer cycle. When the data transfer request signal is not associated with the current buffer in the destination clock domain, the data transfer request signal for the associated data buffer B0 , B1 is delayed to a subsequent data transfer cycle, and the associated data transfer is performed within this subsequent data transfer cycle.

[0047] Figure 3 FIG2 is a functional block diagram of a clock domain crossing synchronization circuit 300 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, portions of the synchronization circuit 300 are included in the RX submodule 108, the TX submodule 110, the FIFO write controller 112, and the FIFO read controller 114 in the electronic system 100. The synchronization circuit 300 includes a destination current buffer generator 302 in the destination clock domain DCD. The destination current buffer generator 302 is configured to generate a destination domain current buffer signal DCB having a value indicating whether the first data buffer B0 or the second data buffer B1 of the dual buffer DB in the source clock domain SCD is the current buffer to be used in the current data transfer cycle or operation. The destination current buffer generator 302 also switches or changes the level or state of the DCB signal in response to a data transfer request signal DTR applied to the FIFO memory 303 during a data transfer cycle of the synchronization circuit 300, as will be described in more detail below. The components of the synchronization circuit 300 in the destination clock domain DCD are clocked by the destination domain clock signal DCK, while the components in the source clock domain SCD are clocked by the source domain clock signal SCK. The clock signals DCK and SCK are shown as being applied only to the Figure 3 The components of the synchronous circuit are selected only to simplify the diagram.

[0048] The first synchronization circuit 304 receives the destination current buffer signal DCB and generates a corresponding synchronized destination current buffer signal DCB-SYNC in the source clock domain. The DCB-SYNC signal is applied to the source current buffer generator 306, which is configured to generate a source domain current buffer signal SCB based on the synchronized destination current buffer signal DCB-SYNC. The source current buffer signal SCB has a first value indicating that the first data buffer B0 is the current buffer and a second value indicating that the second data buffer B1 is the current buffer. The source current buffer generator 306 also receives the start new data transfer signal SNDT supplied by the additional electronic circuit system 16 included in the SDIO slave device IP core 12 of the SDIO card 14 of the electronic system 100, as described above with reference to Figure 1A As described. In response to the SNDT signal becoming active to indicate the start of a new data transfer cycle or operation of the synchronization circuit 300, the source current buffer generator 306 sets the source current buffer signal SCB to a value corresponding to the same current buffer indicated by the synchronized destination current buffer signal SCD-SYNC. In this way, at the start of the data transfer operation, the SCB signal is set to the same current buffer indicated by the DCB signal so that the circuit systems in both clock domains DCD and SCD start with the same current buffer (either data buffer B0 or data buffer B1).

[0049] After the data transfer operation starts, the source current buffer generator 306 changes or switches the value of the source current buffer signal SCB for each data transfer cycle of the data transfer operation in response to the data transfer current buffer signal DTCB indicating that another data buffer B0, B1 should be used. Figure 1A Each of the RX submodule 108 and the TX submodule 110 uses the DTCB signal to switch between the two data buffers B0 and B1. The additional electronic circuit system 16 activates the DTCB so that the corresponding submodule 108 and 110 switches the current buffer B0 and B1 when either the current buffer is full (i.e., all corresponding data is stored in the current buffer) or the last byte of data transferred to the current buffer has been received or sent. The DTCB signal includes a write current buffer signal WCB and a read current buffer signal RCB, which are used by the write clock domain crossing synchronization circuit and the read clock domain crossing synchronization circuit, respectively, as will be referred to below. Figure 4A 、 Figure 4B and Figure 7A 、 Figure 7B discussed in more detail.

[0050] The value of the SCB signal switches between a first value and a second value to alternately indicate whether the first data buffer B0 or the second data buffer B1 is the current buffer. Thus, the current buffer signal SCB alternately changes in each data transfer cycle of the data transfer operation.

[0051] The source data transfer request generator 308 receives the source current buffer signal SCB and generates a source data transfer request signal SDTR in the source clock domain SCD based on the source current buffer signal. The source data transfer request signal SDTR is associated with the current buffer indicated by the source current buffer signal SCB. Figure 3 In the embodiment of the present invention, the source data transfer request signal SDTR includes a first buffer source data transfer request signal SDTR-B0 and a second buffer source data transfer request signal SDTR-B1. When the first buffer B0 is the current buffer, the source data transfer request generator 308 activates the SDTR-B0 signal, and when the second buffer B1 is the current buffer, the source data transfer request generator activates the SDTR-B1 signal. In the source clock domain SCD, only one of the source data transfer request signals SDTR-B0 and SDTR-B1 is activated at a time.

[0052] The second synchronization circuit 310 receives the source data transfer request signals SDTR-B0 and SDTR-B1 and generates corresponding synchronized source data transfer request signals in the destination clock domain. Figure 3 In an exemplary embodiment, the synchronized source data transfer request signals include a first buffer synchronized source data transfer request signal SDTR-B0-SYNC and a second buffer synchronized source data transfer request signal SDTR-B1-SYNC in the destination clock domain. Although only one of the source data transfer request signals SDTR-B0 and SDTR-B1 is activated at a time in the source clock domain SCD, since the synchronization circuit 310 cannot guarantee the correct order of these signals, the SDTR-B0-SYNC and SDTR-B1-SYNC signals may be activated or switched at the same time in the destination clock domain DCD.

[0053] A destination data transfer request and delay generator 312 in the destination clock domain receives the synchronized source data transfer request signals SDTR-B0-SYNC and SDTR-B1-SYNC and the destination domain current buffer signal DCB. In operation, the destination data transfer request and delay generator 312 utilizes the DCB signal to determine which of the synchronized source data transfer request signals SDTR-B0-SYNC and SDTR-B1-SYNC to use during the current data transfer cycle and which of these signals to delay until a subsequent data transfer cycle. When the current buffer indicated by or associated with the destination domain data transfer request signals SDTR-B0-SYNC and SDTR-B1-SYNC does not correspond to the current buffer indicated by the destination domain current buffer signal DCB, the delayed data transfer request and delay generator 312 delays the transfer of data between the FIFO memory 303 (or other types of memory in other embodiments) and one of the data buffers B0 and B1 serving as the current buffer until a subsequent data transfer cycle. When the destination domain current buffer signal DCB has a value indicating the same current buffer associated with the activated SDTR-B0-SYNC, SDTR-B1-SYNC signals, the destination data transfer request and delay generator 312 provides the data transfer request signal DTR to the FIFO memory 303, thereby transferring data between the FIFO memory and the current buffer within the current data transfer cycle.

[0054] In operation of the synchronization circuit 300, the additional electronic circuit system 16 (see Figure 1A ) activates the start new data transfer signal SNDT applied to the source current buffer generator 306, and the data transfer operation begins. Each data transfer operation includes one or more data transfer cycles. In response to the SNDT signal becoming active, the source current buffer generator 306 drives the source current buffer signal SCB to the same level or value as the synchronized destination current buffer signal DCB-SYNC provided by the first synchronization circuit 304 to indicate the same current buffer. The DCB-SYNC signal indicates the current value of the destination current buffer signal DCB generated by the destination current buffer generator 302, thereby indicating the current buffer in the destination clock domain. In this way, the components in the source clock domain SCD determine the current buffer to be used to start the data transfer operation.

[0055] Thereafter, source data transfer request generator 308 activates the first buffer source data transfer request signal SDTR-B0 or the second buffer source data transfer request signal SDTR-B1 that corresponds to the current buffer. Assuming that, for the current example data operation being described, the initial current buffer is data buffer B0, request generator 308 activates the SDTR-B0 signal. Synchronization circuit 310 then resynchronizes the SDTR-B0 signal to activate the synchronized source data transfer request signal SDTR-B0-SYNC in the destination clock domain DCD. At this point, destination data transfer request and delay generator 312 takes one of two actions depending on whether the current buffer (in this example, buffer B0) corresponds to the current buffer indicated by destination domain current buffer signal DCB. When the DCB signal indicates that the current buffer is buffer B0, destination data transfer request and delay generator 312 activates the data transfer signal DTR supplied to FIFO memory 303, thereby transferring data between current buffer B0 and FIFO memory 303 during the current data transfer cycle. In response to the activated DTR signal, the destination current buffer generator 302 increments or switches the DCB signal to indicate that another data buffer B1 is the current buffer during the subsequent data transfer cycle. In the source clock domain SCD, the source current buffer generator 306 also responds to the SDIO slave device IP core 12 ( Figure 1A ) drives the DTCB signal to indicate that the current data buffer B0, B1 is full (i.e., all corresponding data are stored in the current buffer) or the last byte of data transferred to the current buffer has been received or sent and increments or toggles the SCB signal.

[0056] During a data transfer cycle, by the time the SDTR-B0 signal is applied to the destination data transfer request and delay generator 312, the value of the DCB signal may have already changed state. Therefore, if, in this example, the DCB signal indicates that the current buffer is buffer B1 rather than buffer B0, the destination data transfer request and delay generator 312 delays the transfer of data between current buffer B0 and FIFO memory 303 until a subsequent data transfer cycle. In this case, during the current data transfer cycle, data is first transferred between buffer B1 and FIFO memory 303. Once the destination current buffer signal DCB changes state in response to the DTR signal being activated for this transfer, the DCB signal will again indicate that buffer B0 is the current buffer, at which point the destination data transfer request and delay generator 312 immediately activates the DTR signal to transfer data between FIFO memory 303 and buffer B0. In this manner, data transfers between clock domains are not lost; rather, the transfer is delayed until a subsequent data transfer cycle, where the current buffer associated with the transfer does not match the source clock domain SCD and the destination clock domain DCD.

[0057] FIG4 is a more detailed functional block diagram of a write clock domain crossing synchronization circuit 400 according to an embodiment of the present disclosure. Figure 3 The clock domain crossing synchronization circuit 300 includes the write clock domain crossing synchronization circuit 400 of FIG. 4 and the read clock domain crossing synchronization circuit 700 shown in FIG. 7 to provide synchronization of read and write data transfer between the source clock domain SCD and the destination clock domain DCD.

[0058] 4 , the write clock domain crossing synchronization circuit 400 includes a destination current buffer generator 402 to generate a destination current buffer signal DCB. The generator 402 includes a flip-flop 404 having an input and an output, and is clocked by the destination domain clock signal DCK. A multiplexer 406 has a first input coupled to the output of the flip-flop, a second input receiving the output of the flip-flop via an inverter 408, and an output coupled to the input of the flip-flop. The control input of the multiplexer 406 is coupled to receive a write request signal WR-REQ, where the write request signal is the same as the one described above. Figure 3 The synchronization circuit 300 is discussed as a part of the data transfer request signal DTR.

[0059] In operation, each time the WR-REQ signal becomes active, the destination current buffer generator 402 switches the DCB signal to transfer data to the FIFO memory 410. The FIFO memory 410 corresponds to the FIFO memory in the destination clock domain DCD, as described above with reference to FIG. Figure 3When the WR-REQ signal is asserted or activated, multiplexer 406 supplies the complement of the DCB signal from inverter 408 to the input of flip-flop 404, so that when the flip-flop is clocked, the complement of the current value of the DCB signal is output by the flip-flop. In this manner, generator 402 switches the DCB signal in response to the activation of the WR-REQ signal. When the WR-REG signal is not active, multiplexer 408 outputs the feedback DCB signal to the input of flip-flop 404, so that the current value of the DCB signal is maintained whenever the flip-flop is clocked.

[0060] The write clock domain crossing synchronization circuit 400 further includes a first synchronization circuit 412 including first and second series flip-flops 414 and 416 clocked by the source domain clock signal SCK. The series flip-flops 414 and 416 operate in a conventional manner to synchronize the DCB signal in the source clock domain SCD and provide a synchronized DCB signal SCB-SYNC. The source domain current buffer generator 418 includes a first multiplexer 420 having a first input coupled to receive the SCB-SYNC signal and a control input coupled to receive a start new data transfer signal SNDT provided by the additional electronic circuit system 16, as described above with respect to Figure 1A and Figure 3 As described. Flip-flop 422 has an input coupled to the output of first multiplexer 420 and has an output providing source domain current buffer signal SCB. Second multiplexer 424 receives the SCB signal on a first input and receives the complement of the SCB signal on a second input in the form of the SCB signal applied through inverter 426. The output of second multiplexer 424 is coupled to a second input of first multiplexer 420. A control input of second multiplexer 424 is coupled to receive a write current buffer signal WCB provided by additional electronic circuitry 16, wherein the WCB signal is the same as described above with reference to FIG. Figure 1A and 3 One of the signals corresponding to the DTCB signal discussed.

[0061] In the operation of the source domain current buffer generator 418, when the data transfer operation starts, the SDIO card 14 ( Figure 1A) asserts or activates the SNDT signal and deactivates the WCB signal. The activated SNDT signal causes multiplexer 420 to provide the DCB-SYNC signal to the input of flip-flop 422. Flip-flop 422 is then clocked by the SCK signal to output the SCB signal having a value corresponding to the value of the DCB-SYNC signal. After the value of the DCB-SYNC signal has been clocked into flip-flop 422 for a sufficient time, the additional electronic circuitry 16 deactivates the SNDT signal, causing the multiplexer to provide the output of multiplexer 424 to the input of flip-flop 422. When the WCB signal is deactivated, multiplexer 424 provides the SCB signal thereon, causing the current value of the SCB signal to be fed back to the input of flip-flop 422 through multiplexers 424 and 420 to maintain the current value of the SCB signal while the flip-flop is being clocked. When the WCB signal is activated, multiplexer 424 provides the complement of the SCB signal from inverter 426 at its output, and this complement is thereafter provided to the input of flip-flop 422 via multiplexer 420. In this case, when flip-flop 422 is clocked, the flip-flop switches or drives the SCB signal to a complementary state. The additional electronic circuitry 16 activates the WCB signal whenever write data has been loaded into the current buffer and is ready to be transferred to the FIFO memory 410, as will be described in more detail below.

[0062] The clock domain crossing synchronization circuit 400 also includes a source data transfer request generator 428, which generates source data transfer request signals in the form of a first buffer source write request signal SWR-B0 and a second buffer source write request signal SWR-B1. In an embodiment of the circuit 400, each of the SWR-B0 and SWR-B1 signals can be an NRZ signal, and in this description, such NRZ signals can be described as "becoming valid" or becoming a "valid signal." In this context, "becoming valid" or "valid signal" corresponds to a transition or edge of such an NRZ signal. The source data transfer request generator 428 includes a first flip-flop 430 and a second flip-flop 432, which generate the SWR-B0 and SWR-B1 signals at their respective outputs. The source data transfer request generator 428 also includes a logic circuit system 434, which receives the WCB signal and the SCB signal and is coupled to the inputs of the flip-flops 430 and 432. The logic circuitry 434 is configured to provide a valid signal to the input of the first flip-flop 430 in response to the WCB signal becoming valid and the SCB signal indicating that the first data buffer B0 is the current buffer. The logic circuitry 434 is further configured to provide a valid signal to the input of the second flip-flop 432 in response to the WCB signal becoming valid and the SCB signal indicating that the second data buffer B1 is the current buffer. Finally, the logic circuitry 434 is further configured to provide an invalid signal at the input of each of the first and second flip-flops 430 and 432 in response to the first buffer source write request signal SWR-B0 and the second buffer source write request signal SWR-B1 becoming valid, respectively.

[0063] In the embodiment of FIG4 , logic circuitry 434 includes an inverter 436 whose input is coupled to receive the SCB signal and whose output is coupled to a first input of a first AND gate 438. First AND gate 438 has a second input that receives the WCB signal and an output coupled to a first input of a multiplexer 440. The output of multiplexer 440 is applied to an input of flip-flop 430, and the output of this flip-flop is coupled to the first and second inputs of the multiplexer directly and through an inverter 442, respectively. Logic circuitry 434 also includes a second AND gate 446, a multiplexer 448, and an inverter 450 coupled to flip-flop 432 in the same manner as just described for components 438, 440, and 442 of flip-flop 430. However, unlike first AND gate 438, second AND gate 446 receives the SCB signal directly on its input.

[0064] In operation, whenever the additional electronic circuitry 16 activates the WCB signal, the source data transfer request generator 428 activates one of the SWR-B0 and SWR-B1 signals corresponding to the current buffer indicated by the SCB signal. As mentioned above, the WCB signal is activated in response to write data WR-DATA being stored in the current buffer B0 or B1 and ready for transfer to the FIFO memory 410. Initially, assume that the SCB signal is high, indicating that buffer B1 is the current buffer, and the WCB signal is inactive low. The high SCB signal enables AND gate 446, but because the WCB signal is low, this AND gate initially provides a low output to multiplexer 448. The low output from AND gate 446 causes multiplexer 448 to provide the SWR-B1 signal at the output of flip-flop 432 to its input. In this case, if clocked by the source clock domain signal SCD, flip-flop 432 maintains the current state of the SWR-B1 signal. When the WCB signal is activated (i.e., driven high in this embodiment), AND gate 446 applies a high output to multiplexer 448, which in turn couples the complement of the output of flip-flop 432 to the input of flip-flop 432, where the complement of the output of flip-flop 432 is the complement of the SWR-B1 signal output by inverter 450.

[0065] When flip-flop 432 is subsequently clocked by source-domain clock signal SCK, the flip-flop drives the SWR-B1 signal active, assuming both the SCB and WCB signals are at logic 1. Whenever both the SCB and WCB signals are at logic 1, the SWR-B1 signal provided by flip-flop 432 changes value when clocked by the SCK signal. In this manner, the SWR-B1 signal maintains its current value (logic 1 or 0) until the next switch to the current buffer B1 occurs. In the embodiment of FIG. 4 , the active SWR-B1 signal is a non-return-to-zero (NRZ) signal. When flip-flop 432 drives the SWR-B1 signal active, this active signal is fed back through inverter 450 to provide the complement of the SWR-B1 signal to the corresponding input of multiplexer 448, which in turn provides this complement to the input of flip-flop 432. Therefore, when flip-flop 432 is again clocked by the SCK signal, the select signal provided from AND gate 446 to multiplexer 448 is a logic 0, causing the flip-flop to maintain the value of the SWR-B1 signal the next time it is clocked by the SCK signal. In this manner, flip-flop 432 generates a valid NRZ signal for the SWR-B1 signal. Components 436, 438, 440, and 442 coupled to flip-flop 430 operate in the same manner, causing this flip-flop to generate a valid NRZ signal for the SWR-B0 signal when the SCB signal is low (indicating that the current buffer is buffer B0).

[0066] The clock domain crossing synchronization circuit 400 of FIG4 also includes a second synchronization circuit 452, which includes two pairs of serially connected flip-flops. More specifically, the synchronization circuit 452 includes first and second serially connected flip-flops 454 and 456, which are clocked by the destination domain clock signal DCK. These serially connected flip-flops 414 and 416 operate in a conventional manner to synchronize the SWR-B0 signal in the destination clock domain DCD and provide a synchronized first buffer source write request signal SWR-B0-SYNC. The synchronization circuit 452 also includes serially connected flip-flops 458 and 460, which are clocked by the DCK signal and are used to synchronize the SWR-B1 signal in the destination clock domain to provide a synchronized second buffer source write request signal SWR-B1-SYNC.

[0067] 4, the clock domain crossing synchronization circuit 400 further includes a destination data transfer request and delay generator 462, which receives the SWR-B0-SYNC and SWR-B1-SYNC signals from the second synchronization circuit 452. SWR-B0-SYNC and SWR-B1-SYNC are Figure 3 The destination data transfer request and delay generator 462 includes a first pulse generator 464, which includes a flip-flop 466 that receives the SWR-B0-SYNC signal at an input and has an output coupled to one input of an XOR gate 468. A second input of the XOR gate 468 is coupled to directly receive the SWR-B0-SYNC signal, and the XOR gate generates a write first buffer pulse signal WR-B0 at its output. A second pulse generator 470 includes a flip-flop 472 that receives the SWR-B1-SYNC signal at an input and has an output coupled to one input of an XOR gate 474. A second input of XOR gate 474 is coupled to directly receive the SWR-B1-SYNC signal, and the XOR gate generates a write second buffer pulse signal WR-B0 at its output.

[0068] In operation, each pulse generator 464, 470 generates an active pulse signal for the WR-B0 and WR-B1 signals in response to the corresponding SWR-B0-SYNC and SWR-B1-SYNC signals becoming active. For example, assume that the output of flip-flop 466 is initially low along with the SWR-B0-SYNC signal. At this point, XOR gate 468 drives the WR-B0 signal to an inactive low. In response to the SWR-B0-SYNC signal becoming active high, XOR gate 468 drives the WR-B0 signal to an active high because the XOR gate now receives a high SWR-B0-SYNC signal and a low output signal from flip-flop 466. When flip-flop 466 is next clocked by the DCK signal, the flip-flop drives its output high, causing XOR gate 468 to then deactivate the WR-B0 signal. In this manner, pulse generator 464 generates a pulse signal for the WR-B0 signal. The operation of pulse generator 470 is identical to the operation of generating the pulse signal for the WR-B1 signal.

[0069] Destination data transfer request and delay generator 462 also includes a first transfer request delay circuit 476 having a first input coupled to receive the destination domain current buffer signal DCB and a second input coupled to receive the write first buffer pulse signal WR-B0. First transfer request delay circuit 476 is configured to assert the delayed write first buffer signal D-WR-B0 in response to the write first buffer pulse signal WR-B0 becoming active and the destination domain current buffer signal DCB indicating that the second buffer B1 is the current buffer in the destination clock domain DCD. In the embodiment of FIG. 4 , first transfer request delay circuit 476 includes an AND gate 478 having a first input coupled to receive the DCB signal and a second input coupled to the output of an OR gate 479. OR gate 479 receives the WR-B0 signal at a first input and the D-WR-B0 signal at a second input. The output of AND gate 478 is supplied to an input of a flip-flop 480, which generates the D-WR-B0 signal at its output.

[0070] In operation, OR gate 479 enables AND gate 478 when either the WR-B0 signal or the D-WR-B0 signal is active high. When AND gate 478 is enabled and the DCB signal is high (indicating that the current buffer is buffer B1) and the WR-B0 signal is active (indicating that buffer B0 is to be written), AND gate 478 drives its output high. When flip-flop 480 is clocked, this high output of AND gate 478 is latched by the flip-flop, thereby driving the D-WR-B0 signal active high. Thereafter, the D-WR-B0 signal will be used to write the data associated with the WR-B0 signal in subsequent data transfer cycles, as will be described in more detail below. OR gate 479 is used to cause flip-flop 480 to maintain the D-WR-B0 signal high (i.e., logic 1) when clocked when the DCB signal is high (indicating that the current buffer is buffer B1 rather than buffer B0).

[0071] Second transfer request delay circuit 482 includes an AND gate 484, an OR gate 485, and a flip-flop 486 coupled in the same manner as corresponding components 478, 479, and 480 in first transfer request delay circuit 476, except that the DCB signal is applied to one input of AND gate 484 via inverter 487. Second transfer request delay circuit 482 operates in the same manner as described for first transfer request delay circuit 476, except with respect to buffer B1. When the DCB signal is low (indicating that the current buffer is buffer B0) and the WR-B1 signal goes high (indicating that buffer B1 is to be written), AND gate 484 drives its output high. When flip-flop 486 is clocked, this high output of AND gate 484 is latched by the flip-flop, driving the D-WR-B1 signal high. Thereafter, the D-WR-B1 signal is used to write the data associated with the WR-B1 signal during a subsequent data transfer cycle, as described in greater detail below. OR gate 485 is used to cause flip-flop 486 to maintain the D-WR-B1 signal high (ie, logic 1) when clocked when the DCB signal is low (indicating that the current buffer is buffer B0 and not buffer B1).

[0072] The destination data transfer request and delay generator 462 also includes output logic 488, which is coupled to the first and second pulse generators 464 and 470 to receive the write first buffer pulse signal WR-B0 and the write second buffer pulse signal WR-B1. The output logic 488 is also coupled to the first and second transfer request delay circuits 476 and 482 to receive the delayed write first buffer signal D-WR-B0 and the delayed write second buffer signal D-WR-B1. The output logic 488 generates the first buffer write request pulse signal WR-B0-REQ in response to either the WR-B0 or D-WR-B0 signal becoming active. The output logic 488 generates the second buffer write request pulse signal WR-B1-REQ in response to either the WR-B1 or D-WR-B1 signal becoming active. In the embodiment of FIG. 4 , the output logic 488 includes a first OR gate 489 for receiving the WR-B0 and D-WR-B0 signals and generating WR-B0-REQ in response to these signals. The second OR gate 490 receives the WR- B1 and D-WR- B1 signals and generates WR- B1 -REQ in response to these signals.

[0073] In the embodiment of FIG4 , destination data transfer request and delay generator 462 further includes a first selection circuit in the form of a multiplexer 491. Multiplexer 491 has inputs coupled to output logic 488, or more specifically, to the outputs of OR gates 489 and 490, to receive WR-B0-REQ and WR-B1-REQ signals. A control input of multiplexer 491 receives the destination domain current buffer signal DCB. When the DCB signal is low (indicating that the first buffer B0 is the current buffer), multiplexer 491 outputs the WR-B0-REQ signal as the write request signal WR-REQ to FIFO memory 410, transferring write data from the current buffer (buffer B0) indicated by the DCB signal to the FIFO memory. When the DCB signal is high (indicating that the second buffer B1 is the current buffer), the multiplexer 491 provides the WR-B1-REQ signal as a write request signal WR-REQ to the FIFO memory 410 to transfer write data from the current buffer (buffer B1) indicated by the DCB signal to the FIFO memory.

[0074] In addition to the operations described above, the destination data transfer request and delay generator 462 is also used to ensure that the desired write data transfer (i.e., WR-B0 and WR-B1) is not lost or missed. The destination data transfer request and delay generator 462 achieves this by generating a WR-REQ signal to transfer the write data to the FIFO memory 410 when the current buffer indicated by the DCB signal does not correspond to the buffer associated with the activated WR-B0 or WR-B1 signal. This is achieved by delaying the write first and second buffer signals D-WR-B0 and D-WR-B1 generated by the circuit 462. When the WR-B0 signal has been generated to transfer the write data from buffer B0 to the FIFO memory 410, but the DCB signal indicates that the current buffer is buffer B1, the D-WR-B0 signal is set to active. In this case, once the DCB signal transitions to indicate that the current buffer is buffer B0, the active D-WR-B0 signal causes OR gate 489 to activate the WR-B0-REQ signal, which is then provided to FIFO memory 410 as the WR-REQ signal via multiplexer 491, thereby writing data from buffer B0 to the FIFO memory. Therefore, even if the current buffer indicated by the DCB signal is different from the buffer associated with the write request signal (WR-B0 or WR-B1) from the source clock domain SCD, the write request is not lost but is delayed until a subsequent data transfer cycle in which the DCB signal corresponds to the current buffer associated with the write request. The operation of destination data transfer request and delay generator 462 is similar to the operation of the D-WR-B1 and WR-B1 signals with respect to buffer B1.

[0075] Finally, the destination data transfer request and delay generator 462 includes a selection circuit 492, which is a multiplexer in the embodiment of FIG4. The multiplexer has a first input coupled to receive first buffer write data B0-WR-DATA from data buffer B0 and a second input coupled to receive second buffer write data B1-WR-DATA from data buffer B1. Data buffers B0 and B1 are part of a double buffer DB in the source clock domain SCD, as described above with reference to FIG4. Figure 3 In operation, when the DCB signal indicates that the first data buffer B0 is the current buffer, the multiplexer 492 supplies the write data B0-WR-DATA stored in the data buffer B0 to the FIFO memory 410. When the DCB signal indicates that the second data buffer B1 is the current buffer, the multiplexer 492 supplies the write data B1-WR-DATA stored in the data buffer B1 to the FIFO memory 410.

[0076] Finally, in the embodiment of FIG4 , the clock domain crossing synchronization circuit 400 further includes a data selection circuit 493 coupled to data buffers B0 and B1 of the double buffer DB and coupled to receive write data WR-DATA from the host HST. In response to the SCB signal, when the DCB signal indicates that the first data buffer B0 is the current buffer, the data selection circuit 493 supplies the write data WR-DATA from the host HST to the first data buffer B0 for storage. When the DCB signal indicates that the second data buffer B1 is the current buffer, the data selection circuit 493 supplies the write data WR-DATA from the host HST to the second data buffer B1 for storage.

[0077] The data selection circuit 493 includes a first AND gate 494 having a first input coupled to receive WR-DATA from the host HST and a second input coupled to receive the SCB signal applied via an inverter 496. A second AND gate has a first input coupled to receive WR-DATA from the host HST and a second input coupled to receive the SCB signal. When the SCB signal is low (indicating that data buffer B0 is the current buffer), a low SCB signal is applied via inverter 492 to enable AND gate 494, thereby providing WR-DATA from the host HST to the first data buffer B0 for storage in the first data buffer. Conversely, when the SCB signal is high (indicating that data buffer B1 is the current buffer), a high SCB signal enables AND gate 495, thereby providing WR-DATA from the host HST to the second data buffer B1 for storage in the second data buffer. The write data WR-DATA includes multiple signals or bits, but these are not explicitly shown in FIG. Thus, although only two single AND gates 494 and 495 are shown, in practice, a plurality of such AND gates, one for each bit of WR-DATA, will be included in the data selection circuit 492. This is further illustrated by the depiction of data buffers B0 and B1 in FIG4 , where each buffer is shown as including a plurality of flip-flops, one for each bit of WR-DATA to be stored in the buffer.

[0078] Figure 5 is a signal timing diagram illustrating the operation of the write clock domain crossing synchronization circuit 400 of Figure 4. More specifically, the signal timing diagram illustrates the operation of the destination data transfer request and delay generator 462 in delaying the write data transfer from the source clock domain SCD when the data buffers B0, B1 associated with the request do not correspond to the current buffers indicated in the destination clock domain DCD. Figure 5An example is shown in which the write data from the first data buffer B0 is written first, and then the write data from the data buffer B1 is written using the D-WR-B1 signal generated for this write transfer. Figure 5 Describe the operation.

[0079] At time t0, source data transfer request generator 428 generates a first buffer source write request signal SWR-B0 associated with a write data transfer to be performed with data buffer B0 as the current buffer. Later, at time t1, source data transfer request generator 428 generates a second buffer source write request signal SWR-B1 associated with a write data transfer to be performed with data buffer B1 as the current buffer. At time t2, corresponding signals generated in the destination clock domain DCD based on the SWR-B0 and SWR-B1 signals from the source clock domain SCD are shown. More specifically, the SWR-B0-SYNC and SWR-B1-SYNC signals from synchronization circuit 452 and the write first and second buffer pulse signals WR-B0 and WR-B1 from the destination data transfer request and delay generator 462 are shown transitioning in the destination clock domain DCD. The correct order of these signals has been lost, with all signal transitions occurring at approximately t2. Thus, although the edges or transitions of the SWR- B0 and SWR- B1 signals are separated at times t0 and t1 in the source clock domain SCD, the corresponding transitions occur substantially simultaneously in the destination clock domain at t2.

[0080] In conventional synchronous circuits, the loss of proper order and the occurrence of multiple transitions at time t2 can lead to incorrect operation, such as the loss of one of the write transfers in the form of the SWR-B0 and SWR-B1 signals emanating from the source clock domain SCD. Figure 5In the example shown, the write data transfer associated with the SWR-B0 signal is first processed in the destination clock domain DCD to transfer the write data from data buffer B0 to FIFO memory 410. This is seen in the signal timing diagram because the Write First Buffer Pulse signal WR-B0 is asserted from time t2 to time t3. This signal is associated with or corresponds to a write transfer with the first data buffer B0, and during this time, the DCB signal indicates that the first data buffer B0 is the current buffer. Therefore, this write transfer associated with buffer B0 is processed first. Furthermore, the transition of the WR-B1 signal when the DCB signal indicates that the current buffer is data buffer B0 results in the generation of the delayed Write Second Buffer signal D-WR-B1 at time t3. Therefore, when the value of the DCB signal changes state at time t3 to indicate that the current buffer is data buffer B1, the write transfer associated with the SWR-B1 signal is executed. Therefore, despite the loss of synchronization of the associated signals in the destination clock domain DCD, the write transfer associated with the SWR-B0 and SWR-B1 signals is still executed.

[0081] Figure 6 4 is a signal timing diagram illustrating the operation of the write clock domain crossing synchronization circuit 400 in a second example of delaying a write data transfer request. Except that the DCB signal initially indicates that the current buffer is data buffer B1 rather than buffer B0, Figure 6 The example is similar to the one just given for Figure 5 1. The source data transfer request generator 428 initially generates a second buffer source write request signal SWR-B1 at time t0 associated with a write data transfer to be performed using data buffer B1, and then generates a first buffer source write request signal SWR-B0 at time t1. At time t2, corresponding signals generated in the destination clock domain DCD based on the SWR-B0 and SWR-B1 signals from the source clock domain SCD are shown, specifically, the SWR-B0-SYNC and SWR-B1-SYNC signals from the synchronization circuit 452, and the write first and second buffer pulse signals WR-B0 and WR-B1 from the destination data transfer request and delay generator 462. Again, these signals have lost synchronization, with all signal transitions occurring at approximately t2.

[0082] exist Figure 6In the example of , the write data transfer associated with the SWR-B1 signal is processed first in the destination clock domain DCD to transfer the write data from the data buffer B1 to the FIFO memory 410. This is seen in the signal timing diagram because the write first buffer pulse signal WR-B1 is asserted from time t2 to time t3. This signal is associated with or corresponds to the write transfer of the first data buffer B1, and during this time the DCB signal indicates that the first data buffer B1 is the current buffer. Therefore, this write transfer associated with buffer B1 is processed first. In addition, the transition of the WR-B0 signal when the DCB signal indicates that the current buffer is the data buffer B1 results in the generation of a valid delayed write second buffer signal D-WR-B0 at time t3. Therefore, when the value of the DCB signal changes state at time t3 to indicate that the current buffer is the data buffer B0, the write transfer associated with the SWR-B0 signal is performed. Therefore, Figure 5 Compared to the example of , the two write transfers associated with the SWR-B0 and SWR-B1 signals are executed again, although in reverse order. Although the associated signals in the destination clock domain DCD are out of synchronization, the two write transfers are still executed again.

[0083] FIG7 is a more detailed functional block diagram of a read clock domain crossing synchronization circuit 700 according to an embodiment of the present disclosure. Figure 3 The clock domain crossing synchronization circuit 300 includes the write clock domain crossing synchronization circuit 400 of FIG. 4 and the read clock domain crossing synchronization circuit 700 shown in FIG. 7 , to provide synchronization for both read and write data transfers between a source clock domain (SCD) and a destination clock domain (DCD). The read clock domain crossing synchronization circuit 700 includes components 700-795, which generally correspond to components 400-495 of the write clock domain crossing synchronization circuit 400 of FIG. Those skilled in the art will understand the operation of the synchronization circuit 700 based on the above description of the synchronization circuits 300 and 400. Therefore, for the sake of brevity, the detailed operation of the synchronization circuit 700 will not be described in detail herein.

[0084] Figure 8800 is a flow chart illustrating a clock domain crossing synchronization process 800 according to an embodiment of the present disclosure. Process 800 begins at 802 and generates a destination domain current buffer signal in the destination clock domain. The destination domain current buffer signal has a value indicating which of the first and second data buffers in the source clock domain is the current buffer to be used during the current data transfer cycle. The method proceeds to 804 and synchronizes the destination domain current buffer signal in the source clock domain to generate a synchronized destination domain current buffer signal. From 804, process 800 proceeds to 806 and generates a source domain current buffer signal based on the synchronized destination domain current buffer signal. The generated source domain current buffer signal has a value indicating the current buffer. From 806, process 800 proceeds to 808 and generates a source data transfer request signal in the source clock domain based on the source domain current buffer signal. The source data transfer request signal is associated with the current buffer indicated by the source domain current buffer signal. Then, process 800 proceeds to 810 and synchronizes the source data transfer request signal in the destination clock domain to generate the destination domain data transfer request signal. From 810, process 800 proceeds to 812 and delays transferring data between memories in the destination clock domain to a subsequent data transfer cycle when the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

[0085] Example embodiments of the present disclosure are described below. Other embodiments are apparent from the entire specification and claims submitted herein.

[0086] Example 1. A method comprising: generating a destination domain current buffer signal in a destination clock domain, the destination domain current buffer signal having a value indicating which of a first data buffer and a second data buffer in a source clock domain is a current buffer to be used during a current data transfer cycle; synchronizing the destination domain current buffer signal in a source clock domain to generate a synchronized destination domain current buffer signal; generating a source domain current buffer signal based on the synchronized destination domain current buffer signal, the generated source domain current buffer signal having a value indicating the current buffer; generating a source data transfer request signal in the source clock domain based on the source domain current buffer signal, the source data transfer request signal being associated with the current buffer indicated by the source domain current buffer signal; synchronizing the source data transfer request signal in the destination clock domain to generate a destination domain data transfer request signal; and when the current buffer associated with the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal, delaying the transfer of data between the memory in the destination clock domain and the current buffer to a subsequent data transfer cycle.

[0087] Example 2. The method of Example 1 further includes transferring data between the memory and the current buffer indicated by the destination domain data transfer request signal when the current buffer associated with the destination domain data transfer request signal corresponds to the current buffer indicated by the destination domain current buffer signal.

[0088] Example 3. The method of one of Examples 1 or 2, further comprising changing a state of a destination domain current buffer signal to indicate the start of a next data transfer cycle.

[0089] Example 4. The method of one of Examples 1 to 3, wherein the transmission of delayed data further comprises: storing a valid delayed destination domain data transmission request signal associated with one of the first data buffer and the second data buffer that is not the current buffer; and initiating the transmission of data between the memory and one of the first data buffer and the second data buffer that is not the current buffer when the destination domain current buffer signal changes state to indicate the start of a next data transmission cycle.

[0090] Example 5. The method of one of Examples 1 to 4, wherein initiating the transfer of the data comprises activating a memory request signal, and wherein the method further comprises changing a state of a destination domain current buffer signal in response to the memory request signal becoming active.

[0091] Example 6. The method of one of Examples 1 to 5, further comprising changing a value of a source domain current buffer signal in response to generating a source domain data transfer request signal.

[0092] Example 7. The method of one of Examples 1 to 6, wherein generating a source data transfer request signal includes generating a source domain write first buffer signal and a source domain write second buffer signal, and wherein generating a destination domain data transfer request signal includes generating a destination domain write first buffer signal and a destination domain write second buffer signal.

[0093] Example 8. The method of one of Examples 1 to 7, wherein generating a source data transfer request signal includes generating a source domain read first buffer signal and a source domain read second buffer signal, and wherein generating a destination domain data transfer request signal includes generating a destination domain read first buffer signal and a destination domain read second buffer signal.

[0094] Example 9. A clock domain crossing synchronization circuit, comprising: a destination current buffer generator in a destination clock domain, the destination current buffer generator being configured to generate a destination domain current buffer signal having a value indicating whether the first data buffer or the second data buffer is the current buffer to be used in the current data transfer cycle; a first synchronization circuit being configured to receive the destination current buffer signal and generate a corresponding synchronized destination current buffer signal in a source clock domain; a source current buffer generator being configured to generate a source domain current buffer signal based on the synchronized destination current buffer signal, wherein the source domain current buffer signal has a value indicating the current buffer; a source data transfer request generator being configured to receive the source domain current buffer signal and generate a corresponding synchronized destination current buffer signal based on the source domain current buffer signal. a signal to generate a source data transfer request signal in the source clock domain, the generated source data transfer request signal being associated with the current buffer indicated by the source domain current buffer signal; a second synchronization circuit being configured to receive the source data transfer request signal and generate a corresponding synchronized source data transfer request signal in the destination clock domain; and a destination data transfer request and delay generator in the destination clock domain being configured to receive the synchronized source data transfer request signal and the destination domain current buffer signal, the destination data transfer request and delay generator being configured to delay the transfer of data between the memory in the destination clock domain and the current buffer to a subsequent data transfer cycle when the current buffer indicated by the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

[0095] Example 10. The clock domain crossing synchronous circuit of Example 9, wherein each of the first synchronous circuit and the second synchronous circuit includes a plurality of flip-flops in series.

[0096] Example 11. The clock domain crossing synchronization circuit of one of Examples 9 or 10, wherein the synchronized destination domain data transfer request signal includes a write first buffer signal and a write second buffer signal, and wherein the destination data transfer request and delay generator includes: a first pulse generator coupled to receive the write first buffer signal and configured to generate a write first buffer pulse signal in response to the write first buffer signal; a second pulse generator coupled to receive the write second buffer signal and configured to generate a write second buffer pulse signal in response to the write second buffer signal; a first transfer request delay circuit having a first input coupled to receive the destination domain current buffer signal and a second input coupled to receive the write first buffer pulse signal, the first transfer request delay circuit configured to drive the delayed write first buffer signal to be valid in response to the write first buffer pulse signal becoming valid and the destination domain current buffer signal indicating that the second buffer is the current buffer in the destination clock domain; and a second transfer request delay circuit having a first input coupled to receive the destination domain current buffer signal and a second input coupled to receive the write second buffer pulse signal, the second transfer request delay circuit configured to drive the delayed write first buffer signal to be valid in response to the write second buffer pulse signal becoming valid. driving a delayed write second buffer signal to be valid when the destination domain current buffer signal indicates that the first buffer is the current buffer in the destination clock domain; and output logic coupled to the first pulse generator and the second pulse generator to receive the write first buffer pulse signal and the write second buffer pulse signal, and coupled to the first transfer request delay circuit and the second transfer request delay circuit to receive the delayed write first buffer signal and the delayed write second buffer signal, the output logic being configured to generate a first buffer write request pulse signal in response to either the write first buffer pulse signal or the delayed write first buffer signal being valid, and to generate a second buffer write request pulse signal in response to either the write second buffer pulse signal or the delayed write second buffer signal being valid; and selection circuitry coupled to the output logic and having a control input coupled to receive the destination domain current buffer signal, the selection circuit being configured to provide the first buffer write request pulse signal to the memory when the destination domain current buffer signal indicates that the first buffer is the current buffer in the destination clock domain, and to provide the second buffer write request pulse signal to the memory when the destination domain current buffer signal indicates that the second buffer is the current buffer in the destination clock domain.

[0097] Example 12. The clock domain crossing synchronization circuit of one of Examples 9 to 11, wherein each of the first pulse generator and the second pulse generator comprises: a flip-flop having an output terminal and having an input terminal coupled to receive a corresponding one of the write first buffer signal or the write second buffer signal; and an XOR gate having a first input terminal coupled to receive a corresponding one of the write first buffer signal or the write second buffer signal and a second input terminal coupled to the output terminal of the flip-flop, the XOR gate having an output terminal configured to generate a corresponding write first buffer pulse signal or a write second buffer pulse signal.

[0098] Example 13. The clock domain crossing synchronization circuit of one of Examples 9 to 12, wherein the output logic includes: a first OR gate having a first input coupled to receive a write first buffer pulse signal and a delayed write first buffer signal, and configured to generate a first buffer write request pulse signal at the output; and a second OR gate having a first input coupled to receive a write second buffer pulse signal and a delayed write second buffer signal, and configured to generate a second buffer write request signal at the output.

[0099] Example 14. The clock domain crossing synchronization circuit of one of Examples 9 to 13, wherein the selection circuit includes a multiplexer having a first input coupled to the output of the first OR gate, a second input coupled to the output of the second OR gate, an output coupled to the memory, and a control input coupled to receive the destination domain current buffer signal.

[0100] Example 15. The clock domain crossing synchronization circuit of one of Examples 9 to 14, wherein the destination current buffer generator includes: a trigger having an input and an output; and a multiplexer having a first input coupled to the output of the trigger, a second input receiving the output of the trigger through an inverter, an output coupled to the input of the trigger, and a control input coupled to receive a data transfer request signal from a destination data transfer request and a delay generator.

[0101] Example 16. A clock domain crossing synchronization circuit of one of Examples 9 to 15, wherein the source data transfer request signal includes a first buffer source write request signal and a second buffer source write request signal, and wherein the source data transfer request generator includes: a first trigger including an input terminal and having an output terminal configured to generate the first buffer source write request signal; a second trigger including an input terminal and having an output terminal configured to generate the second buffer source write request signal; and a logic circuit system configured to receive a data transfer current buffer signal and a source domain current buffer signal, and coupled to the input terminals of the first trigger and the second trigger, the logic circuit system being configured to provide a valid signal to the input terminal of the first trigger in response to the data transfer current buffer signal becoming valid and the source domain current buffer signal indicating that the first data buffer is the current buffer, and to provide a valid signal to the input terminal of the second trigger in response to the data transfer current buffer signal becoming valid and the source domain current buffer signal indicating that the second data buffer is the current buffer, and the logic circuit system being further configured to provide an invalid signal on the input terminals of the first trigger and the second trigger in response to the first buffer source data transfer request signal and the second buffer source data transfer request signal becoming valid, respectively.

[0102] Example 17. The clock domain crossing synchronization circuit of any one of Examples 9 to 16, wherein the logic circuit system includes: an inverter having an input coupled to receive the source domain current buffer signal and having an output; a first AND gate having a first input coupled to receive the write current buffer signal and a second input coupled to the output of the inverter, and having an output; a first multiplexer having a select input coupled to the output of the first AND gate, a first input coupled to the output of the first flip-flop, a second input, and an output coupled to the input of the first flip-flop; a second inverter having an output coupled to the second input of the first multiplexer and having an output coupled to the second input of the first multiplexer. an input terminal coupled to the output terminal of the first trigger to receive the first buffer source write request signal; a second AND gate having a first input terminal coupled to receive the write current buffer signal and a second input terminal coupled to receive the source domain current buffer signal, and having an output terminal; a second multiplexer having a selection input terminal coupled to the output terminal of the second AND gate, a first input terminal coupled to the output terminal of the second trigger, a second input terminal, and an output terminal coupled to the input terminal of the second trigger; and a third inverter having an output terminal coupled to the second input terminal of the second multiplexer and an input terminal coupled to the output terminal of the second trigger to receive the second buffer source write request signal.

[0103] Example 18. A clock domain crossing synchronization circuit of one of Examples 9 to 17, wherein the source domain current buffer generator includes: a first multiplexer having a first input terminal coupled to receive a synchronized destination current buffer signal, a second input terminal, an output terminal, and a control input terminal coupled to receive a start new data transfer signal; a trigger having an input terminal coupled to the output terminal of the first multiplexer and an output terminal on which the source domain current buffer signal is provided; a second multiplexer having a first input terminal coupled to the output terminal of the trigger, a second input terminal, an output terminal coupled to the second input terminal of the first multiplexer, and a control input terminal coupled to receive a write current buffer signal; and an inverter having an input terminal coupled to the output terminal of the trigger and an output terminal coupled to the second input terminal of the second multiplexer.

[0104] Example 19. An electronic system comprising a first-in-first-out (FIFO) memory in a destination clock domain; a dual buffer in a source clock domain, comprising a first data buffer and a second data buffer; and a clock domain crossing synchronization circuit, comprising: a destination current buffer generator in the destination clock domain, the destination current buffer generator being configured to generate a destination domain current buffer signal having a value indicating whether the first data buffer or the second data buffer is the current buffer to be used in a current data transfer cycle; a first synchronization circuit being configured to receive the destination current buffer signal and generate a synchronized destination current buffer signal in the source clock domain; a source current buffer generator in the source clock domain, the source current buffer generator being configured to generate a source domain current buffer signal based on the synchronized destination current buffer signal, wherein the source domain current buffer signal has a first value indicating the first data buffer and a second value indicating the second data buffer ; a source data transfer request generator, configured to receive a source domain current buffer signal and generate a source data transfer request signal in a source clock domain based on the source domain current buffer signal, the generated source data transfer request signal being associated with one of the first data buffer or the second data buffer corresponding to the value of the source domain current buffer signal; a second synchronization circuit, configured to receive the source data transfer request signal and generate a synchronized destination domain data transfer request signal in the destination clock domain; and a destination data transfer request and delay generator in the destination clock domain, configured to receive the synchronized source data transfer request signal and the destination domain current buffer signal, the destination data transfer request and delay generator being configured to delay the transfer of data between the memory in the destination clock domain and the current buffer to a subsequent data transfer cycle when the current buffer indicated by the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

[0105] Example 20. The electronic system of Example 19, wherein the source clock domain is a secure digital clock domain, and wherein the destination clock domain is a high-level hardware bus clock domain.

[0106] Although the present disclosure has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the present disclosure, will be apparent to those skilled in the art upon reference to this description. Accordingly, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A clock domain crossing synchronization circuit, characterized in that: include: a destination current buffer generator in a destination clock domain, the destination current buffer generator configured to generate a destination domain current buffer signal, the destination domain current buffer signal having a value indicating whether the first data buffer or the second data buffer is to be used as a current buffer in a current data transfer cycle; a first synchronization circuit configured to receive a destination current buffer signal and generate a corresponding synchronized destination current buffer signal in a source clock domain; a source current buffer generator configured to generate a source domain current buffer signal based on the synchronized destination current buffer signal, wherein the source domain current buffer signal has a value indicative of a current buffer; a source data transfer request generator configured to receive a source domain current buffer signal and generate a source data transfer request signal in a source clock domain based on the source domain current buffer signal, the generated source data transfer request signal being associated with a current buffer indicated by the source domain current buffer signal; a second synchronization circuit configured to receive a source data transfer request signal and generate a corresponding synchronized source data transfer request signal in a destination clock domain; as well as A destination data transfer request and delay generator in a destination clock domain is configured to receive a synchronized source data transfer request signal and a destination domain current buffer signal. The destination data transfer request and delay generator is configured to delay the transfer of data between the memory in the destination clock domain and the current buffer to a subsequent data transfer cycle when the current buffer indicated by the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal. 2 . The clock domain crossing synchronous circuit according to claim 1 , wherein each of the first synchronous circuit and the second synchronous circuit comprises a plurality of flip-flops connected in series.

3. The clock domain crossing synchronization circuit of claim 1 , wherein the synchronized destination domain data transfer request signal comprises a write first buffer signal and a write second buffer signal, and wherein the destination data transfer request and delay generator comprises: a first pulse generator coupled to receive the write first buffer signal and configured to generate a write first buffer pulse signal in response to the write first buffer signal; a second pulse generator coupled to receive the write second buffer signal and configured to generate a write second buffer pulse signal in response to the write second buffer signal; a first transfer request delay circuit having a first input coupled to receive a destination domain current buffer signal and a second input coupled to receive a write first buffer pulse signal, the first transfer request delay circuit being configured to drive the delayed write first buffer signal active in response to the write first buffer pulse signal becoming active and the destination domain current buffer signal indicating that the second buffer is the current buffer in the destination clock domain; a second transfer request delay circuit having a first input coupled to receive the destination domain current buffer signal and a second input coupled to receive the write second buffer pulse signal, the second transfer request delay circuit being configured to drive the delayed write second buffer signal active in response to the write second buffer pulse signal becoming active and the destination domain current buffer signal indicating that the first buffer is the current buffer in the destination clock domain; as well as an output logic coupled to the first pulse generator and the second pulse generator to receive a write first buffer pulse signal and a write second buffer pulse signal, and coupled to the first transfer request delay circuit and the second transfer request delay circuit to receive a delayed write first buffer signal and a delayed write second buffer signal, the output logic being configured to generate a first buffer write request pulse signal in response to the write first buffer pulse signal or the delayed write first buffer signal being valid, and to generate a second buffer write request pulse signal in response to the write second buffer pulse signal or the delayed write second buffer signal being valid; as well as A selection circuit is coupled to the output logic and has a control input coupled to receive a destination domain current buffer signal, the selection circuit being configured to provide a first buffer write request pulse signal to the memory when the destination domain current buffer signal indicates that the first buffer is the current buffer in the destination clock domain, and to provide a second buffer write request pulse signal to the memory when the destination domain current buffer signal indicates that the second buffer is the current buffer in the destination clock domain.

4. The clock domain crossing synchronization circuit of claim 3 , wherein each of the first pulse generator and the second pulse generator comprises: a flip-flop having an output terminal and having an input terminal coupled to receive a corresponding one of the write first buffer signal or the write second buffer signal; as well as An XOR gate has a first input terminal coupled to receive a corresponding one of the write first buffer signal or the write second buffer signal and a second input terminal coupled to the output terminal of the flip-flop, the XOR gate having an output terminal configured to generate a corresponding write first buffer pulse signal or a write second buffer pulse signal.

5. The clock domain crossing synchronization circuit according to claim 3 , wherein the output logic comprises: a first OR gate having a first input coupled to receive the write first buffer pulse signal and the delayed write first buffer signal and configured to generate a first buffer write request pulse signal at an output; as well as A second OR gate has a first input coupled to receive the write second buffer pulse signal and the delayed write second buffer signal and is configured to generate a second buffer write request signal at an output.

6. The clock domain crossing synchronization circuit of claim 5 , wherein the selection circuit comprises a multiplexer having a first input coupled to the output of the first OR gate, a second input coupled to the output of the second OR gate, an output coupled to the memory, and a control input coupled to receive the destination domain current buffer signal.

7. The clock domain crossing synchronization circuit of claim 1 , wherein the destination current buffer generator comprises: A trigger having an input terminal and an output terminal; as well as A multiplexer has a first input coupled to the output of the flip-flop, a second input receiving the output of the flip-flop through an inverter, an output coupled to the input of the flip-flop, and a control input coupled to receive a data transfer request signal from a destination data transfer request and a delay generator.

8. The clock domain crossing synchronization circuit of claim 1 , wherein the source data transfer request signal comprises a first buffer source write request signal and a second buffer source write request signal, and wherein the source data transfer request generator comprises: a first flip-flop including an input terminal and having an output terminal configured to generate a first buffer source write request signal; a second flip-flop including an input terminal and having an output terminal configured to generate a second buffer source write request signal; as well as A logic circuit system is configured to receive a data transfer current buffer signal and a source domain current buffer signal and is coupled to input terminals of a first flip-flop and a second flip-flop. The logic circuit system is configured to provide a valid signal to the input terminal of the first flip-flop in response to the data transfer current buffer signal becoming valid and the source domain current buffer signal indicating that the first data buffer is the current buffer, and to provide a valid signal to the input terminal of the second flip-flop in response to the data transfer current buffer signal becoming valid and the source domain current buffer signal indicating that the second data buffer is the current buffer. The logic circuit system is also configured to provide an invalid signal on the input terminals of the first flip-flop and the second flip-flop in response to the first buffer source data transfer request signal and the second buffer source data transfer request signal becoming valid, respectively.

9. The clock domain crossing synchronization circuit of claim 8, wherein the logic circuit system comprises: an inverter having an input coupled to receive the source domain current buffer signal and having an output; a first AND gate having a first input coupled to receive the write current buffer signal and a second input coupled to the output of the inverter, and having an output; a first multiplexer having a select input coupled to the output of the first AND gate, a first input coupled to the output of the first flip-flop, a second input, and an output coupled to the input of the first flip-flop; a second inverter having an output coupled to the second input of the first multiplexer and having an input coupled to the output of the first flip-flop to receive the first buffer source write request signal; a second AND gate having a first input coupled to receive the write current buffer signal and a second input coupled to receive the source domain current buffer signal, and having an output; a second multiplexer having a select input coupled to the output of the second AND gate, a first input coupled to the output of the second flip-flop, a second input, and an output coupled to the input of the second flip-flop; as well as The third inverter has an output terminal coupled to the second input terminal of the second multiplexer and an input terminal coupled to the output terminal of the second flip-flop to receive the second buffer source write request signal.

10. The clock domain crossing synchronization circuit according to claim 8, wherein the source domain current buffer generator comprises: a first multiplexer having a first input coupled to receive a synchronized destination current buffer signal, a second input, an output, and a control input coupled to receive a start new data transfer signal; a flip-flop having an input coupled to the output of the first multiplexer and an output at which a source domain current buffer signal is provided; a second multiplexer having a first input coupled to the output of the flip-flop, a second input, an output coupled to the second input of the first multiplexer, and a control input coupled to receive the write current buffer signal; as well as An inverter has an input coupled to the output of the flip-flop and an output coupled to the second input of the second multiplexer.

11. An electronic system, characterized in that: include: a first-in-first-out memory in the destination clock domain; A double buffer in the source clock domain, comprising a first data buffer and a second data buffer; as well as Clock domain spanning synchronous circuits, including: a destination current buffer generator in a destination clock domain, the destination current buffer generator configured to generate a destination domain current buffer signal, the destination domain current buffer signal having a value indicating whether the first data buffer or the second data buffer is to be used as a current buffer in a current data transfer cycle; a first synchronization circuit configured to receive a destination current buffer signal and generate a synchronized destination current buffer signal in a source clock domain; a source current buffer generator in a source clock domain, the source current buffer generator configured to generate a source domain current buffer signal based on the synchronized destination current buffer signal, wherein the source domain current buffer signal has a first value indicating the first data buffer and a second value indicating the second data buffer; a source data transfer request generator configured to receive a source domain current buffer signal and generate a source data transfer request signal in a source clock domain based on the source domain current buffer signal, the generated source data transfer request signal being associated with one of the first data buffer or the second data buffer corresponding to a value of the source domain current buffer signal; a second synchronization circuit configured to receive the source data transfer request signal and generate a synchronized destination domain data transfer request signal in the destination clock domain; and A destination data transfer request and delay generator in a destination clock domain is configured to receive a synchronized source data transfer request signal and a destination domain current buffer signal. The destination data transfer request and delay generator is configured to delay the transfer of data between the memory in the destination clock domain and the current buffer to a subsequent data transfer cycle when the current buffer indicated by the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

12. The electronic system of claim 11, wherein the source clock domain is a secure digital clock domain, and wherein the destination clock domain is a high-level hardware bus clock domain.

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