Semiconductor package

Abstract

A semiconductor package is provided herein. The semiconductor package may include a die attached to a substrate. The cover may also be attached to the substrate. The die includes a die nanowire, and the cap includes a cap nanowire. The nanowires may be formed over the entirety of the die or in a pattern. The cover may have a corresponding or symmetric overlay or pattern. In a semiconductor package, a die nanowire is coupled with a lid nanowire to provide improved heat dissipation, etc.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to nanowires for semiconductors, and more particularly to heat dissipation in a semiconductor package using nanowires. Background Art

[0002] A semiconductor package may include a die or chip enclosed under a lid or cap. The lid acts as a heat sink to dissipate heat. A thermal interface material (TIM) may be used between the die and the lid to help dissipate heat from the die to the lid. The TIM may degrade over time, including by retreating from the edges of the coverage applied by the TIM between the die and the lid. This retreat reduces the efficiency of heat dissipation. Furthermore, the retreat in the TIM coverage further concentrates heat in locations still covered by the TIM, thereby absorbing heat unevenly (compared to uncovered locations), which may further concentrate heat and accelerate degradation.

[0003] There is a need for new systems, apparatus, and methods for semiconductor packaging. The inventors have discovered numerous improvements in existing technologies and techniques that are the subject of the embodiments described herein. Through dedicated effort, ingenuity, and innovation, many of these deficiencies, challenges, and problems have been addressed by developing solutions included in the embodiments of the present disclosure, some examples of which are described in detail herein. Utility Model Content

[0004] Various embodiments described herein relate to systems, apparatus, and methods for nanowires in semiconductor packaging.

[0005] According to some embodiments of the present disclosure, an example semiconductor package is provided. The semiconductor package may include: a substrate; a die including a first side of the die and a second side of the die, wherein the first side of the die includes a formation of multiple die nanowires, wherein the second side of the die is coupled to the substrate; a lid including a first side of the lid facing the die, wherein the first side of the lid includes a formation of multiple lid nanowires; and wherein at least one die nanowire formation is coupled to at least one lid nanowire formation.

[0006] In some embodiments, the cover is composed of a cover top portion and a plurality of cover side portions, and the cover top portion is coupled to the cover side portions by glue.

[0007] In some embodiments, the at least one of the formation of the plurality of die nanowires is coupled to at least one of the formation of the plurality of cap nanowires, and wherein the coupling is aligned with a shared common axis.

[0008] In some embodiments, at least one of the plurality of formations of die nanowires is coupled to at least one of the plurality of formations of cap nanowires, and wherein the coupling is staggered, wherein the at least one of the plurality of formations of die nanowires has a different axis than the at least one of the plurality of formations of cap nanowires.

[0009] In some embodiments, the formation of the plurality of cap nanowires covers a first portion of the first side of the cap that is not the entire first side of the cap.

[0010] In some embodiments, the formation of the plurality of die nanowires covers a first portion of the first side of the die that is not the entire first side of the die.

[0011] In some embodiments, the first portion of the first side of the die covered by the formation of the plurality of die nanowires includes coverage of at least one die hotspot.

[0012] In some embodiments, the formation of the plurality of die nanowires is in a first pattern, wherein the formation of the plurality of cap nanowires is in a second pattern, and wherein the first pattern and the second pattern are complementary patterns.

[0013] In some embodiments, in addition to covering the die, the first side of the cover also covers one or more circuits.

[0014] In some embodiments, the formation of the plurality of cap nanowires is only on a first portion of the cap associated with the die.

[0015] According to some embodiments of the present disclosure, an example method is provided. The method may be a method of manufacturing a semiconductor package, comprising: growing a formation of a plurality of die nanowires on a first side of a die; growing a formation of a plurality of cap nanowires on a first side of a lid; attaching the die to a substrate; attaching the lid to the substrate, including coupling the formation of the plurality of die nanowires to the formation of the plurality of cap nanowires.

[0016] In some embodiments, the cover includes a cover top portion and a plurality of cover side portions, and the cover top portion is coupled to the cover side portions by glue.

[0017] In some embodiments, at least one formation of die nanowires is coupled to at least one formation of cap nanowires, and the coupling is aligned with a shared common axis.

[0018] In some embodiments, the formation of at least one die nanowire is offset from the formation of at least one cap nanowire, wherein the formation of the at least one die nanowire has a different axis than the formation of the at least one cap nanowire.

[0019] In some embodiments, the formation of the plurality of cap nanowires covers a first portion of the first side of the cap that is not the entire first side of the cap.

[0020] In some embodiments, the formation of the plurality of die nanowires covers a first portion of the first side of the die that is not the entire first side of the die.

[0021] In some embodiments, the first portion of the first side of the die covered by the formation of the plurality of die nanowires includes coverage of at least one die hotspot.

[0022] In some embodiments, the formation of the plurality of die nanowires is in a first pattern, wherein the formation of the plurality of cap nanowires is in a second pattern, and wherein the first pattern and the second pattern are complementary patterns.

[0023] In some embodiments, the first side of the cover covers one or more circuits in addition to the die.

[0024] In some embodiments, the formation of the plurality of cap nanowires is located only on a first portion of the cap associated with the die.

[0025] The above summary is provided merely for the purpose of outlining some example embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it will be understood that the above embodiments are merely examples and should not be construed as limiting the scope or spirit of the present disclosure in any way. It will also be understood that in addition to those embodiments summarized here, the scope of the present disclosure also includes many potential embodiments, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Having thus generally described certain example embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0027] Figure 1A illustrates a cross-sectional view of an example block diagram of a semiconductor package with a detached lid according to one or more embodiments of the present disclosure;

[0028] Figure 1B illustrates a cross-sectional view of an example block diagram of a semiconductor package with an attached lid according to one or more embodiments of the present disclosure;

[0029] Figure 2A-2C illustrates a cross-sectional diagram of an example block diagram of a cap nanowire and a die nanowire according to one or more embodiments of the present disclosure;

[0030] Figures 3A-3Dillustrates a diagram of an example block diagram of a die and lid according to one or more embodiments of the present disclosure;

[0031] Figure 4A 、 4B illustrates a cross-sectional view of an example block diagram of a cover having a separated top and sides according to one or more embodiments of the present disclosure;

[0032] Figure 5 illustrates a flow chart of operations for manufacturing an exemplary semiconductor package according to one or more embodiments of the present disclosure;

[0033] Figure 6 a flowchart illustrating operations for fabricating an exemplary die in accordance with one or more embodiments of the present disclosure; and

[0034] Figure 7 A flow chart illustrating operations for manufacturing an exemplary lid in accordance with one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0035] Some embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. Indeed, the various embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0036] As used herein, the term "comprising" means including, but not limited to, and should be interpreted in the manner commonly used in the patent context. The use of broader terms such as "comprises," "includes," and "having" should be understood to provide support for narrower terms such as "consisting of," "consisting essentially of," and "consisting essentially of."

[0037] The phrases "in various embodiments," "in one embodiment," "according to one embodiment," "in some embodiments," etc. generally indicate that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, these phrases do not necessarily refer to the same embodiment).

[0038] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0039] If the specification states that a component or feature "may," "could," "might," "should," "would," "preferably," "likely," "typically," "optionally," "for example," "often," or "might" (or other such language) be included or have a characteristic, that particular component or feature is not required to be included or have that characteristic. Such components or features may be optionally included in some embodiments, or may also be excluded.

[0040] The term "circuitry," as used herein with respect to components of a system or device, should be understood to include specific hardware configured to perform the functions associated with the specific circuitry described herein. The term "circuitry" should be broadly interpreted to include hardware and, in some embodiments, software for configuring the hardware. For example, in some embodiments, a "circuitry" may include processing circuitry, communication circuitry, input / output circuitry, and the like. In some embodiments, other elements may provide or supplement the functionality of a particular circuit.

[0041] Overview

[0042] The present disclosure relates to systems, devices, and methods for semiconductor packaging that use nanowires for improved thermal management. Heat generated by the die during thermal cycling can cause degradation or failure of the semiconductor package or components and / or circuits within the semiconductor package. Dissipating heat from the semiconductor package improves the performance and lifespan of the semiconductor package.

[0043] A semiconductor package may include a die coupled to a substrate and a lid coupled to the substrate, the lid covering the die and other components and / or circuitry of the semiconductor package. Nanowires may be formed individually on the die and on the lid such that when the die and the lid are each coupled to the substrate, the die nanowires couple with the lid nanowires. The die nanowires and the lid nanowires may be grown in a plurality of formations, which may present a pattern. The corresponding formations of the die nanowires and the lid nanowires may be aligned and coupled. When coupled, the die nanowires form mechanical and electrical contact with the lid nanowires, which allows them to couple and allows for improved heat dissipation. An example of a semiconductor package is a ball grid array, which may then be mounted to or used in an electronic device or another system.

[0044] The nanowires can be arranged in a pattern that includes a first pattern on the die and a second (complementary) pattern on the lid. An example pattern can be a ring or a series of rings. Alternatively, the pattern can be based on a characteristic of the die, such as the location of one or more hot spots. The location of the hot spot can have a nanowire associated with the hot spot that is configured to conduct heat away from the hot spot. The pattern can also have one or more portions of the pattern that do not include nanowires (e.g., spaces between formations of nanowires).

[0045] Nanowires improve reliability and thermal performance. Given that semiconductor packages utilize TIMs, the nanowires described herein can result in improved thermal dissipation of heat that is an order of magnitude greater than that achieved using TIMs. Even when misaligned, the formation of nanowires provides increased thermal dissipation compared to semiconductor packages using TIMs.

[0046] Example Systems and Apparatus

[0047] Embodiments of the present disclosure herein include systems and apparatus for nanowires for semiconductor packaging as described herein, which can be implemented in various embodiments. Exemplary embodiments include a semiconductor package having a lid and a die, wherein the lid nanowires are grown on the lid and the die nanowires are grown on the die. When the lid is attached to a substrate to which the die is attached, the lid nanowires couple with the die nanowires. The coupled lid nanowires and die nanowires allow for improved heat dissipation in the semiconductor package, among other things.

[0048] Figure 1A A cross-sectional view of an example block diagram of a semiconductor package with a detached lid according to one or more embodiments of the present disclosure is illustrated. The semiconductor package 100 may include a die 110, a lid 120, and a substrate 130. The lid 120 is illustrated as being detached from the substrate 130. The lid 120 detached from the substrate 130 illustrates the lid nanowires 122A-D detached from the die nanowires 112A-D.

[0049] The die 110 has a first side 114A facing the lid 120 and a second side 114B facing the substrate 130. The first side 114A of the die 110 has a plurality of nanowire formations 112A-D. The second side 114B of the die 110 has a plurality of solder balls 116, copper pillars, etc., that couple the die 110 to the substrate 130. For example, the solder balls can be coupled to one or more signal pads 136A-C of the substrate. The nanowires on the die 110 are die nanowires. It will be understood that some of the figures illustrate solder balls 116, and alternative embodiments may use copper pillars, etc.

[0050] Lid 120 may include a top portion and multiple side portions. The top portion may have a first side 124A facing die 110 and substrate 120. Lid 120's top portion 124A may have a plurality of nanowire formations 122A-122D. The nanowires on lid 120 are lid nanowires. The lid may be a plated metal core. For example, lid 120 may have a copper core with another metal to prevent oxidation.

[0051] The formation of nanowires (e.g., 112A-112D, 122A-122D) may include several nanowires grown together. Although the drawings may illustrate the formation of nanowires 112 as including a few nanowires, it should be understood that the drawings are not to scale and the number of nanowires in the formation of nanowires 112 may be based on the area of the formation of nanowires 112 on the die 110. The nanowires may be made of a metal such as copper.

[0052] For example, the substrate 130 can be a laminate substrate, and the substrate 130 can include one or more signal pads 136 and / or other circuits. The cover 120 can be attached to the substrate 130 to cover one or more other circuits (e.g., ICs, electrical components, etc.) in addition to the signal pads 136. Utilizing nanowires to dissipate heat generated by the die 110 can also provide improvements to the lifespan of these other circuits by reducing the temperature to which they are exposed. A solder mask can cover the substrate 130 and be removed in various operations, such as at and when connecting solder balls 116. In various embodiments, the substrate 130 can be a wafer or panel from which the semiconductor package 100 is to be separated. For example, a plurality of semiconductor packages 100 can be manufactured together before being separated from a common wafer or panel.

[0053] Figure 1B A cross-sectional view of an example block diagram of a semiconductor package with an attached lid according to one or more embodiments of the present disclosure is illustrated. When the lid 120 is attached to the substrate 130, the die nanowires are coupled to the lid nanowires. As shown, the first formation 112A of the die nanowires is coupled to the first formation 122A of the lid nanowires; the second formation 112B of the die nanowires is coupled to the second formation 122B of the lid nanowires; the third formation 112C of the die nanowires is coupled to the third formation 122C of the lid nanowires; and the fourth formation 112D of the die nanowires is coupled to the fourth formation 122D of the lid nanowires. In various embodiments, when the lid 120 is attached to the substrate 130, the distance from the first side 124A of the lid to the first side 114A of the die can be 50 microns. In various embodiments, the lid 120 can be attached to the substrate 130 using glue.

[0054] Figure 2A-2CA cross-sectional view of an example block diagram of a cover nanowire and a die nanowire according to one or more embodiments of the present disclosure is illustrated. Specifically, a die nanowire formation 112 and a cover nanowire formation 122 are illustrated. The die nanowire formation 112 can have a first height 122H on a first axis 212, and the cover nanowire formation 122 can also have the same or different heights 222H on a second axis 222. The axis can be referred to as a central axis. The width of the nanowire formation (e.g., 112, 212) can be 5 to 10 microns wide, but even if the coupling of the nanowire formations is misaligned (where the axis of the cover nanowire is not aligned with the axis of the die nanowire), it allows for improved heat dissipation. The distance or gap between the die and the cover of the semiconductor package can be less than the first height 122H and the second height 222H, so that when the cover 120 is attached to the substrate 130, the cover nanowire 122 will contact the die nanowire 112 to form a mechanical connection and an electrical connection.

[0055] Figure 2A A cross-sectional diagram of an example block diagram of a die nanowire formation 112 separated from a cap nanowire formation 122 according to one or more embodiments of the present disclosure is shown. As shown, when the die nanowire formation 112 is separated from the cap nanowire formation 122, axes 212 and 222 are aligned. When the die nanowire formation 112 and the cap nanowire formation 122 are coupled, the nanowires couple to create a mechanical connection as well as an electrical connection.

[0056] Figure 2B A cross-sectional diagram of an example block diagram of a formation of die nanowires 112 coupled to a formation of cap nanowires 122 with axes 212 aligned with 222, according to one or more embodiments of the present disclosure, is illustrated. When axes 212 and 222 are aligned, the coupling can allow for maximum heat transfer through the coupling.

[0057] Figure 2C A cross-sectional diagram of an example block diagram illustrating separation of the die nanowire formation 112 from the cap nanowire formation 122 in accordance with one or more embodiments of the present disclosure is shown with the axes 212 and 222 misaligned. When the axes 212 and 222 are misaligned, but still coupled as shown, heat transfer through misaligned coupling is still improved.

[0058] Figures 3A-3DA diagram illustrating an example block diagram of a die and a lid according to one or more embodiments of the present disclosure is shown. The die 110 and the lid 120 can have patterns of nanowires. The pattern of nanowires on the lid 120 can be on a first portion of the lid 120 associated with the die 110. The dimensions of the first portion of the lid 120 can be determined based on the dimensions of the first side 114A of the die 110. The pattern of nanowires can be formed by a formation of die nanowires 112 and / or a formation of lid nanowires 122. Figures 3A-3D Each of the figures illustrates a die (e.g., 310A-310D) and a lid (e.g., 320A-320D). The lid (e.g., 320A-320D) is larger than the die and can include lid portions (e.g., 326A-326D) having dimensions corresponding to the dimensions of the die (e.g., 310A-310D). The die and lid portions can be matched in size so that the die nanowires connect to the lid nanowires, including having a symmetrical pattern on each. In various embodiments, the pattern can have nanowires at locations on the die that have one or more hot spots.

[0059] Figure 3A comprising a die 310A having nanowires covering the entire die 310A, and Figure 3A Also included is a cover 320A having a first portion 326A with nanowires covering the entirety of the first portion 326A.

[0060] Figure 3B including a die 310B having nanowires in a pattern of four squares, and Figure 3B Also included is a cover 320B having a first portion 326B with nanowires in a matching pattern of four squares.

[0061] Figure 3C including a die 320C having nanowires in a donut-shaped pattern, and Figure 3C Also included is a cover 320C having a first portion 326C having a matching pattern of nanowires in a donut shape.

[0062] Figure 3D The die 310D includes nanowires in rectangular and square patterns, and Figure 3D Also included is a lid 320D having a first portion 326D with nanowires in a matching pattern of rectangles and squares. The patterns on the die and lids 310D and 320D match so that when the lid 320D is flipped over to cover the die 310D, the patterns will align.

[0063] The patterns on the die and the lid can include areas and / or portions that are cleared to not have nanowires. Such areas and / or portions can be cleared because the die can include circuits and / or areas or portions that do not generate heat to be dissipated or do not generate as much heat to be dissipated.

[0064] Figure 4A 、 4B A cross-sectional view of an example block diagram of a lid having separate top and side portions according to one or more embodiments of the present disclosure is illustrated. In various embodiments, the lid 400 can include a top portion 442 and multiple side portions 444A, 444B. It will be understood that the lid 420 can have one side for each of its outer sides, such as having four side portions 444 for a lid 420 having a square shape. Thus, after the nanowires have been formed on the top portion of the lid, the lid can be assembled from the corresponding portions of the lid. In various embodiments, the nanowires can be formed using a deposition liquid that can be removed by centrifugal force by rotating the top portion of the lid. Thus, in various embodiments, assembling the lid from portions can allow for an easier way to form the nanowires. It will be understood that the lid 420 can have a shape other than a square, such as a rectangle or a shape with more or less than four sides.

[0065] Figure 4A The lid side portions 444A, 444B are shown separated from the top portion 442. The top portion may have formations 122A-D of lid nanowires formed on the lid top portion 442 prior to attaching the lid side portions 444A, 444B.

[0066] Figure 4B The cover 420 is shown having a cover top portion 442 attached to side portions 444A, 444B. The attachment may use an adhesive, such as glue.

[0067] It should be readily understood that the embodiments of the systems and apparatus described herein may be configured in various additional and alternative ways besides those explicitly described herein.

[0068] Example Method

[0069] Figure 5 A flowchart illustrating operations for fabricating an exemplary semiconductor package is shown in accordance with one or more embodiments of the present disclosure.

[0070] At operation 502, a die nanowire is created on the die. Figure 6 The various operations described create die nanowires 112 on die 110 .

[0071] At operation 504, a cap nanowire is created on the cap. Figure 7 The various operations described create die nanowires 112 on die 110 .

[0072] At operation 506, the die is attached to the substrate. Attaching the die 110 to the substrate 130 may include positioning the die 110 in alignment with the substrate 130 such that the solder balls 116 on the second side 114B of the die 110 are aligned with the signal pads 136 on the first side 134A of the substrate 134. If the substrate 130 includes a solder mask layer over the signal pads 134, such as to prevent oxidation of the metal of the signal pads 134, the solder mask layer may be removed to allow the solder balls 116 to couple to the signal pads 134. Once positioned, the die 110 and substrate 130 may be coupled by melting solder. An underfill material may be applied to fill the space around the solder and between the die 110 and the substrate 130. For example, the underfill may be an epoxy that fills the space between the die 110 and the substrate 130 through capillary action.

[0073] In various embodiments, placing the die 110 can include flipping the die 110 so that the second side 114B of the die 110 faces the first side of the substrate 130. This can include picking up the die 110 with a flip-chip fixture. To use a flip-chip fixture, the die 110 may need to be sufficiently rigid so as not to crack due to the thickness of the die 110. In various embodiments, the die nanowire formation 112 can provide increased rigidity. This can include a pattern of die nanowires 112 covering all or a majority of the die 110.

[0074] At operation 508, the lid is attached to the substrate, thereby coupling the die nanowires and the lid nanowires. Attaching the lid to the substrate includes aligning the lid nanowire formations with their corresponding die nanowire formations. This can include aligning complementary and / or symmetrical nanowire patterns on the die 110 and the lid 120. The lid 120 can be placed onto the substrate 130, and the lid nanowire formations can be brought to the die nanowire formations. The lid 120 can be attached to the substrate 130 by glue. In various embodiments, attaching by glue can include depositing glue around the substrate 130 at locations where the side portions of the lid 120 contact the substrate 130. The semiconductor package can then be heated to, for example, 150-200 degrees Celsius to cure the glue. Additionally, pressure can be applied to the semiconductor package or the portion of the semiconductor package having the nanowires to anneal the die nanowires and the lid nanowires together. Annealing and curing of the glue can occur simultaneously, or can occur at separate times, such as sequentially.

[0075] Figure 6A flow chart of operations for manufacturing an exemplary die according to one or more embodiments of the present disclosure is illustrated. Creating die nanowires 112 on die 110 can include preparing die 110 from multiple dies on a wafer, panel, or the like. For example, the wafer can be bumped to add solder bumps and can be ground to a desired thickness. The wafer may require a handler to be attached after grinding to allow handling of the wafer. For example, the solder bumps are on the second side 114B of the die, and the die nanowires 112 will be grown on the first side 114A of the die 110, so the wafer is handled by at least flipping the wafer to expose the first side 114A of the die 110 for growing the formation of die nanowires 112.

[0076] The second side of the wafer is bumped at operation 602. Multiple dies may be prepared together on the wafer including die 110. Bumping the bottom side of the wafer including second side 114B with solder bumps creates solder balls 116A.

[0077] At operation 604, a first side of the wafer is ground. The wafer may have a standard size that may require a reduced thickness for use in semiconductor packaging. The wafer including die 110 may be ground to a first thickness. In various embodiments, grinding may include flipping the wafer over and performing top grinding to remove a portion of the wafer.

[0078] At operation 606, a handler is attached to the wafer. The wafer including the die 110 may require increased rigidity for handling after being ground to a reduced thickness. A front handler can be applied to the face of the wafer where the bumps are to be formed. The front handler can be a first material (e.g., a heat-deactivated glue or a tape with glue) that can add rigidity while absorbing the topology of the solder bumps. The handler can be a temporary layer that can be removed later. Additionally or alternatively, a sawing tape can be added to the wafer for use in a subsequent singulation step that includes sawing individual die from the wafer. If a handler of the first material is added, the handler can be disengaged to add the sawing tape to one or more portions of the wafer.

[0079] At operation 608, a nanowire seed layer is applied to the first side of the die. The nanowire seed layer is applied to the top portion of the wafer (including the first side 114A of the die 110) and can be applied over the entirety of the die 110 or can be applied in one or more patterns. This can create a pattern, such as growing nanowires on hot spots or areas targeted for heat dissipation. In various embodiments, the die 110 is part of a wafer and the nanowire seed layer can be applied simultaneously.

[0080] At operation 610, die nanowires are grown from the nanowire seed layer. Die nanowires 112 are grown on the first side 114A of the die 110 from the nanowire seed layer. The growth of the nanowires may include one or more electroplating operations. The growth of the nanowires may also include applying a photoresist layer. The photoresist layer may have one or more openings, or one or more openings may be created therein after the photoresist layer is applied. The nanowires may be grown in the openings of the photoresist layer. These openings may be formed into one or more patterns, which may allow the nanowires to be grown in one or more patterns. In various embodiments, the die 110 is part of a wafer, and multiple dies having nanowires may be grown simultaneously.

[0081] In embodiments where multiple dies are part of a wafer, the dies 110 may be separated from the wafer by one or more singulation operations. This may include sawing the wafer using a saw along a sawing tape applied to the wafer.

[0082] Figure 7 A flow chart illustrating operations for fabricating an exemplary lid according to one or more embodiments of the present disclosure is shown. Creating lid nanowires 122 on the lid 120 may include applying a nanowire seed layer to the lid 120 and growing the lid nanowires from the seed layer. In various embodiments where the lid 420 includes a top portion 442 that is separate from side portions 444, one or more lid top portions 442 may be prepared by growing the lid nanowires 122 on the top portion 442 before the corresponding side portions 444 are attached to the top portion(s) 442. Then, after the lid nanowires 122 have been grown on the top portion 442, the corresponding lid side portions 444 are attached to the lid top portion 442.

[0083] At operation 702, a nanowire seed layer is applied to the lid 120. The lid 120 may include applying the nanowire seed layer. Applying the nanowire seed layer may include covering all areas of the lid in a pattern, or removing one or more portions of the seed layer after applying the seed layer. In various embodiments, the pattern may include applying the seed layer in one or more shapes. In various embodiments, the pattern may include applying the seed layer only to hot spots.

[0084] At operation 704, cap nanowires are grown from the nanowire seed layer. The nanowires are grown on the nanowire seed layer, which may include electroplating. The growth of the nanowires may also include applying a photoresist layer. The photoresist layer may have one or more openings, or one or more openings may be created therein after the photoresist layer is applied. The nanowires may be grown in the openings of the photoresist. These openings may be formed into one or more patterns, which may allow the nanowires to be grown in one or more patterns.

[0085] At operation 706, the side portions of the lid are attached to the top portion of the lid. In various embodiments where the lid has multiple portions, subsequent steps may include attaching one or more side portions of the lid to the portion of the lid having the nanowires. For example, the attachment may be accomplished using one or more adhesives.

[0086] Summarize

[0087] The operations and / or functions of the present disclosure have been described herein, such as in flow charts. Although the operations and / or functions are illustrated in a particular order in the accompanying drawings, this should not be construed as requiring that such operations and / or functions be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed in order to achieve the desired results. In some cases, it may also be advantageous to perform the operations and / or functions in an alternative order. In some cases, the acts detailed in the claims can be performed in a different order and still achieve the desired results. Therefore, although specific embodiments of the subject matter have been described, other embodiments are within the scope of the subsequent claims.

[0088] Although this specification contains many specific embodiments and implementation details, these should not be interpreted as limitations on the scope of any disclosure or possible claim, but rather as descriptions of features specific to particular disclosed embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described in the above description as acting in certain combinations, or even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to sub-combinations or variations of sub-combinations.

[0089] Although this detailed description sets forth certain embodiments of the disclosure, the appended claims cover other embodiments of the disclosure according to various modifications and improvements that differ from the described embodiments.

Claims

1. A semiconductor package, characterized in that: include: substrate; a die comprising a first side of the die and a second side of the die, wherein the first side of the die comprises a formation of a plurality of die nanowires, wherein the second side of the die is coupled to a substrate; a lid comprising a first side of the lid facing the die, wherein the first side of the lid comprises a formation of a plurality of lid nanowires; and Wherein the formation of at least one die nanowire is coupled to the formation of at least one cap nanowire.

2. The semiconductor package according to claim 1, wherein The cover comprises a cover top portion and a plurality of cover side portions, and the cover top portion is coupled to the cover side portions by glue.

3. The semiconductor package according to claim 1, wherein Wherein the at least one of the formations of the plurality of die nanowires is coupled to at least one of the formations of the plurality of cap nanowires, and wherein the coupling is aligned with a shared common axis.

4. The semiconductor package according to claim 1, wherein wherein at least one of the plurality of formations of die nanowires is coupled to at least one of the plurality of formations of cap nanowires, and wherein the coupling is staggered, wherein the at least one of the plurality of formations of die nanowires has a different axis than the at least one of the plurality of formations of cap nanowires.

5. The semiconductor package according to claim 1, wherein The formation of the plurality of cap nanowires covers a first portion of the first surface of the cap, the first portion not being the entire first surface of the cap.

6. The semiconductor package according to claim 1, wherein The formation of the plurality of die nanowires covers a first portion of the first side of the die, the first portion not being the entire first side of the die.

7. The semiconductor package according to claim 6, wherein: Wherein the first portion of the first side of the die covered by the formation of the plurality of die nanowires includes coverage of at least one die hotspot.

8. The semiconductor package according to claim 1, wherein wherein the formation of the plurality of die nanowires is in a first pattern, wherein the formation of the plurality of cap nanowires is in a second pattern, and wherein the first pattern and the second pattern are complementary patterns.

9. The semiconductor package according to claim 1, wherein In addition to covering the die, the first side of the cover also covers one or more circuits.

10. The semiconductor package according to claim 9, wherein Wherein the formation of the plurality of cap nanowires is only on a first portion of the cap associated with the die.

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