Vehicle-mounted multi-camera synchronization system and vehicle

Abstract

The utility model discloses a vehicle-mounted multi-camera synchronization system and a vehicle, and the system comprises a central processing unit, the central processing unit is in data connection with a plurality of deserializers, each deserializer is connected with an image sensor through a serializer, each deserializer is in signal connection with a same first clock generator, and each first clock generator is in signal connection with a second clock generator; each deserializer is in signal connection with the same second clock generator; wherein the first clock generator is used for providing a local clock source for each deserializer, and the second clock generator is used for providing a frame synchronization signal for each image sensor. According to the utility model, high-precision frame synchronization of a plurality of cameras can be realized through hardware design.

Description

Technical Field

[0001] The utility model relates to the technical field of vehicle hardware, and in particular to a vehicle-mounted multi-camera synchronization system and a vehicle. Background Art

[0002] Currently, image synchronization between automotive cameras mostly relies on a single deserializer solution, typically used to synchronize two to four cameras, such as those for surround, forward, or forward-looking cameras. This solution cannot achieve precise video frame synchronization between different deserializers (e.g., for surround, forward, rear, and side cameras) in hardware. Consequently, the multi-source perception data received by the intelligent driving domain controller cannot be precisely synchronized, affecting the image stitching and fusion accuracy of high-level intelligent driving systems. Utility Model Content

[0003] In response to the above technical problems, the present invention provides a vehicle-mounted multi-camera synchronization system and a vehicle, which can achieve high-precision frame synchronization of multiple cameras through hardware design.

[0004] A first aspect of the present invention provides a vehicle-mounted multi-camera synchronization system, comprising:

[0005] A central processing unit, wherein the central processing unit is data-connected to multiple deserializers, each deserializer is connected to an image sensor via a serializer, each deserializer is signal-connected to the same first clock generator, and each deserializer is signal-connected to the same second clock generator; wherein the first clock generator is used to provide a local clock source for each deserializer, and the second clock generator is used to provide a frame synchronization signal for each image sensor.

[0006] Optionally, as an implementation manner of the present invention, the deserializer includes a phase-locked loop circuit, and the phase-locked loop circuit is used to perform phase-locked adjustment on the local clock source emitted by the first clock generator.

[0007] Optionally, as an implementation manner of the present invention, the first clock generator sends out multiple first clock signals of the same source.

[0008] Optionally, as an implementation manner of the present utility model, the frequency of the first clock signal is set to 25 MHz.

[0009] Optionally, as an embodiment of the present invention, the deserializer includes a frame synchronization input pin, which is used to receive a frame synchronization signal emitted by the second clock generator; the frame synchronization signal is sent to the serializer through the reverse channel of the serial bus, and is sent to the image sensor through the output pin of the serializer.

[0010] Optionally, as an implementation manner of the present invention, the frequency of the frame synchronization signal is consistent with the acquisition frequency of the image sensor.

[0011] Optionally, as an implementation manner of the present invention, the serializer includes an internal register, and the internal register is used to configure the frame synchronization signal.

[0012] A second aspect of the present invention provides a vehicle-mounted multi-camera synchronization system, comprising: a central processing unit, wherein the central processing unit is data-connected to multiple deserializers, each deserializer is connected to an image sensor via a serializer, and each of the deserializers is signal-connected to the same third clock generator, wherein the third clock generator is used to provide a local clock source for each deserializer and to provide a frame synchronization signal for each image sensor.

[0013] Optionally, as an implementation manner of the present invention, the third clock generator includes a frequency divider or a phase-locked loop circuit, which is used to generate the local clock source or frame synchronization signal.

[0014] A third aspect of the present invention provides a vehicle, wherein the vehicle is equipped with the vehicle-mounted multi-camera synchronization system described in any one of the first aspect or the second aspect.

[0015] This utility model uses a single first clock generator to provide a unified local clock source for multiple deserializers, ensuring clock synchronization between them. Simultaneously, a single second clock generator provides a unified frame synchronization signal for each image sensor, enabling video frame synchronization across multiple cameras. This design effectively improves the synchronization accuracy of multi-camera systems, avoiding video frame desynchronization issues caused by time differences between different deserializers and cameras, and enhancing the reliability and accuracy of multi-camera data fusion in intelligent driving systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a hardware solution for synchronizing multiple on-board cameras in the existing technology.

[0017] Figure 2 It is a structural diagram of an embodiment of the present utility model.

[0018] Figure 3 This is a structural diagram of another embodiment of the present invention.

[0019] Description of the drawings: 1. Central processing unit; 2. First deserializer; 3. Second deserializer; 4. First serializer; 5. Second serializer; 6. Third serializer; 7. Fourth serializer; 8. First image sensor; 9. Second image sensor; 10. Third image sensor; 11. Fourth image sensor; 12. First clock generator; 13. Second clock generator; 14. Third clock generator. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0021] It should be understood that the terms "first," "second," and "third," etc. in the claims, specifications, and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprising" used in the specifications and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their collections. It should also be understood that the terms used in this disclosure specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure.

[0022] The existing vehicle-mounted multi-camera synchronization hardware solution is as follows: Figure 1 As shown, the system primarily connects to the central processing unit (SoC) via multiple deserializers. Each deserializer connects to multiple serializers, which in turn connect to cameras (image sensors). Each deserializer uses an independent crystal oscillator (CLK) to provide a clock signal, ensuring synchronization of data processing within the deserializer. However, this system only synchronizes cameras within a single deserializer and cannot guarantee precise synchronization across multiple deserializers. This can result in incomplete synchronization of camera video frames between different deserializers, impacting the performance of advanced intelligent driving systems.

[0023] Based on this, an embodiment of the present invention provides a vehicle-mounted multi-camera synchronization system, including a central processor 1, wherein the central processor 1 is data-connected to multiple deserializers, each deserializer is connected to an image sensor through a serializer, and each deserializer is signal-connected to the same first clock generator 12, and each deserializer is signal-connected to the same second clock generator 13; wherein the first clock generator 12 is used to provide a local clock source for each deserializer, and the second clock generator 13 is used to provide a frame synchronization signal for each image sensor.

[0024] Specifically, refer to Figure 2 The vehicle-mounted multi-camera synchronization system includes multiple image sensors for capturing image data, such as a first image sensor 8 , a second image sensor 9 , a third image sensor 10 and a fourth image sensor 11 .

[0025] Each image sensor converts parallel image data into serial data via its corresponding serializer. Image data from first image sensor 8 and second image sensor 9 is converted into serial data via first serializer 4 and second serializer 5 and transmitted to first deserializer 2. Image data from third image sensor 10 and fourth image sensor 11 is converted into serial data via third serializer 6 and fourth serializer 7 and transmitted to second deserializer 3.

[0026] First deserializer 2 receives serial data from first serializer 4 and second serializer 5 and decodes it into parallel data. Second deserializer 3 receives serial data from third serializer 6 and fourth serializer 7 and decodes it into parallel data. The decoded image data is transmitted to central processing unit 1 (SoC) via a control line.

[0027] The first clock generator 12 can be configured as an oscillator (OSC) to generate a unified local clock signal and provide it to the first deserializer 2 and the second deserializer 3, ensuring clock synchronization between the deserializers. The second clock generator 13 issues a frame synchronization signal (FSYNC) and transmits the synchronization signal to the serializer through the input pins of the first deserializer 2 and the second deserializer 3. The signal is then transmitted to the image sensor, ensuring the synchronization of image frames captured by all image sensors.

[0028] The central processor 1 receives and processes the image data from the first deserializer 2 and the second deserializer 3, and performs subsequent processing or fusion according to the intelligent driving requirements.

[0029] Because all deserializers (such as the first deserializer 2 and the second deserializer 3) use the same clock source (OSC) and all image sensors use the same frame synchronization signal (FSYNC), the system ensures that the image data captured by multiple image sensors and transmitted to the central processor 1 is highly synchronized in time. This synchronization is achieved through hardware-level clock and frame synchronization signals, greatly reducing data inconsistencies caused by time differences and providing a foundation for high-precision data fusion and processing.

[0030] Furthermore, as an implementation manner of the present invention, the deserializer includes a phase-locked loop circuit, and the phase-locked loop circuit is used to perform phase-locked adjustment on the local clock source sent by the first clock generator 12 .

[0031] Specifically, a phase-locked loop (PLL) circuit is integrated into the deserializer. This PLL circuit phase-locks the local clock source from the first clock generator 12 to ensure that the deserializer's internal clock signal remains precisely synchronized with the input clock signal. This adjustment compensates for any clock signal errors caused by transmission or processing, thereby improving the system's clock accuracy and stability and ensuring precise synchronization of multiple deserializers during data processing.

[0032] Furthermore, as an implementation mode of the present invention, the first clock generator 12 sends out a plurality of first clock signals of the same source.

[0033] Specifically, the first clock generator 12 is capable of generating multiple homologous first clock signals. "Honogenous" means that these clock signals originate from the same clock source, and therefore have identical frequencies and phases. By issuing multiple homologous clock signals, the system ensures that all clock signals connected to different deserializers remain synchronized, which is crucial for data processing and transmission synchronization in multi-camera systems, further improving the overall stability and accuracy of the system.

[0034] Furthermore, as an implementation manner of the present utility model, the frequency of the first clock signal is set to 25 MHz.

[0035] Specifically, the frequency of the first clock signal can be set to 25 MHz. In this system, all clock signals generated by the first clock generator 12 and provided to the deserializer have a frequency of 25 MHz. The selection of 25 MHz as the clock frequency is based on the system's requirements for clock accuracy and synchronization, ensuring that the deserializer and its related components can operate efficiently and stably at this frequency, thereby achieving precise synchronization and data processing for the multi-camera system.

[0036] Furthermore, as an embodiment of the present invention, the deserializer includes a frame synchronization input pin, which is used to receive a frame synchronization signal emitted by the second clock generator 13; the frame synchronization signal is sent to the serializer through the reverse channel of the serial bus, and is sent to the image sensor through the output pin of the serializer.

[0037] Specifically, the deserializers are designed with a frame synchronization input pin for receiving a frame synchronization signal from the second clock generator 13. In this system, the frame synchronization signal is first generated by the second clock generator 13 and received by the frame synchronization input pins of the first and second deserializers 2 and 3. The frame synchronization signal is then sent to the serializers (such as the first serializer 4, the second serializer 5, the third serializer 6, and the fourth serializer 7) via the reverse channel of the serial bus. Finally, the serializers pass this synchronization signal to the image sensors via their output pins. This design ensures that all image sensors can capture images synchronously at the same time, thereby maintaining image frame synchronization in the multi-camera system and achieving highly accurate data synchronization.

[0038] Furthermore, as an implementation manner of the present invention, the frequency of the frame synchronization signal is consistent with the acquisition frequency of the image sensor.

[0039] Specifically, the frequency of the frame synchronization signal is aligned with the image sensor's acquisition frequency. During system operation, the frame synchronization signal frequency is precisely set to the same frequency as the image sensor's acquisition of image frames per second (e.g., 30Hz). This ensures that each image sensor begins capturing images at the correct time upon receiving the frame synchronization signal. This design ensures that all image sensors operate synchronously, avoiding image data asynchrony caused by frequency mismatches, thereby improving overall system synchronization and image data processing accuracy.

[0040] Furthermore, as an implementation manner of the present invention, the serializer includes an internal register, and the internal register is used to configure the frame synchronization signal.

[0041] Specifically, the serializer is designed with internal registers for configuring the frame synchronization signal. Within the system, the setting and adjustment of the frame synchronization signal can be controlled through these registers. By programming these registers, the behavior and parameters of the frame synchronization signal can be flexibly defined to ensure that they match the synchronization requirements of the image sensor. This design provides greater system flexibility and accuracy, allowing the frame synchronization signal to be precisely configured according to actual needs, further optimizing the synchronization performance of multi-camera systems.

[0042] Based on the above embodiments, the synchronization signals reaching the image sensors are all generated by the same signal from the second clock generator 13, and the source clocks used by the various deserializers are provided by the same first clock generator 12. This achieves clock synchronization of all links in hardware, thus achieving synchronization of all camera video frames.

[0043] Furthermore, as another embodiment of the present invention, the vehicle-mounted multi-camera synchronization system described in the present invention includes a central processor 1, the central processor 1 is data-connected to multiple deserializers, each deserializer is connected to an image sensor through a serializer, and each of the deserializers is signal-connected to the same third clock generator 14, wherein the third clock generator 14 is used to provide a local clock source for each deserializer and to provide a frame synchronization signal for each image sensor.

[0044] Specifically, refer to Figure 3 Multiple deserializers and image sensors in the system are synchronized via a single third clock generator 14. In this system, a central processing unit (SoC) 1 is connected to a first deserializer 2 and a second deserializer 3. Each deserializer is connected to multiple image sensors via a serializer. The third clock generator 14 is responsible for generating and providing two important clock signals: a local clock source (e.g., 25MHz) that synchronizes the operating frequency of all deserializers; and a frame synchronization signal (FSYNC) that ensures that all image sensors begin capturing images at the same time. This unified clock management ensures highly synchronized image data captured from different cameras, providing a precise foundation for subsequent data processing and fusion. Using a single third clock generator 14 for synchronization simplifies the system architecture and reduces hardware installation space compared to using two clock generators.

[0045] Furthermore, as an implementation manner of the present invention, the third clock generator 14 includes a frequency divider and / or a phase-locked loop circuit, which is used to generate the local clock source and / or the frame synchronization signal.

[0046] Specifically, the third clock generator 14 integrates a frequency divider and / or a phase-locked loop circuit. These circuits are used to generate a local clock source and / or frame synchronization signal. The frequency divider is used to divide a high-frequency clock signal into lower-frequency clock signals to meet the clock requirements of different parts of the system; the phase-locked loop circuit is used to stabilize and adjust the phase and frequency of the clock signal to ensure precise synchronization of the clock signal. By combining these circuits, the third clock generator 14 can flexibly and accurately generate a variety of clock signals that meet the requirements of the deserializer and image sensor, thereby further improving the synchronization performance and stability of the system.

[0047] As the number of cameras increases, the number of deserializers will also increase. Through the synchronization system described in the utility model, one or two clock generators are used instead of multiple crystal oscillators to provide local clocks for the deserializers, reducing component costs, PCB area costs, etc.

[0048] The embodiment of the utility model also discloses a vehicle.

[0049] A vehicle equipped with the on-board multi-camera synchronization system described in any one of the aforementioned embodiments. By configuring the system, the vehicle is equipped with high-precision multi-camera synchronization capabilities. Unified clock management ensures that the on-board camera systems maintain high synchronization when acquiring and processing image data, thereby providing more accurate and reliable perception data support for vehicle functions such as intelligent driving, assisted driving, and surround view monitoring.

[0050] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A vehicle-mounted multi-camera synchronization system, comprising a central processing unit (CPU), wherein the CPU is data-connected to a plurality of deserializers, each deserializer being connected to an image sensor via a serializer, characterized in that: Each of the deserializers is signal-connected to the same first clock generator, and each of the deserializers is signal-connected to the same second clock generator; wherein the first clock generator is used to provide a local clock source for each deserializer, and the second clock generator is used to provide a frame synchronization signal for each image sensor.

2. The vehicle-mounted multi-camera synchronization system according to claim 1, characterized in that: The deserializer includes a phase-locked loop circuit, which is used to perform phase-locked adjustment on a local clock source sent by the first clock generator.

3. The vehicle-mounted multi-camera synchronization system according to claim 2, characterized in that: The first clock generator generates a plurality of first clock signals of the same source.

4. The vehicle-mounted multi-camera synchronization system according to claim 3, characterized in that: The frequency of the first clock signal is set to 25 MHz.

5. The vehicle-mounted multi-camera synchronization system according to claim 1, characterized in that: The deserializer includes a frame synchronization input pin, which is used to receive a frame synchronization signal emitted by the second clock generator; the frame synchronization signal is sent to the serializer through the reverse channel of the serial bus, and is sent to the image sensor through the output pin of the serializer.

6. The vehicle-mounted multi-camera synchronization system according to claim 5, characterized in that: The frequency of the frame synchronization signal is consistent with the acquisition frequency of the image sensor.

7. The vehicle-mounted multi-camera synchronization system according to claim 1 or 5, characterized in that: The serializer includes an internal register, and the internal register is used to configure the frame synchronization signal.

8. A vehicle-mounted multi-camera synchronization system, comprising a central processing unit (CPU), wherein the CPU is data-connected to a plurality of deserializers, each deserializer being connected to an image sensor via a serializer, characterized in that: Each of the deserializers is signal-connected to the same third clock generator, wherein the third clock generator is used to provide a local clock source for each deserializer and to provide a frame synchronization signal for each image sensor.

9. The vehicle-mounted multi-camera synchronization system according to claim 8, characterized in that: The third clock generator includes a frequency divider or a phase-locked loop circuit, which is used to generate the local clock source or the frame synchronization signal.

10. A vehicle, characterized in that: The vehicle is equipped with the vehicle-mounted multi-camera synchronization system according to any one of claims 1 to 7 or claims 8 to 9.

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