High and low voltage MOS structure

Abstract

The utility model provides a high-low voltage MOS structure comprising a low voltage region provided with a low voltage well region and a high voltage region provided with a high voltage well region. The low-voltage MOS device in the low-voltage region comprises a thin gate oxide layer and a low-voltage side grid electrode which are stacked, and low-voltage side source / drain regions located on the two sides of the low-voltage side grid electrode; the high-voltage MOS device in the high-voltage region comprises a high-voltage side gate oxide layer and a high-voltage side grid electrode which are stacked; the first drift region and the second drift region are located in the high-voltage well region; a high-voltage side source region and a high-voltage side drain region are arranged in the first drift region and the second drift region respectively, and the high-voltage side source region and the high-voltage side drain region are located on two sides of the high-voltage side gate oxide layer respectively; the high-voltage side gate oxide layer comprises a first field oxide layer, a thick gate oxide layer and a second field oxide layer which are sequentially overlapped along the gate length direction, the thickness of the thick gate oxide layer is greater than that of the thin gate oxide layer, and the thicknesses of the first and second field oxide layers are greater than that of the thick gate oxide layer. According to the design of the high-voltage side gate oxide layer, the implantation dose and depth of the source / drain region can be accurately controlled, and the electrical performance and reliability of a product are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a high-low voltage MOS structure. Background Art

[0002] MOS (Metal-Oxide-Semiconductor), short for Metal-Oxide-Semiconductor Field-Effect Transistor, is a common semiconductor device used for amplification, impedance conversion, variable resistance, electronic switching, and other applications. Based on their operating voltage, MOS devices can be categorized as high-voltage MOS devices and low-voltage MOS devices. A high- and low-voltage MOS structure integrates high- and low-voltage MOS devices on the same semiconductor substrate. To simplify processing, the structures of high- and low-voltage MOS devices are similar. One of the most significant differences between the two is the gate oxide layer: the gate oxide layer of the low-voltage MOS device is thinner, while the gate oxide layer of the high-voltage MOS device is thicker, achieving different voltage withstand capabilities.

[0003] However, according to existing processes, when the gate oxide thickness difference between the low-voltage MOS device and the high-voltage MOS device is large, for example, the gate oxide thickness of the 5V low-voltage MOS device is about 120 angstroms, and the gate oxide thickness of the 40V high-voltage MOS device is about 550 angstroms, a difference of about 430 angstroms, the difference in the thickness of the silicon oxide residual film after etching will inevitably be large during the process of manufacturing the polysilicon gate. This will not only cause the implantation dose and implantation depth of the source / drain region to deviate from the target values, but also affect the electrical performance and reliability of the high and low voltage MOS structures. Utility Model Content

[0004] In order to overcome the above-mentioned defects, the present invention provides a high- and low-voltage MOS structure, which can effectively solve the above-mentioned problem caused by the large difference in residual film thickness between low-voltage MOS devices and high-voltage MOS devices after polysilicon etching, and improve the electrical performance and reliability of the high- and low-voltage MOS structure.

[0005] The high and low voltage MOS structure provided by the utility model includes:

[0006] A substrate comprising a low-pressure region and a high-pressure region, wherein a low-pressure well region is provided in the low-pressure region and a high-pressure well region is provided in the high-pressure region, wherein both the low-pressure well region and the high-pressure well region extend from a surface of one side of the substrate into the substrate, and the low-pressure well region and the high-pressure well region are spaced apart from each other;

[0007] A low-voltage MOS device located in a low-voltage region comprises a thin gate oxide layer and a low-voltage side gate stacked on the surface of a low-voltage well region, and a low-voltage side source region and a low-voltage side drain region located in the low-voltage well region, wherein the low-voltage side source region and the low-voltage side drain region are respectively located on both sides of the low-voltage side gate;

[0008] A high-voltage MOS device located in a high-voltage region comprises: a high-voltage side gate oxide layer and a high-voltage side gate stacked on the surface of a high-voltage well region; a first drift region and a second drift region disposed in the high-voltage well region, with a channel region between the two drift regions; a high-voltage side source region located in the first drift region, and a high-voltage side drain region located in the second drift region, wherein the high-voltage side source region and the high-voltage side drain region are respectively located on both sides of the high-voltage side gate oxide layer;

[0009] Among them, the above-mentioned high-voltage side gate oxide layer includes a first field oxide layer, a thick gate oxide layer and a second field oxide layer which are arranged in sequence and overlap along the gate length direction, the thickness of the thick gate oxide layer is greater than the thickness of the thin gate oxide layer, the thickness of the first field oxide layer is greater than the thickness of the thick gate oxide layer, and the thickness of the second field oxide layer is greater than the thickness of the thick gate oxide layer; the orthographic projection of the high-voltage side gate on the substrate surface is located within the orthographic projection of the high-voltage side gate oxide layer on the substrate surface.

[0010] Furthermore, in the above-mentioned high and low voltage MOS structure, the first field oxide layer and the second field oxide layer are symmetrically arranged with respect to the center line of the high voltage side gate along the gate width direction.

[0011] Furthermore, in the above-mentioned high-low voltage MOS structure, the high-voltage side gate covers a thick gate oxide layer and extends to both sides along the gate length direction to partially cover the first field oxide layer and partially cover the second field oxide layer.

[0012] Furthermore, in the above-mentioned high and low voltage MOS structure, the orthographic projection of the thick gate oxide layer on the substrate surface partially overlaps with the orthographic projection of the first drift region on the substrate surface; the orthographic projection of the thick gate oxide layer on the substrate surface partially overlaps with the orthographic projection of the second drift region on the substrate surface.

[0013] Furthermore, in the above-mentioned high and low voltage MOS structure, the orthographic projection of the thick gate oxide layer on the substrate surface does not overlap with the orthographic projection of the high-voltage side source region on the substrate surface; the orthographic projection of the thick gate oxide layer on the substrate surface does not overlap with the orthographic projection of the high-voltage side drain region on the substrate surface.

[0014] Furthermore, in the above-mentioned high-low voltage MOS structure, a first doped region is provided in the low-voltage well region, the doping type of the first doped region is consistent with the doping type of the low-voltage well region, and the doping concentration of the first doped region is greater than the doping concentration of the low-voltage well region; the first doped region extends from the substrate surface into the substrate, and the orthographic projection of the first doped region on the substrate surface is annular and surrounds the low-voltage side source region and the low-voltage side drain region;

[0015] A second doped region is provided in the high-voltage well region, the doping type of the second doped region is consistent with the doping type of the high-voltage well region, and the doping concentration of the second doped region is greater than the doping concentration of the high-voltage well region; the second doped region extends from the substrate surface into the substrate, and the orthographic projection of the second doped region on the substrate surface is annular and surrounds the first drift region, the second drift region and the channel region.

[0016] Furthermore, in the above-mentioned high-low voltage MOS structure, a third field oxide layer is further provided on the surface of the low-voltage well region. The projection of the third field oxide layer on the substrate surface is annular and is located inside the orthographic projection of the first doped region on the substrate surface, and surrounds the low-voltage side source region and the low-voltage side drain region.

[0017] A fourth field oxide layer is also provided on the surface of the high-voltage well region. The projection of the fourth field oxide layer on the substrate surface is annular and is located inside the positive projection of the second doped region on the substrate surface, and surrounds the first drift region, the second drift region and the channel region.

[0018] Furthermore, the above-mentioned high-low voltage MOS structure further includes an isolation structure, which isolates the low-voltage well region from the high-voltage well region.

[0019] Furthermore, in the above-mentioned high-low voltage MOS structure, the isolation structure includes an isolation region located in the high voltage region, and the high voltage well region is located in the isolation region.

[0020] Furthermore, in the above-mentioned high-low voltage MOS structure, the isolation structure further includes a fifth field oxide layer, and the fifth field oxide layer is located at the junction of the low voltage region and the high voltage region.

[0021] Furthermore, in the above-mentioned high-low voltage MOS structure, a sixth field oxide layer is further provided on the surface of the high-voltage well region, and the sixth field oxide layer is located between the isolation region and the high-voltage well region.

[0022] The utility model provides a high- and low-voltage MOS structure, in which the high-voltage side gate oxide layer is located between the high-voltage side source region and the high-voltage side drain region, and includes a first field oxide layer, a thick gate oxide layer, and a second field oxide layer that are overlapped along the gate length direction. The high-voltage side gate oxide layer is located between the high-voltage side source region and the high-voltage side drain region, rather than covering the entire high-voltage well region. Therefore, in the subsequent process of manufacturing a polysilicon gate, after the polysilicon layer is formed, a thicker film layer exists in the region corresponding to the high-voltage side gate. When the polysilicon layer is etched to form the high-voltage side gate and the low-voltage side gate, the difference in residual film in other regions is small. In this way, when performing source / drain region implantation and possible LDD implantation, the implantation dose and depth can be controlled more accurately, thereby improving the electrical performance and reliability of the high- and low-voltage MOS structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The disclosure of the present invention will become more easily understood with reference to the accompanying drawings. Those skilled in the art will readily appreciate that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Furthermore, similar numbers in the drawings represent similar structures or regions, where:

[0024] Figure 1 It is a planar schematic diagram of an existing high and low voltage MOS structure;

[0025] Figure 2It is a plan view of a high and low voltage MOS structure according to an embodiment of the present utility model;

[0026] Figure 3 is a cross-sectional view of a high and low voltage MOS structure according to an embodiment of the present utility model;

[0027] Figures 4a to 4j is formed Figure 3 The structural schematic diagram corresponding to some process steps of the high and low voltage MOS structure shown. DETAILED DESCRIPTION

[0028] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, the following detailed description of specific embodiments of the present invention is provided in conjunction with the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0029] In the description of this utility model, the terms "first," "second," etc. are used solely for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the technical features indicated. Furthermore, in this utility model, unless otherwise expressly specified or limited, the terms "connected" and "connected" should be interpreted broadly, meaning, for example, directly connected or indirectly connected through an intermediary, unless otherwise expressly limited. Those skilled in the art will understand the specific meanings of these terms in this utility model based on the specific circumstances.

[0030] MOS devices require different gate voltages in different applications, requiring them to withstand different high and low voltages. High-voltage and low-voltage MOS devices are integrated on the same semiconductor substrate to form a high- and low-voltage MOS structure to meet the overall circuit's high and low voltage requirements. Low-voltage MOS devices have thinner gate oxides, while high-voltage MOS devices have thicker gate oxides to achieve differentiated voltage-withstanding capabilities.

[0031] Figure 1 It is a planar schematic diagram of an existing high and low voltage MOS structure, such as Figure 1 As shown, the high-low voltage MOS structure includes a low voltage MOS device on the left side of the substrate 10, a high voltage MOS device on the right side and an isolation region 21 for isolation.

[0032] Among them, the low-voltage MOS device includes a source region and a drain region (collectively referred to as the low-voltage side source / drain region 13a) located in the low-voltage well region 17a and a low-voltage side gate 11a (the gate dielectric layer is not shown here) located on the surface of the low-voltage well region 17a. In addition, a first doped region 20a is provided in the low-voltage well region 17a. The doping type of the first doped region 20a is consistent with the doping type of the low-voltage well region 17a, and is used to connect the source and the low-voltage well region 17a serving as the body region.

[0033] Similarly, the high-voltage MOS device includes a source region and a drain region (collectively referred to as the high-side source / drain region 13b) located within the high-voltage well region 17b, and a high-voltage gate 11b located on the surface of the high-voltage well region 17b. Furthermore, the high-voltage well region 17b also includes a second doped region 20b, a first drift region 15a, and a second drift region 15b. The second doped region 20b is used to connect the source electrode to the high-voltage well region 17b, which serves as the body region. The high-voltage drain region is located within the second drift region 15b, and the high-voltage source region is located within the first drift region 15a. This means that the high-voltage MOS device has a symmetrical structure, with the high-voltage gate as the center line of symmetry along the gate width.

[0034] Continue to see Figure 1 For high-voltage MOS devices, the entire surface of the high-voltage well region 17b is covered by an oxide layer 18', and the high-voltage side gate 11b is located on this oxide layer 18'. Therefore, during the subsequent polysilicon gate fabrication process, when the polysilicon layer is etched to simultaneously form the low-voltage side gate 11a and the high-voltage side gate 11b, the silicon oxide film in areas other than the area corresponding to the high-voltage well region 17b is relatively thin, resulting in a relatively thin residual film after polysilicon overetching. However, the silicon oxide film in the area corresponding to the high-voltage well region 17b is relatively thick, resulting in a relatively thick residual film after polysilicon overetching. If the gate oxide thickness of the low-voltage MOS device and the high-voltage MOS device differ significantly, the residual film thickness after polysilicon overetching will also differ significantly. This will not only cause the source / drain region implantation dose and implantation depth to deviate from the target values, but may also affect the LDD implantation dose and depth, thereby affecting the electrical performance and reliability of the high- and low-voltage MOS structures.

[0035] In order to solve the above technical problems, the present invention optimizes the existing high and low voltage MOS structures, which are described in detail below with reference to the accompanying drawings.

[0036] Figure 2 and Figure 3 They are respectively a plan view and a cross-sectional view of a high and low voltage MOS structure according to an embodiment of the present invention. Figures 2 to 3As shown, the high-low voltage MOS structure includes a substrate 10, which includes a low-voltage region L and a high-voltage region H, wherein a low-voltage well region 17a is provided in the low-voltage region L, and a high-voltage well region 17b is provided in the high-voltage region H. The low-voltage well region 17a and the high-voltage well region 17b both extend from the surface of one side of the substrate 10 (commonly known as the front side) to the surface of the other side of the substrate 10 (commonly known as the back side); this embodiment does not limit the depth of the low-voltage well region 17a and the high-voltage well region 17b to be consistent.

[0037] It should be noted that the "high-pressure area" and "low-pressure area" are named only for the convenience of expression and distinction to represent different areas; in addition, although the high-pressure area H is located on the right side of the low-pressure area L in the figure and the two are adjacent to each other, in practice they are not limited to this. The low-pressure area L can also be located in other directions of the high-pressure area H, and the two may not even be adjacent to each other.

[0038] The high-low voltage MOS structure provided in this embodiment includes a low-voltage MOS device located in the low-voltage region L and a high-voltage MOS device located in the high-voltage region H. The structure of the low-voltage MOS device is similar to that of the low-voltage MOS device in the existing high-low voltage MOS structure, including a low-voltage side source / drain region 13a located in the low-voltage well region 17a. The low-voltage side source / drain region 13a is a general term for the low-voltage side source region and the low-voltage side drain region, both of which extend from the surface of the low-voltage well region 17a into the low-voltage well region 17a. The channel region is located between the low-voltage side source region and the low-voltage side drain region. A thin gate oxide layer 12a and a low-voltage side gate 11a are stacked on the surface of the low-voltage well region 17a. The thin gate oxide layer 12a and the low-voltage side gate 11a are located between the low-voltage side source region and the low-voltage side drain region; in other words, the thin gate oxide layer 12a and the low-voltage side gate 11a cover the channel region.

[0039] A first doped region 20a is also provided in the low-voltage well region 17a. The doping type of the first doped region 20a is consistent with the doping type of the low-voltage well region 17a, and the doping concentration of the first doped region 20a is higher than the doping concentration of the low-voltage well region 17a. The first doped region 20a is used to electrically connect the source and the low-voltage well region 17a serving as the body region; the first doped region 20a extends a certain distance from the surface of the low-voltage well region 17a into the low-voltage well region 17a; the orthographic projection of the first doped region 20a on the surface of the substrate 10 is annular and surrounds the low-voltage side source / drain region 13a and the channel region.

[0040] A third field oxide layer 183 is also provided in the low-voltage region L to isolate the low-voltage side source / drain region 13a and the first doped region 20a. The orthographic projection of the third field oxide layer 183 on the surface of the substrate 10 is annular, and the orthographic projection of the first doped region 20a on the surface of the substrate 10 surrounds the orthographic projection of the third field oxide layer 183 on the surface of the substrate 10. The orthographic projection of the third field oxide layer 183 on the surface of the substrate 10 also surrounds the low-voltage side source / drain region 13a and the channel region.

[0041] In this embodiment, the low-voltage MOS device may further include sidewalls located on both sides of the low-voltage side gate 11a and an LDD region 22 located below the low-voltage side gate 11a and in the low-voltage well region 17a. The specific structures of the sidewalls and the LDD region 22 can be referred to in the prior art and will not be described in detail.

[0042] like Figure 2 and Figure 3 As shown, the high-voltage MOS device includes a first drift region 15a, a second drift region 15b, and a high-side source / drain region 13b located within a high-voltage well region 17b. The first drift region 15a, the second drift region 15b, and the high-side source / drain region 13b all extend from the surface of the high-voltage well region 17b into the high-voltage well region 17b. The first drift region 15a and the second drift region 15b are spaced apart, with the channel region formed between them. The doping type of the first drift region 15a and the second drift region 15b are consistent with that of the high-voltage well region 17b, and the doping concentration of the first drift region 15a and the second drift region 15b are both higher than that of the high-voltage well region 17b. The high-side source / drain region 13b collectively refers to the high-side source region and the high-side drain region. The high-side source region is located within the first drift region 15a, and the high-side drain region is located within the second drift region 15b. A high-voltage side gate oxide layer 18 is provided on the surface of the high-voltage well region 17b. The high-voltage side gate oxide layer 18 is located between the high-voltage side source region and the high-voltage side drain region. Specifically, the high-voltage side gate oxide layer 18 covers the channel region and extends to cover part of the drift region on both sides of the channel region; a high-voltage side gate 11b is provided on the high-voltage side gate oxide layer 18.

[0043] Different from the prior art, in this embodiment, the high-voltage side gate oxide layer 18 in the high-voltage MOS device only partially covers the high-voltage well region 17b. Specifically, according to the orthographic projection on the surface of the substrate 10, the high-voltage side gate oxide layer 18 is located between the high-voltage side source region and the high-voltage side drain region, and is located along the gate width direction (i.e., Figure 3 The direction perpendicular to the paper surface) exceeds the high-voltage side source region and the high-voltage side drain region.

[0044] Furthermore, the high-side gate oxide layer 18 includes a first field oxide layer 181, a thick gate oxide layer 12b, and a second field oxide layer 182. The three layers partially overlap in the gate length direction. That is, the first field oxide layer 181 and the second field oxide layer 182 are respectively located on either side of the thick gate oxide layer 12b. In a geometric sense, the first field oxide layer 181 and the thick gate oxide layer 12b extend into each other, and the second field oxide layer 182 and the thick gate oxide layer 12b extend into each other. The thickness of the first field oxide layer 181 and the second field oxide layer 182 are both greater than the thickness of the thick gate oxide layer 12b, and the thickness of the thick gate oxide layer 12b is greater than the thickness of the thin gate oxide layer 12a.

[0045] The high-side gate 11b is located on the surface of the high-side gate oxide layer 18, and the orthographic projection of the high-side gate 11b on the surface of the substrate 10 is located within the orthographic projection of the high-side gate oxide layer 18 on the surface of the substrate 10. Because the thickness of the first field oxide layer 181 and the second field oxide layer 182 is greater than the thickness of the thick gate oxide layer 12b, the high-side gate 11b forms a height difference, i.e., a step, in the area where the first field oxide layer 181, the second field oxide layer 182, and the thick gate oxide layer 12b overlap. In fact, the portion of the high-side gate 11b located above the first field oxide layer 181 and the second field oxide layer 182 acts as a field plate. When voltage is applied to the gate, the surface electric field of the substrate 10 can be dispersed, thereby improving the breakdown performance of the high-voltage MOS device.

[0046] In this embodiment, the high-voltage side gate 11b covers the thick gate oxide layer 12b and extends along the gate length direction to partially cover the first field oxide layer 181 and the second field oxide layer 182, that is, there is a certain distance between the high-voltage side gate 11b and the edge on the same side of the first field oxide layer 181, and there is a certain distance between the high-voltage side gate 11b and the edge on the same side of the second field oxide layer 182.

[0047] Further references Figure 2 and Figure 3 The orthographic projection of the high-side gate 11 b on the surface of the substrate 10 does not overlap with the orthographic projection of the high-side source / drain region 13 b on the surface of the substrate 10 .

[0048] Continue to see Figures 2 to 3 Since the first field oxide layer 181 and the second field oxide layer 182 set on both sides of the high-voltage side gate 11b extend beyond the high-voltage side gate 11b, and the thickness of the first field oxide layer 181 and the second field oxide layer 182 is greater than the thickness of the thick gate oxide layer 12b, side drilling will basically not occur during the process of wet etching to obtain the thick gate oxide layer 12b.

[0049] In a specific implementation process, the first field oxide layer 181 and the second field oxide layer 182 are symmetrically arranged along the center line of the high-voltage side gate along the gate width direction. In this way, when the gate is pressurized, the ability to disperse the surface electric field of the substrate 10 on the left and right sides is guaranteed to be consistent, thereby achieving a more uniform current distribution and improving the overall electrical performance and stability of the high and low voltage MOS structure.

[0050] Unless otherwise specified, in the description of this embodiment, the gate length direction refers to the direction from the source region to the drain region or from the drain region to the source region, that is, the gate length direction is consistent with the channel length direction; the gate width direction is perpendicular to the gate length direction, and both are perpendicular to the substrate thickness direction.

[0051] Further references Figure 2 and Figure 3The orthographic projection of the thick gate oxide layer 12b on the surface of the substrate 10 partially overlaps with the orthographic projection of the first drift region 15a on the surface of the substrate 10 and the orthographic projection of the second drift region 15b on the surface of the substrate 10; in other words, the thick gate oxide layer 12b covers the channel region and extends toward both sides to cover part of the drift region.

[0052] A second doped region 20b is also provided in the high-voltage well region 17b. The doping type of the second doped region 20b is consistent with the doping type of the high-voltage well region 17b, and the doping concentration of the second doped region 20b is higher than the doping concentration of the high-voltage well region 17b. It is used to connect the source and the high-voltage well region 17b serving as the body region; the second doped region 20b extends from the front surface of the substrate 10 into the substrate 10, and its orthographic projection on the surface of the substrate 10 is annular, surrounding the first drift region 15a, the second drift region 15b and the channel region located therebetween.

[0053] A fourth field oxide layer 184 is also provided in the high-voltage well region 17b to isolate the high-voltage side source / drain region 13b and the second doped region 20b. Specifically, the orthographic projection of the fourth field oxide layer 184 on the surface of the substrate 10 is annular; the orthographic projection of the second doped region 20b on the surface of the substrate 10 surrounds the orthographic projection of the fourth field oxide layer 184 on the surface of the substrate 10, and the orthographic projection of the fourth field oxide layer 184 on the surface of the substrate 10 surrounds the orthographic projection of the first drift region 15a, the second drift region 15b and the channel region located therebetween on the surface of the substrate 10, thereby separating the drift region from the second doped region 20b, and also separating the high-voltage side source / drain region 13b and the second doped region 20b.

[0054] In a specific implementation process, the first field oxide layer 181 , the second field oxide layer 182 , the third field oxide layer 183 and the fourth field oxide layer 184 are all formed by a LOCOS process, that is, the four can be formed in the same process flow.

[0055] An isolation structure may be provided between the low-voltage well region 17a and the high-voltage well region 17b. An appropriate isolation structure may be selected according to actual needs, thereby effectively isolating the high-voltage MOS device from the low-voltage MOS device, or isolating the high-voltage MOS device from other components. Figure 2 and Figure 3 In the embodiment shown, the high-voltage MOS device and the low-voltage MOS device are arranged adjacent to each other. In fact, in other embodiments, other semiconductor devices may also be provided between the high-voltage MOS device and the low-voltage MOS device. Therefore, the isolation structure can be selected according to actual isolation requirements.

[0056] In this embodiment, the isolation structure includes an isolation region 21 located within the high-voltage region H, and the high-voltage well region 17b is located within the isolation region 21. Specifically, the doping depth of the isolation region 21 is greater than the doping depth of the high-voltage well region 17b, and the orthographic projection of the high-voltage well region 17b on the surface of the substrate 10 is located within the orthographic projection of the isolation region 21 on the surface of the substrate 10. In addition, a sixth field oxide layer 186 may be provided on the surface of the substrate 20 between the isolation region 21 and the high-voltage well region 17b.

[0057] In addition, the isolation structure may further include a fifth field oxide layer 185, which at least covers the interface between the high voltage region H and the low voltage region L. In other embodiments, a suitable isolation method may be selected according to actual conditions, such as STI isolation.

[0058] In the high- and low-voltage MOS structure of this embodiment, from the perspective of the orthographic projection on the surface of the substrate 10, a first field oxide layer 181, a thick gate oxide layer 12b, and a second field oxide layer 182 are provided in the high-voltage well region 17b, which only surround the high-voltage side gate 11b. The first field oxide layer 181, the thick gate oxide layer 12b, and the second field oxide layer 182 are located between the high-voltage side source region and the high-voltage side drain region, rather than covering the entire high-voltage well region. In this way, in the subsequent process of manufacturing the polysilicon gate, after the polysilicon layer is formed, only the area corresponding to the high-voltage side gate 11b has a relatively thick film layer (excluding the field oxide layer). When the polysilicon layer is etched to form the high- and low-voltage side gates, the difference in the residual silicon oxide film in other areas is relatively small. In this way, when performing source / drain region implantation and possible LDD implantation, the implantation dose and depth can be controlled more accurately, thereby improving the electrical performance and reliability of the high- and low-voltage MOS structure.

[0059] It should be noted that for Figure 1 In the conventional structure shown, since the oxide layer 18' covers the entire high-voltage well region 17b, during the subsequent self-aligned silicide (Salicide) process, the deposited metal silicide barrier layer is subjected to photolithography and etching to expose the silicon and polysilicon regions of the substrate 10 where the Salicide is to be formed. The following problem is likely to occur: after the metal silicide barrier layer in the region corresponding to the low-voltage well region 17a is completely etched to expose the silicon surface, the region corresponding to the high-voltage well region 17b still needs to be etched further because the residual film after polysilicon etching is relatively thick and the silicon substrate surface has not yet been exposed. This will cause damage to the silicon substrate surface in the region corresponding to the low-voltage well region 17a, thereby causing degradation of the performance of the low-voltage MOS device, reduced reliability, or even failure.

[0060] The high and low voltage MOS structure provided in this embodiment eliminates the difference in residual film between the area corresponding to the high voltage well region 17b and other areas outside the field oxide layer when etching the polysilicon layer to form the high voltage side gate 11b and the low voltage side gate 11a, so that the metal silicide barrier layer in other areas can be etched at the same time and the silicon surface is exposed, thereby avoiding the impact on the performance and reliability of the low voltage MOS device.

[0061] The following combination Figures 4a to 4j Pair formation Figure 2-3 Some process steps of the high and low voltage MOS structures are described in detail.

[0062] S1, an isolation region 21 and a high-voltage well region 17b are formed in the high-voltage region H of the substrate 10, wherein the high-voltage well region 17b is located in the region defined by the isolation region 21, as shown in FIG. Figure 4a shown.

[0063] The substrate 10 may be a silicon substrate or other suitable material. The substrate 10 includes a high-voltage region H and a low-voltage region L. The high-voltage region H and the low-voltage region L are for convenience only and represent the regions for fabricating high-voltage MOS devices and low-voltage MOS devices, respectively. The regions may be adjacent or non-adjacent. The isolation region 21 may be formed by ion implantation, with the specific doping concentration and type determined by the desired isolation effect. The doping type of the high-voltage well region 17b is the same as that of the substrate 10, and the doping concentration of the high-voltage well region 17b is higher than that of the substrate 10.

[0064] S2. By photolithography and ion implantation, a first drift region 15a and a second drift region 15b are formed in the high-voltage well region 17b. Figure 4b As shown, the ion implantation depths of the first drift region 15a and the second drift region 15b are both smaller than the ion implantation depth of the high-voltage well region 17b, and the region between the two drift regions is the channel region of the high-voltage MOS device. Figure 2 and Figure 3 As shown, to ensure uniform current distribution, the first drift region 15a and the second drift region 15b are symmetrically arranged along the center line of the high-voltage side gate 11b to be formed later along the gate width direction. The doping type of the above two drift regions is consistent with the doping type of the high-voltage well region 17b, and the doping concentration of both drift regions is higher than the doping concentration of the high-voltage well region 17b.

[0065] S3, depositing silicon nitride or other hard mask material on the surface of the substrate 10 and patterning it, then using thermal oxidation to grow a thick oxide layer in the area not covered by the hard mask material, then removing the hard mask material to form a silicon nitride or other hard mask material on the surface of the substrate 10. Figure 4c The LOCOS structure shown.

[0066] The thick oxide layer at the junction of the low-voltage region L and the high-voltage region H, namely the fifth field oxide layer 185, also serves as an isolation structure. In other embodiments, isolation methods such as STI can also be used at the junction between the two. In addition, in the structure shown in this embodiment, the low-voltage region L and the high-voltage region H are adjacent, but this is not limited to this.

[0067] The projection of the third field oxide layer 183 on the surface of the substrate 10 is annular in the thick oxide layer of the low-voltage area L and is also located in the subsequently formed low-voltage well area 17a, for isolating the subsequently formed first doped area 20a and the low-voltage side source / drain area 13a.

[0068] In the thick oxide layer located in the high-voltage region H, a first field oxide layer 181 corresponds to the first drift region 15a, and a second field oxide layer 182 corresponds to the second drift region 15b. In the thick oxide layer surrounding the first and second field oxide layers 181 and 182, in order from inside to outside (or from near to far), the fourth field oxide layer 184 is used to isolate the subsequently formed second doped region 20b and the high-side source / drain region 13b. The sixth field oxide layer 186 is located between the high-voltage well region 17b and the isolation region 21. The outermost thick oxide layer is the seventh field oxide layer 187. The projection of the seventh field oxide layer 187 on the surface of the substrate 10 is annular. Part of the projection of the seventh field oxide layer 187 on the surface of the substrate 10 is located within the low-voltage region L, while the other part is located within the high-voltage region H. The projection surrounds the low-voltage well region 17a, the high-voltage well region 17b, and the isolation region 21. Of course, in this embodiment, since the high-voltage region H and the low-voltage region L are adjacent to each other, the seventh field oxide layer 187 is annular; in other embodiments, if the two are not adjacent, it can be selected whether to set the seventh field oxide layer 187 according to the situation, and the shape of the seventh field oxide layer 187 can also be changed.

[0069] S4, by photolithography and ion implantation, a low-voltage well region 17a is formed in the low-voltage region L of the substrate 10, as shown in FIG. Figure 4d As shown. The ion doping type of the low-voltage well region 17a is the same as the doping type of the substrate 10, and the doping concentration of the low-voltage well region 17a is higher than the doping concentration of the substrate 10. The low-voltage well region 17a is spaced apart from the isolation region 21, and the fifth field oxide layer 185 is separated therefrom. The ion implantation depth of the low-voltage well region 17a can be lower than the ion implantation depth of the high-voltage well region 17b.

[0070] S5, first gate oxide layer growth: the first gate oxide layer is grown by thermal oxidation method, such as wet oxygen oxidation, as shown in FIG. Figure 4e The thickness of the first gate oxide layer is greater than the target thickness of the thin gate oxide layer 12a and less than the thickness of the thick gate oxide layer 12b. For example, if the target thickness of the thick gate oxide layer 12b is 550±50 angstroms, the thickness of the first gate oxide layer can be 480-490 angstroms.

[0071] After step S5, the entire surface of substrate 10 is covered with an oxide layer, including the first gate oxide layer formed in this step and the LOCOS field oxide layer formed in step S4. That is, the patterns of the two oxide layers are complementary. Because the thickness of the LOCOS layer is much greater than the thickness of the first gate oxide layer, the diffusion rate of the oxidant in the LOCOS field oxide layer during the growth of the first gate oxide layer is relatively slow. Therefore, the effect of the growth of the first gate oxide layer on the thickness of the LOCOS field oxide layer can be ignored.

[0072] S6, forming a patterned photoresist layer on the first gate oxide layer, such as Figure 4f The patterned photoresist layer is used to define the thick gate oxide layer 12b located on the surface of the high-voltage well region 17b.

[0073] S7, wet-etch the oxide layer not covered by the photoresist layer. Using the patterned photoresist layer as a mask, wet-etch the first gate oxide layer and the LOCOS field oxide layer to remove the first gate oxide layer not covered by the photoresist layer. Since the thickness of LOCOS is much greater than that of the first gate oxide layer, after wet etching, the thickness of the LOCOS structure is reduced but still retained, eventually forming the following Figure 4g The structure shown in FIG. 1 is then completely removed from the patterned photoresist layer to form a Figure 4h The structure shown in FIG. It is easy to understand that the remaining first gate oxide layer partially overlaps with the first field oxide layer 181 and the second field oxide layer 182 on either side thereof, and the three form a whole. In addition, since the first field oxide layer 181 and the second field oxide layer 182 are provided on either side of the remaining first gate oxide layer, undercutting will not occur on either side of the first gate oxide layer during the wet etching process.

[0074] S8, grow the gate oxide layer for the second time to form Figure 4i The structure shown. Through the second gate oxide layer growth, the thickness of the oxide layer partially overlapping the first field oxide layer 181 and the second field oxide layer 182 is increased to the target value, forming the thick gate oxide layer 12b. The thick gate oxide layer 12b, the first field oxide layer 181, and the second field oxide layer 182 remain an integral structure, serving as the high-side gate oxide layer 18. The second gate oxide layer located in the low-voltage well region 17a is subsequently patterned to serve as the thin gate oxide layer 12a.

[0075] In one specific implementation, both gate oxide layers are grown using a thermal oxidation process, such as wet oxygen oxidation. By controlling the reaction conditions of the wet oxygen oxidation, such as temperature, pressure, and oxidant composition, the growth rate and thickness of the two gate oxide layers can be precisely controlled. These conditions can be independently optimized during both growth processes to ensure that the thickness of the gate oxide layer grown each time meets the desired value. By superimposing the thickness of the two grown gate oxide layers, the thickness of the thick gate oxide layer 12b in the high-voltage well region 17b can be precisely controlled to, for example, 550±50 angstroms. The gate oxide layer thickness in the low-voltage well region 17a can be precisely controlled to 120±10 angstroms through a single wet oxygen oxidation growth, ultimately achieving effective control of the performance of both high-voltage and low-voltage MOS devices. Furthermore, because the thickness of the LOCOS structure is much greater than the gate oxide layer thickness, the diffusion rate of the oxidant in the LOCOS structure is relatively slow during the second gate oxide layer growth. Therefore, the effect of the growing gate oxide layer on the LOCOS thickness is negligible.

[0076] S9, depositing a polysilicon layer on the surface of the substrate 10, and patterning the polysilicon layer to obtain the gate of the device, including the high-voltage side gate 11b and the low-voltage side gate 11a, as shown in FIG. Figure 4j shown.

[0077] It should be noted that, in order to ensure that the polysilicon layer is completely etched, an over-etching method is usually required during the etching process, that is, etching a portion of the oxide layer under the polysilicon layer.

[0078] S10, perform LDD implantation, sidewall implantation, and source / drain implantation. During the above ion implantation process, the thickness of the second oxide layer is relatively low, which can be used as a barrier layer to avoid the tunnel effect. After the ion implantation is completed, the excess second oxide layer is removed, and finally the Figure 3 The high and low voltage MOS structures shown in the figure, wherein these processes can refer to the existing related technologies and will not be described in detail here.

[0079] S11: Perform the Salicide process. First, a metal silicide barrier layer is deposited. After photolithography and etching, the substrate silicon and polysilicon areas where the Salicide layer is to be formed are exposed. The Salicide process can refer to existing related technologies and will not be described in detail here.

[0080] In the above steps, due to the design of step S8, except for the high-voltage side gate oxide layer 18 and the LOCOS structure, the thickness of the oxide layer in the remaining areas is consistent, that is, the thickness of the second gate oxide layer is consistent, so that after the polysilicon layer is over-etched (step S9), the difference in the thickness of the residual oxide layer after etching can be effectively controlled. In this way, in the subsequent steps, especially the ion implantation process, the dose and concentration of the ion implantation are effectively controlled, so that the ion implantation effect is consistent with the expectation, close to or even reaches the target value, and ultimately the performance of the high and low voltage MOS devices is guaranteed.

[0081] Moreover, during the Salicide process, since there is no difference in the residual oxide film between the high and low voltage well regions after polysilicon etching, after the metal silicide barrier layer of the low voltage well region 17a is etched to expose the surface of the substrate 10, the metal silicide barrier layer of the high voltage well region 17b is also etched to expose the surface of the substrate 10. Therefore, the design of the high and low voltage MOS structure can effectively avoid the performance degradation problem of the low voltage MOS device caused by the difference in residual film after etching.

[0082] Thus far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will fall within the scope of protection of the present invention.

Claims

1. A high and low voltage MOS structure, characterized in that: include: A substrate comprising a low-pressure region and a high-pressure region, wherein a low-pressure well region is provided in the low-pressure region and a high-pressure well region is provided in the high-pressure region, wherein both the low-pressure well region and the high-pressure well region extend from a surface of one side of the substrate into the substrate, and the low-pressure well region and the high-pressure well region are spaced apart from each other; A low-voltage MOS device located in the low-voltage region comprises a thin gate oxide layer and a low-voltage side gate stacked on the surface of the low-voltage well region, and a low-voltage side source region and a low-voltage side drain region located in the low-voltage well region, wherein the low-voltage side source region and the low-voltage side drain region are respectively located on both sides of the low-voltage side gate; The high-voltage MOS device located in the high-voltage region includes: a high-voltage side gate oxide layer and a high-voltage side gate stacked on the surface of the high-voltage well region; a first drift region and a second drift region arranged in the high-voltage well region, with a channel region between the first drift region and the second drift region; a high-voltage side source region located in the first drift region, and a high-voltage side drain region located in the second drift region, wherein the high-voltage side source region and the high-voltage side drain region are respectively located on both sides of the high-voltage side gate oxide layer; In which, the high-voltage side gate oxide layer includes a first field oxide layer, a thick gate oxide layer and a second field oxide layer which are overlapped in sequence along the gate length direction, the thickness of the thick gate oxide layer is greater than the thickness of the thin gate oxide layer, and the thickness of the first field oxide layer and the thickness of the second field oxide layer are both greater than the thickness of the thick gate oxide layer; the orthographic projection of the high-voltage side gate on the substrate surface is located within the orthographic projection of the high-voltage side gate oxide layer on the substrate surface.

2. The high and low voltage MOS structure according to claim 1, characterized in that: The first field oxide layer and the second field oxide layer are symmetrically arranged about a center line of the high-voltage side gate along a gate width direction.

3. The high and low voltage MOS structure according to claim 1, characterized in that: The high-voltage side gate covers the thick gate oxide layer and extends toward both sides along the gate length direction to partially cover the first field oxide layer and the second field oxide layer.

4. The high and low voltage MOS structure according to any one of claims 1 to 3, characterized in that: The orthographic projection of the thick gate oxide layer on the substrate surface partially overlaps with the orthographic projection of the first drift region on the substrate surface; the orthographic projection of the thick gate oxide layer on the substrate surface partially overlaps with the orthographic projection of the second drift region on the substrate surface.

5. The high and low voltage MOS structure according to any one of claims 1 to 3, characterized in that: The orthographic projection of the thick gate oxide layer on the substrate surface does not overlap with the orthographic projection of the high-voltage side source region on the substrate surface; the orthographic projection of the thick gate oxide layer on the substrate surface does not overlap with the orthographic projection of the high-voltage side drain region on the substrate surface.

6. The high and low voltage MOS structure according to any one of claims 1 to 3, characterized in that: A first doped region is provided in the low-voltage well region, wherein the doping type of the first doped region is consistent with the doping type of the low-voltage well region, and the doping concentration of the first doped region is greater than the doping concentration of the low-voltage well region; the first doped region extends from the substrate surface into the substrate, and the orthographic projection of the first doped region on the substrate surface is annular and surrounds the low-voltage side source region and the low-voltage side drain region; A second doped region is provided in the high-voltage well region, the doping type of the second doped region is consistent with the doping type of the high-voltage well region, and the doping concentration of the second doped region is greater than the doping concentration of the high-voltage well region; the second doped region extends from the substrate surface into the substrate, and the orthographic projection of the second doped region on the substrate surface is annular and surrounds the first drift region, the second drift region and the channel region.

7. The high and low voltage MOS structure according to claim 6, characterized in that: A third field oxide layer is further provided on the surface of the low-voltage well region. The projection of the third field oxide layer on the substrate surface is annular and is located inside the orthographic projection of the first doped region on the substrate surface, and surrounds the low-voltage side source region and the low-voltage side drain region. A fourth field oxide layer is also provided on the surface of the high-voltage well region. The projection of the fourth field oxide layer on the substrate surface is annular and is located on the inner side of the positive projection of the second doped region on the substrate surface, and surrounds the first drift region, the second drift region and the channel region.

8. The high-low voltage MOS structure according to any one of claims 1 to 3, characterized in that: The system also includes an isolation structure, which isolates the low-voltage well region from the high-voltage well region.

9. The high and low voltage MOS structure according to claim 8, characterized in that: The isolation structure includes an isolation region located in the high voltage region, and the high voltage well region is located in the isolation region.

10. The high and low voltage MOS structure according to claim 9, characterized in that: The isolation structure further includes a fifth field oxide layer, and the fifth field oxide layer is located at the junction of the low voltage region and the high voltage region.

11. The high and low voltage MOS structure according to claim 9, characterized in that: A sixth field oxide layer is further provided on the surface of the high-voltage well region, and the sixth field oxide layer is located between the isolation region and the high-voltage well region.

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